AD ADN2530YCPZ

11.3 Gbps, Active Back-Termination,
Differential VCSEL Driver
ADN2530
FEATURES
GENERAL DESCRIPTION
Up to 11.3 Gbps operation
−40°C to +100°C operation
Very low power: ISUPPLY = 65 mA
Typical 26 ps rise/fall times
Full back-termination of output transmission lines
Crosspoint adjust function
PECL-/CML-compatible data inputs
Bias current range: 2 mA to 25 mA
Differential modulation current range: 2.2 mA to 23 mA
Automatic laser shutdown (ALS)
3.3 V operation
Compact 3 mm × 3 mm LFCSP
Voltage-input control for bias and modulation currents
XFP-compliant bias current monitor
The ADN2530 laser diode driver is designed for direct modulation of packaged VCSELs with a differential resistance ranging
from 35 Ω to 140 Ω. The active back-termination technique
provides excellent matching with the output transmission lines
while reducing the power dissipation in the output stage. The
back-termination in the ADN2530 absorbs signal reflections
from the TOSA end of the output transmission lines, enabling
excellent optical eye quality to be achieved even when the
TOSA end of the output transmission lines is significantly
misterminated. The small package provides the optimum
solution for compact modules where laser diodes are packaged
in low pin count optical subassemblies.
The modulation and bias currents are programmable via the
MSET and BSET control pins. By driving these pins with
control voltages, the user has the flexibility to implement
various average power and extinction ratio control schemes,
including closed-loop control and look-up tables. The eye
crosspoint in the output eye diagram is adjustable via the
crosspoint adjust (CPA) control voltage input. The automatic
laser shutdown (ALS) feature allows the user to turn on/off the
bias and modulation currents by driving the ALS pin with the
proper logic levels. The product is available in a space-saving
3 mm × 3 mm LFCSP specified from −40°C to +100°C.
APPLICATIONS
10 Gb Ethernet optical transceivers
10G-BASE-LRM optical transceivers
8× and 10× Fibre Channel optical transceivers
XFP/X2/XENPAK/MSA 300 optical modules
SONET OC-192/SDH STM-64 optical transceivers
FUNCTIONAL BLOCK DIAGRAM
VCC
CPA
ALS
VCC
ADN2530
VCC
50Ω
IMODP
50Ω
100Ω
IMOD
IMODN
GND
DATAP
VCC
CROSS
POINT
ADJUST
DATAN
IBMON
IBIAS
800Ω
200Ω
200Ω
MSET
GND
BSET
200Ω
10Ω
05457-001
800Ω
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADN2530
TABLE OF CONTENTS
Features .............................................................................................. 1
Automatic Laser Shutdown (ALS) ........................................... 11
Applications....................................................................................... 1
Modulation Current................................................................... 11
General Description ......................................................................... 1
Load Mistermination ................................................................. 13
Functional Block Diagram .............................................................. 1
Crosspoint Adjust....................................................................... 13
Revision History ............................................................................... 2
Power Consumption .................................................................. 13
Specifications..................................................................................... 3
Applications Information .............................................................. 15
Package Thermal Specifications ................................................. 4
Typical Application Circuit....................................................... 15
Absolute Maximum Ratings............................................................ 5
Layout Guidelines....................................................................... 15
ESD Caution.................................................................................. 5
Design Example.......................................................................... 16
Pin Configuration and Function Descriptions............................. 6
Headroom Calculations ........................................................ 16
Typical Performance Characteristics ............................................. 7
BSET and MSET Pin Voltage Calculation .......................... 16
Theory of Operation ...................................................................... 10
IBIAS Monitor Accuracy Calculations................................ 17
Input Stage................................................................................... 10
Outline Dimensions ....................................................................... 18
Bias Current ................................................................................ 10
Ordering Guide .......................................................................... 18
REVISION HISTORY
8/06—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Table 3............................................................................ 5
Changes to Figure 24...................................................................... 10
Changes to Figure 30...................................................................... 11
Changes to Modulation Current Section .................................... 12
Changes to Typical Application Circuit Section......................... 15
10/05—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADN2530
SPECIFICATIONS
VCC = VCCMIN to VCCMAX, TA = −40°C to +100°C, 100 Ω differential load impedance, crosspoint adjust disabled, unless otherwise noted.
Typical values are specified at 25°C and IMOD = 10 mA with crosspoint adjust disabled, unless otherwise noted.
Table 1.
Parameter
BIAS CURRENT (IBIAS)
Bias Current Range
Bias Current While ALS Asserted
Compliance Voltage 1
MODULATION CURRENT (IMODP, IMODN)
Modulation Current Range
Modulation Current While ALS Asserted
Crosspoint Adjust (CPA) Range 2
Rise Time (20% to 80%)2, 3, 4
Min
2
0.55
0.55
2.2
2.2
35
26
26.4
26
26.5
<0.5
<0.5
5.4
5.8
5.4
5.8
−5
−13.6
Fall Time (20% to 80%)2, 3, 4
Random Jitter2, 3, 4
Deterministic Jitter2, 4, 5
Deterministic Jitter 2, 4, 6
Differential |S22|
Compliance Voltage1
DATA INPUTS (DATAP, DATAN)
Input Data Rate
Differential Input Swing
Differential |S11|
Input Termination Resistance
BIAS CONTROL INPUT (BSET)
BSET Voltage to IBIAS Gain
BSET Input Resistance
MODULATION CONTROL INPUT (MSET)
MSET Voltage to IMOD Gain
MSET Input Resistance
BIAS MONITOR (IBMON)
IBMON to IBIAS Ratio
Accuracy of IBIAS to IBMON Ratio
AUTOMATIC LASER SHUTDOWN (ALS)
VIH
VIL
IIL
IIH
Typ
Max
Unit
Test Conditions/Comments
25
50
VCC – 1.3
VCC – 0.8
mA
μA
V
V
ALS = high
IBIAS = 25 mA
IBIAS = 2 mA
23
19
250
65
32.5
34.7
32.5
33.7
mA diff
mA diff
μA diff
%
ps
ps
ps
ps
ps rms
ps rms
ps p-p
ps p-p
ps p-p
ps p-p
dB
dB
V
8.2
8.2
8.2
8.2
VCC − 0.7
VCC + 0.7
0.4
11.3
1.6
85
−15
100
115
Gbps
V p-p diff
dB
Ω
15
800
20
1000
24
1200
mA/V
Ω
14
800
19
1000
23
1200
mA/V
Ω
+5.0
+4.3
+3.5
+3.0
+2.5
μA/mA
%
%
%
%
%
0.8
+20
200
V
V
μA
μA
50
−5.0
−4.3
−3.5
−3.0
−2.5
2.4
−20
0
Rev. A | Page 3 of 20
RLOAD = 35 Ω to 100 Ω differential
RLOAD = 140 Ω differential
ALS = high
CPA disabled
CPA 35% to 65%
CPA disabled
CPA 35% to 65%
CPA disabled
CPA 35% to 65%
10.7 Gbps, CPA disabled
10.7 Gbps, CPA 35% to 65%
11.3 Gbps, CPA disabled
11.3 Gbps, CPA 35% to 65%
5 GHz < f < 10 GHz, Z0 = 100 Ω differential
f < 5 GHz, Z0 = 100 Ω differential
NRZ
Differential ac-coupled
f < 10 GHz, Z0 = 100 Ω differential
Differential
IBIAS = 2 mA, RIBMON = 750 Ω
IBIAS = 4 mA, RIBMON = 750 Ω
IBIAS = 8 mA, RIBMON = 750 Ω
IBIAS = 14 mA, RIBMON = 750 Ω
IBIAS = 25 mA, RIBMON = 750 Ω
ADN2530
Parameter
ALS Assert Time
Min
Typ
ALS Negate Time
POWER SUPPLY
VCC
ICC 7
ISUPPLY 8
3.07
3.3
27
65
Max
2
Unit
μs
10
μs
3.53
32
76
V
mA
mA
Test Conditions/Comments
Rising edge of ALS to fall of IBIAS and IMOD
below 10% of nominal; see Figure 2
Falling edge of ALS to rise of IBIAS and IMOD
above 90% of nominal; see Figure 2
VBSET = VMSET = 0 V
VBSET = VMSET = 0 V
1
The voltage between the pin with the specified compliance voltage and GND.
Specified for TA = −40°C to +85°C due to test equipment limitation. See the Typical Performance Characteristics section for data on performance for TA = −40°C to +100°C.
3
The pattern used is composed of a repetitive sequence of eight 1s followed by eight 0s at 10.7 Gbps.
4
Measured using the high speed characterization circuit shown in Figure 3.
5
The pattern used is K28.5 (00111110101100000101) at 10.7 Gbps rate.
6
The pattern used is K28.5 (00111110101100000101) at 11.3 Gbps rate.
7
Only includes current in the ADN2530 VCC pins.
8
Includes current in ADN2530 VCC pins and dc current in IMODP and IMODN pull-up inductors. See the Power Consumption section for total supply current calculation.
2
PACKAGE THERMAL SPECIFICATIONS
Table 2.
Parameter
θJ-TOP
θJ-PAD
IC Junction Temperature
Min
65
2.6
Typ
72.2
5.8
Max
79.4
10.7
125
Unit
°C/W
°C/W
°C
Conditions/Comments
Thermal resistance from junction to top of package.
Thermal resistance from junction to bottom of exposed pad.
ALS
NEGATE TIME
ALS
t
IBIAS
AND IMOD
90%
10%
05457-002
t
ALS
ASSERT TIME
Figure 2. ALS Timing Diagram
VEE
VEE
VEE
750Ω
VBSET
TP1
GND
10Ω
10nF
TP2
GND
VCC
GND
DC-BLOCK
J2
GND
GND
Z0 = 50Ω
GND
GND
50Ω
Z0 = 50Ω
IMODP
DATAP
GND
BIAS TEE
GND
ADAPTER
ATTENUATOR
ADAPTER
ATTENUATOR
GND
GND
Z0 = 50Ω
OSCILLOSCOPE
Z0 = 50Ω
DC-BLOCK
J3
GND
VCC
ADN2530
Z0 = 50Ω
Z0 = 50Ω
GND
IMODN
DATAN
50Ω
GND
GND
GND
MSET
BIAS TEE
VCC
VCC
CPA
ALS
GND
GND
VMSET
GND
10nF
VEE
VCPA
VEE
VEE
J8
GND
J5
GND
GND
GND
VEE
BIAS TEE: PICOSECOND PULSE LABS MODEL 5542-219
ADAPTER: PASTERNACK PE-9436 2.92mm FEMALE-TO-FEMALE ADAPTER
ATTENUATOR: PASTERNACK PE-7046 2.92mm 10dB ATTENUATOR
DC-BLOCK: AGILENT BLOCKING CAPACITOR 11742A
10μF
GND
Figure 3. High Speed Characterization Circuit
Rev. A | Page 4 of 20
05457-003
BSET IBMON IBIAS
ADN2530
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage—VCC to GND
IMODP, IMODN to GND
DATAP, DATAN to GND
All Other Pins
Junction Temperature
Storage Temperature Range
Soldering Temperature
(Less than 10 sec)
Rating
−0.3 V to +4.2 V
VCC − 1.5 V to +4.5 V
VCC − 1.8 V to VCC − 0.4 V
−0.3 V to VCC + 0.3 V
150°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 20
ADN2530
13 VCC
14 DATAP
ADN2530
12 BSET
11 IBMON
10 IBIAS
9 GND
VCC 8
TOP VIEW
(Not to Scale)
VCC 5
GND 4
PIN 1
INDICATOR
IMODN 6
IMODP 7
CPA 2
ALS 3
NOTES:
THERE IS AN EXPOSED PAD ON THE
BOTTOM OF THE PACKAGE THAT MUST BE
CONNECTED TO THE VCC OR GND PLANE.
05457-004
MSET 1
15 DATAN
16 VCC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Exposed Pad
Mnemonic
MSET
CPA
ALS
GND
VCC
IMODN
IMODP
VCC
GND
IBIAS
IBMON
BSET
VCC
DATAP
DATAN
VCC
Pad
I/O
Input
Input
Input
Power
Power
Output
Output
Power
Power
Output
Output
Input
Power
Input
Input
Power
Power
Description
Modulation Current Control Input
Crosspoint Adjust Control Input
Automatic Laser Shutdown
Negative Power Supply
Positive Power Supply
Modulation Current Negative Output
Modulation Current Positive Output
Positive Power Supply
Negative Power Supply
Bias Current Output
Bias Current Monitoring Output
Bias Current Control Input
Positive Power Supply
Data Signal Positive Input
Data Signal Negative Input
Positive Power Supply
Connect to GND or VCC
Rev. A | Page 6 of 20
ADN2530
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3 V, crosspoint adjust disabled, unless otherwise noted.
10
30
9
20
15
10
0
05457-035
5
0
5
10
15
20
8
7
10.7Gbps
6
5
11.3Gbps
4
3
2
05457-037
DETERMINISTIC JITTER (ps)
RISE TIME (ps)
25
1
0
25
0
5
10
15
20
25
DIFFERENTIAL MODULATION CURRENT (mA)
DIFFERENTIAL MODULATION CURRENT (mA)
Figure 5. Rise Time vs. IMOD
Figure 8. Deterministic Jitter vs. IMOD
30
1.0
0.9
0.8
RANDOM JITTER (ps rms)
20
15
10
0.6
0.5
0.4
0.3
JITTER BELOW EQUIPMENT
MEASUREMENT CAPABILITY
0.2
05457-036
5
0
0.7
5
0
10
15
20
05457-048
FALL TIME (ps)
25
0.1
0
25
0
5
DIFFERENTIAL MODULATION CURRENT (mA)
0
–5
–5
–10
–10
DIFFERENTIAL |S22| (dB)
0
–15
–20
–25
–30
0
1
2
3
4
5
6
7
8
9
20
25
–15
–20
–25
–30
–35
–40
10 11 12 13 14 15
FREQUENCY (GHz)
05457-050
–40
15
Figure 9. Random Jitter vs. IMOD
05457-049
DIFFERENTIAL |S11| (dB)
Figure 6. Fall Time vs. IMOD
–35
10
DIFFERENTIAL MODULATION CURRENT (mA)
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
FREQUENCY (GHz)
Figure 7. Differential |S11|
Figure 10. Differential |S22|
Rev. A | Page 7 of 20
ADN2530
35
10
9
20
15
10
0
–40
05457-044
5
–20
0
20
40
60
80
8
7
10.7Gbps
6
11.3Gbps
5
4
3
2
1
0
–40
100
–20
0
20
TEMPERATURE (°C)
Figure 11. Rise Time vs. Temperature (Worse-Case Conditions, CPA Disabled)
VCC = [3.07, 3.3, 3.53]
IMOD EYE CROSSPOINT (%)
20
15
10
60
50
40
30
05457-045
5
–20
0
20
40
60
80
05457-042
FALL TIME (ps)
100
70
25
20
1.00
100
1.25
1.50
TEMPERATURE (°C)
1.75
2.00
2.25
2.50
CPA VOLTAGE (V)
Figure 15. IMOD Eye Diagram Crosspoint vs. CPA Voltage and VCC
(IMOD = 10 mA)
Figure 12. Fall Time vs. Temperature (Worst-Case Conditions, CPA Disabled)
1.0
80
70
IMOD EYE CROSSPOINT (%)
0.8
RANDOM JITTER (ps rms)
80
80
30
0.6
0.4
0.2
60
50
40
+100°C
30
05457-046
0
–40
60
Figure 14. Deterministic Jitter vs. Temperature
(Worse-Case Conditions, CPA Disabled)
35
0
–40
40
TEMPERATURE (°C)
–20
0
20
40
60
80
20
0.75
100
TEMPERATURE (°C)
Figure 13. Random Jitter vs. Temperature
(Worst-Case Conditions, CPA Disabled [Worst-Case IMOD = 2.2 mA])
–40°C
+85°C
05457-043
RISE TIME (ps)
25
05457-047
DETERMINISTIC JITTER (ps)
30
+25°C
1.00
1.25
1.50
1.75
2.00
2.25
2.50
CPA VOLTAGE (V)
Figure 16. IMOD Eye Diagram Crosspoint vs. CPA Voltage and Temperature
(IMOD = 10 mA)
Rev. A | Page 8 of 20
ADN2530
140
IBIAS = 25mA
IBIAS = 10mA
1 LEVEL
1 LEVEL
100
80
IBIAS = 2mA
CROSSING
60
40
0
0 LEVEL
05457-038
20
0
5
10
15
20
0 LEVEL
05457-014
TOTAL SUPPLY CURRENT (mA)
120
25
DIFFERENTIAL MODULATION CURRENT (mA)
Figure 20. Electrical Eye Diagram
(IMOD = 10 mA, PRBS31 Pattern at 10.3125 Gbps)
Figure 17. Total Supply Current vs. IMOD
25
OCCURANCE (%)
20
15
10
26
27
28
29
30
05457-016
0
05457-039
5
31
RISE TIME (ps)
Figure 18. Worst-Case Rise Time Distribution
Figure 21. Filtered 10G Ethernet Optical Eye Using AOC HFE6192-562 VCSEL
(PRBS31 Pattern at 10.3125 Gbps, 3 dB Optical Attenuator)
25
15
10
5
0
05457-040
OCCURANCE (%)
20
26
27
28
29
30
31
FALL TIME (ps)
Figure 19. Worst-Case Fall Time Distribution
Rev. A | Page 9 of 20
ADN2530
THEORY OF OPERATION
50Ω
50Ω
ADN2530
C
DATAP
DATAN
C
05457-018
As shown in Figure 1, the ADN2530 consists of an input
stage and two voltage-controlled current sources for bias and
modulation. The bias current is available at the IBIAS pin. It is
controlled by the voltage at the BSET pin and can be monitored
at the IBMON pin. The differential modulation current is
available at the IMODP and IMODN pins. It is controlled by
the voltage at the MSET pin. The output stage implements the
active back-termination circuitry for proper transmission line
matching and power consumption reduction. The ADN2530
can drive a load with differential resistance ranging from 35 Ω
to 140 Ω. The excellent back-termination in the ADN2530
absorbs signal reflections from the TOSA end of the output
transmission lines, enabling excellent optical eye quality to be
achieved even when the TOSA end of the output transmission
lines is significantly misterminated.
DATA SIGNAL SOURCE
Figure 23. AC Coupling the Data Source to the ADN2530 Data Inputs
BIAS CURRENT
The bias current is generated internally using a voltage-to-current
converter consisting of an internal operational amplifier and a
transistor, as shown in Figure 24.
VCC
INPUT STAGE
ADN2530
The input stage of the ADN2530 converts the data signal applied
to the DATAP and DATAN pins to a level that ensures proper
operation of the high speed switch. The equivalent circuit of the
input stage is shown in Figure 22.
IBMON
BSET
IBMON
800Ω
IBIAS
IBIAS
200Ω
200Ω
DATAP
50Ω
VCC
GND
10Ω
05457-019
VCC
Figure 24. Voltage-to-Current Converter Used to Generate IBIAS
VCC
05457-017
50Ω
DATAN
Figure 22. Equivalent Circuit of the Input Stage
The DATAP and DATAN pins are terminated internally with a
100 Ω differential termination resistor. This minimizes signal
reflections at the input that could otherwise lead to degradation
in the output eye diagram. It is not recommended to drive the
ADN2530 with single-ended data signal sources.
The ADN2530 input stage must be ac-coupled to the signal
source to eliminate the need for matching between the commonmode voltages of the data signal source and the input stage of
the driver (see Figure 23). The ac-coupling capacitors should
have an impedance less than 50 Ω over the required frequency
range. Generally, this is achieved using 10 nF to 100 nF
capacitors.
The BSET to IBIAS voltage-to-current conversion factor is
set at 20 mA/V by the internal resistors, and the bias current is
monitored at the IBMON pin using a current mirror with a gain
equal to 1/20. By connecting a 750 Ω resistor between IBMON
and GND, the bias current can be monitored as a voltage across
the resistor. A low temperature coefficient precision resistor
must be used for the IBMON resistor (RIBMON). Any error in
the value of RIBMON due to tolerances or drift in its value over
temperature contributes to the overall error budget for the IBIAS
monitor voltage. If the IBMON voltage is being connected to an
ADC for A/D conversion, RIBMON should be placed close to the
ADC to minimize errors due to voltage drops on the ground
plane. See the Design Example section for example calculations
of the accuracy of the IBIAS monitor as a percentage of the
nominal IBIAS value.
Rev. A | Page 10 of 20
ADN2530
The equivalent circuits of the BSET, IBIAS, and IBMON pins
are shown in Figure 25 to Figure 27.
VCC
VCC
BSET
See the Headroom Calculations section for examples.
The function of Inductor L is to isolate the capacitance of the
IBIAS output from the high frequency signal path. For
recommended components, see Table 6.
AUTOMATIC LASER SHUTDOWN (ALS)
800Ω
The ALS pin is a digital input that enables/disables both the bias
and modulation currents, depending on the logic state applied,
as shown in Table 5.
05457-020
200Ω
Figure 25. Equivalent Circuit of the BSET Pin
Table 5.
ALS Logic State
High
Low
Floating
VCC
VCC
2kΩ
100Ω
The ALS pin is compatible with 3.3 V CMOS and TTL logic
levels. Its equivalent circuit is shown in Figure 29.
05457-021
10Ω
Figure 26. Equivalent Circuit of the IBIAS Pin
VCC
IBIAS and IMOD
Disabled
Enabled
Enabled
VCC
VCC
VCC
100Ω
ALS
35kΩ
500Ω
05457-024
IBIAS
2kΩ
Figure 29. Equivalent Circuit of the ALS Pin
MODULATION CURRENT
100Ω
05457-022
VCC
IBMON
Figure 27. Equivalent Circuit of the IBMON Pin
The recommended configuration for BSET, IBIAS, and IBMON
is shown in Figure 28.
The modulation current can be controlled by applying a dc
voltage to the MSET pin. This voltage is converted into a dc
current by using a voltage-to-current converter that uses an
operational amplifier and a bipolar transistor, as shown in
Figure 30.
VCC
TO LASER CATHODE
IMODP
L
IBIAS
100Ω
IMOD
IMODN
IBIAS
ADN2530
BSET
GND
MSET
RIBMON
750Ω
800Ω
05457-023
VBSET
FROM CPA STAGE
IBMON
200Ω
The circuit used to drive the BSET voltage must be able to drive
the 1 kΩ input resistance of the BSET pin. For proper operation
of the bias current source, the voltage at the IBIAS pin must be
between the compliance voltage specifications for this pin over
supply, temperature, and bias current range (see Table 1). The
maximum compliance voltage is specified for only two bias
current levels (2 mA and 25 mA), but it can be calculated for
any bias current by
VCOMPLIANCE (V) = VCC (V) − 0.75 − 22 × IBIAS (A)
ADN2530
GND
05457-025
Figure 28. Recommended Configuration for BSET, IBIAS, and IBMON Pins
Figure 30. Generation of Modulation Current on the ADN2530
This dc current is switched by the data signal applied to the
input stage (DATAP and DATAN pins) and gained up by the
output stage to generate the differential modulation current at
the IMODP and IMODN pins. The output stage also generates
the active back-termination, which provides proper transmission
line termination. Active back-termination uses feedback around
an active circuit to synthesize a broadband termination resistance.
Rev. A | Page 11 of 20
ADN2530
VCC
MSET
40
35
MAX
30
TYP
25
MIN
20
15
10
10
800Ω
05457-029
VCC
45
MSET VOLTAGE TO MODULATION
CURRENT RATIO (mA/V)
This provides excellent transmission line termination while
dissipating less power than a traditional resistor passive backtermination. No portion of the modulation current flows in the
active back-termination resistance. All of the preset modulation
current IMOD, the range specified in Table 1, flows in the
external load. The equivalent circuits for MSET, IMODP, and
IMODN are shown in Figure 31 and Figure 32. The two 50 Ω
resistors in Figure 32 are not real resistors. They represent the
active back-termination resistance.
20
30
40
50
60
70
80
90 100 110 120 130 140
05457-026
DIFFERENTIAL LOAD RESISTANCE
200Ω
Figure 34. MSET Voltage to Modulation Current Ratio vs.
Differential Load Resistance
Figure 31. Equivalent Circuit of the MSET Pin
VCC
IMODN
Using the resistance of the TOSA, the user can calculate the
voltage range that should be applied to the MSET pin to
generate the required modulation current range (see the
example in the Applications Information section).
VCC
IMODP
50Ω
50Ω
15Ω
05457-027
15Ω
Figure 32. Equivalent Circuit of the IMODP and IMODN Pins
The recommended configuration of the MSET, IMODP, and
IMODN pins is shown in Figure 33. See Table 6 for recommended components. When the voltage on DATAP is greater
than the voltage on DATAN, the modulation current flows into
the IMODP pin and out of the IMODN pin, generating an
optical Logic 1 level at the TOSA output when the TOSA is
connected as shown in Figure 33.
IBIAS
VCC
L
L
ADN2530
Z0 = 50Ω
C
Z0 = 50Ω
Z0 = 50Ω
C
Z0 = 50Ω
The circuit used to drive the MSET voltage must be able to
drive the 1 kΩ resistance of the MSET pin. To be able to drive
23 mA modulation currents through the differential load, the
output stage of the ADN2530 (IMODP and IMODN pins)
must be ac-coupled to the load. The voltages at these pins
have a dc component equal to VCC and an ac component with
single-ended peak-to-peak amplitude of IMOD × 50 Ω. This
is the case when the load impedance (RTOSA) is less than
100 Ω differential because the transmission line characteristic
impedance sets the peak-to-peak amplitude. For the case where
RTOSA is greater than 100 Ω, the single-ended, peak-to-peak
amplitude is IMOD × RTOSA ÷ 2. For proper operation of the
output stage, the voltages at the IMODP and IMODN pins must
be between the compliance voltage specifications for this pin
over supply, temperature, and modulation current range, as
shown in Figure 35. See the Headroom Calculations section for
examples of headroom calculations.
VIMODP, VIMODN
IMODP
TOSA
IMODN
VCC + 0.7V
VMSET
GND
L
L
VCC
VCC
05457-028
MSET
NORMAL OPERATION REGION
VCC
Figure 33. Recommended Configuration for the
MSET, IMODP, and IMODN Pins
Rev. A | Page 12 of 20
05457-030
VCC – 0.7V
The ratio between the voltage applied to the MSET pin and the
differential modulation current available at the IMODP and
IMODN pins is a function of the load resistance value, as shown
in Figure 34.
Figure 35. Allowable Range for the Voltage at IMODP and IMODN
ADN2530
LOAD MISTERMINATION
POWER CONSUMPTION
Due to its excellent S22 performance, the ADN2530 can drive
differential loads that range from 35 Ω to 140 Ω. In practice,
many TOSAs have differential resistance not equal to 100 Ω. In
this case, with 100 Ω differential transmission lines connecting
the ADN2530 to the load, the load end of the transmission lines
are misterminated. This mistermination leads to signal reflections
back to the driver. The excellent back-termination in the
ADN2530 absorbs these reflections, preventing their reflection
back to the load. This enables excellent optical eye quality to
be achieved even when the load end of the transmission lines is
significantly misterminated. The connection between the load
and the ADN2530 must be made with 100 Ω differential (50 Ω
single-ended) transmission lines so that the driver end of the
transmission lines is properly terminated.
The power dissipated by the ADN2530 is given by
CROSSPOINT ADJUST
The crossing level in the output electrical eye diagram can be
adjusted between 35% and 65% using the crosspoint adjust (CPA)
control input. This can be used to compensate for asymmetry in
the VCSEL response and optimizes the optical eye mask margin.
The CPA input is a voltage control input, and a plot of eye crosspoint vs. CPA control voltage is shown in Figure 15 and Figure 16
in the Typical Performance Characteristics section. The equivalent
circuit for the CPA pin is shown in Figure 36. To disable the
crosspoint adjust function and set the eye crossing to 50%, the
CPA pin should be tied to VCC.
⎞
⎛V
P = VCC × ⎜ MSET + I SUPPLY ⎟ + V IBIAS × ( IBIAS × 1.2)
⎠
⎝ 50
where:
VCC is the power supply voltage.
IBIAS is the bias current generated by the ADN2530.
VMSET is the voltage applied to the MSET pin.
ISUPPLY is the sum of the current that flows into the VCC,
IMODP, and IMODN pins of the ADN2530 when IBIAS =
IMOD = 0 expressed in amps (see Table 1).
VIBIAS is the average voltage on the IBIAS pin.
Considering VBSET/IBIAS = 50 as the conversion factor from
VBSET to IBIAS, the dissipated power becomes
⎛V
⎞
⎛V
⎞
P = VCC × ⎜ MSET + I SUPPLY ⎟ + V IBIAS × ⎜ BSET × 1.2 ⎟
⎝ 50
⎠
⎝ 50
⎠
To ensure long-term reliable operation, the junction temperature of the ADN2530 must not exceed 125°C, as specified in
Table 2. For improved heat dissipation, the module’s case can be
used as a heat sink, as shown in Figure 37.
THERMAL COMPOUND
MODULE CASE
TTOP
DIE
100Ω
TJ
THERMO-COUPLE
PACKAGE
T PAD
PCB
COPPER PLANE
Figure 36. Equivalent Circuit for CPA Pin
VIAS
Figure 37. Typical Optical Module Structure
Rev. A | Page 13 of 20
05457-032
CPA
05457-031
VCC
ADN2530
TTOP
A compact optical module is a complex thermal environment,
and calculations of device junction temperature using the
package θJA (junction-to-ambient thermal resistance) do not
yield accurate results. The following equation, derived from the
model in Figure 38, can be used to estimate the IC junction
temperature:
TTOP
TJ
P
θJ-PAD
TPAD
)
TPAD
P × θ J − PAD × θ J −TOP + TTOP × θ J − PAD + TPAD × θ J −TOP
θ J − PAD + θ J −TOP
05757-033
TJ =
(
θJ-TOP
Figure 38. Electrical Model for Thermal Calculations
where:
TTOP and TPAD can be determined by measuring the temperature
at points inside the module, as shown in Figure 37. The thermocouples should be positioned to obtain an accurate measurement of
the package top and paddle temperatures. θJ-TOP and θJ-PAD are
given in Table 2.
TTOP is the temperature at top of package in degrees Celsius.
TPAD is the temperature at package exposed paddle in degrees
Celsius.
TJ is the IC junction temperature in degrees Celsius.
P is the ADN2530 power dissipation in watts.
θJ-TOP is the thermal resistance from IC junction to package top.
θJ-PAD is the thermal resistance from IC junction to package
exposed pad.
Rev. A | Page 14 of 20
ADN2530
APPLICATIONS INFORMATION
TYPICAL APPLICATION CIRCUIT
LAYOUT GUIDELINES
Figure 39 shows the typical application circuit for the
ADN2530. The dc voltages applied to the BSET and MSET pins
control the bias and modulation currents. The bias current can
be monitored as a voltage drop across the 750 Ω resistor connected
between the IBMON pin and GND. The dc voltage applied to
the CPA pin controls the crosspoint in the output eye diagram.
By tying the CPA pin to VCC, the CPA function is disabled. The
ALS pin allows the user to turn on/off the bias and modulation
currents depending on the logic level applied to the pin. The
data signal source must be connected to the DATAP and DATAN
pins of the ADN2530 using 50 Ω transmission lines. The
modulation current outputs, IMODP and IMODN, must be
connected to the load (TOSA) using 100 Ω differential (50 Ω
single-ended) transmission lines. Table 6 shows recommended
components for the ac-coupling interface between the ADN2530
and TOSA. For additional application information and optical
eye diagram performance data, see the application notes and
reference design for the ADN2530 at www.analog.com.
Due to the high frequencies at which the ADN2530 operates,
care should be taken when designing the PCB layout to obtain
optimum performance. Controlled impedance transmission
lines must be used for the high speed signal paths. The length
of the transmission lines must be kept to a minimum to reduce
losses and pattern-dependent jitter. The PCB layout must be
symmetrical both on the DATAP and DATAN inputs and on
the IMODP and IMODN outputs to ensure a balance between
the differential signals. All VCC and GND pins must be connected
to solid copper planes by using low inductance connections.
When the connections are made through vias, multiple vias can
be connected in parallel to reduce the parasitic inductance.
Each GND pin must be locally decoupled to VCC with high
quality capacitors, see Figure 39. If proper decoupling cannot be
achieved using a single capacitor, the user can use multiple
capacitors in parallel for each GND pin. A 20 μF tantalum
capacitor must be used as the general decoupling capacitor for
the entire module. For recommended PCB layouts, including
those suitable for XFP modules, contact sales. For guidelines on
the surface-mount assembly of the ADN2530, consult the
Amkor Technology® “Application Notes for Surface Mount
Assembly of Amkor’s MicroLeadFrame® (MLF®) Packages.”
Table 6.
Value
110 Ω
300 Ω
100 nF
L6, L7
160 nH
L2, L3
L1, L4, L5, L8
10 μH
Description
0603 size resistor
0603 size resistor
0402 size capacitor,
Phycomp 223878719849
0603 size inductor,
Murata LQW18ANR16
0603 size chip ferrite bead,
Murata BLM18HG601
0805 size inductor,
Murata LQM21FN100M70L
BSET
C8
100nF
VCC
GND
R5
750Ω
TP1
VCC
GND
C5
10nF
L1
R1
L8
R4
VCC
VCC
BSET IBMON IBIAS GND
VCC
VCC
Z0 = 50Ω
VCC
L2
L7
Z0 = 50Ω
DATAP
DATAP
DATAN
DATAN
Z0 = 50Ω
VCC
MSET
Z0 = 50Ω
TOSA
IMODN
C2
VCC
C4
GND
ADN2530
Z0 = 50Ω
Z0 = 50Ω
IMODP
C1
CPA
ALS
VCC
GND
GND
L3
VCC
C3
L6
VCC
C6
10nF
MSET
+3.3V
VCC
C7
20μF
CPA
ALS
L4
R2
L5
R3
GND
VCC
GND
Figure 39. Typical ADN2530 Application Circuit
Rev. A | Page 15 of 20
VCC
05757-034
Component
R1, R2
R3, R4
C3, C4
ADN2530
DESIGN EXAMPLE
This design example covers:
•
Headroom calculations for IBIAS, IMODP, and IMODN pins.
•
Calculation of the typical voltage required at the BSET
and MSET pins to produce the desired bias and
modulation currents.
•
Calculations of the IBIAS monitor accuracy over the IBIAS
current range.
Assuming the dc voltage drop across L1, L2, L3, and L4 = 0 V
and IMOD = 10 mA, the minimum voltage at the modulation
output pins is equal to
VCC − (IMOD × 50)/2 = VCC − 0.25
VCC − 0.25 > VCC − 0.7 V, which satisfies the requirement
The maximum voltage at the modulation output pins is equal to
This design example assumes that the impedance of the
TOSA is 60 Ω, the forward voltage of the VCSEL at low current
is VF = 1.2 V, IBIAS = 10 mA, IMOD = 10 mA, and VCC = 3.3 V.
Headroom Calculations
To ensure proper device operation, the voltages on the IBIAS,
IMODP, and IMODN pins must meet the compliance voltage
specifications in Table 1.
Considering the typical application circuit shown in Figure 39,
the voltage at the IBIAS pin can be written as
VIBIAS = VCC − VF − (IBIAS × RTOSA) − VLA
where:
VCC + (IMOD × 50)/2 = VCC + 0.25
VCC + 0.25 < VCC + 0.7 V, which satisfies the requirement
Headroom calculations must be repeated for the minimum and
maximum values of the required IBIAS and IMOD ranges to
ensure proper device operation over all operating conditions.
BSET and MSET Pin Voltage Calculation
To set the desired bias and modulation currents, the BSET and
MSET pins of the ADN2530 must be driven with the appropriate
dc voltage. The voltage range required at the BSET pin to generate
the required IBIAS range can be calculated using the BSET voltage
to IBIAS gain specified in Table 1. Assuming that IBIAS = 10 mA
and the typical IBIAS/VBSET ratio of 20 mA/V, the BSET voltage
is given by
VBSET =
VCC is the supply voltage.
IBIAS (mA)
20 mA/V
=
10
= 0.5 V
20
VF is the forward voltage across the laser at low current.
The BSET voltage range can be calculated using the required
IBIAS range and the minimum and maximum BSET voltage to
IBIAS gain values specified in Table 1.
RTOSA is the resistance of the TOSA.
VLA is the dc voltage drop across L5, L6, L7, and L8.
For proper operation, the minimum voltage at the IBIAS pin
should be greater than 0.55 V, as specified by the minimum
IBIAS compliance specification in Table 1.
The voltage required at the MSET pin to produce the desired
modulation current can be calculated using
V MSET =
Assuming that the voltage drop across the 50 Ω transmission lines
is negligible and that VLA = 0 V, VF = 1.2 V, and IBIAS = 10 mA,
IMOD
K
VIBIAS = 3.3 − 1.2 − (0.01 × 60) = 1.5 V
where K is the MSET voltage to IMOD ratio.
VIBIAS = 1.5 V > 0.55 V, which satisfies the requirement
The value of K depends on the actual resistance of the TOSA
and can be obtained from Figure 34. For a TOSA resistance of
60 Ω, the typical value of K = 24 mA/V. Assuming that IMOD =
10 mA and using the preceding equation, the MSET voltage is
given by
The maximum voltage at the IBIAS pin must be less than the
maximum IBIAS compliance specification as described by
VCOMPLIANCE_MAX = VCC − 0.75 − 22 × IBIAS (A)
VMSET =
For this example,
VCOMPLIANCE_MAX = VCC – 0.75 − 22 × 0.01 = 2.33 V
VIBIAS = 1.5 V < 2.33 V, which satisfies the requirement
To calculate the headroom at the modulation current pins
(IMODP and IMODN), the voltage has a dc component equal
to VCC due to the ac-coupled configuration and a swing equal
to IMOD × 50 Ω, as RTOSA < 100 Ω. For proper operation of the
ADN2530, the voltage at each modulation output pin should be
within the normal operation region shown in Figure 35.
IMOD (mA)
24 mA/V
=
10
= 0.42 V
24
The MSET voltage range can be calculated using the required
IMOD range and the minimum and maximum K values. These can
be obtained from the minimum and maximum curves in Figure 34.
Rev. A | Page 16 of 20
ADN2530
IBIAS Monitor Accuracy Calculations
Referring to Figure 40, the IBMON output current accuracy is
±4.3% for the minimum IBIAS of 4 mA and ±3.0% for the
maximum IBIAS value of 14 mA.
5
The accuracy of the IBMON output current as a percentage of
the nominal IBIAS is given by
4
IBMON _ Accuracy MIN = 4 mA
3
IBMON _ Accuracy MAX = 14 mA
1
0
4.3 100
×
= ± 2.15%
100 8 mA
for the minimum IBIAS value, and by
2
05457-041
ACCURACY OF IBIAS TO IBMON RATIO (%)
6
0
5
10
15
20
25
IBIAS (mA)
Figure 40. Accuracy of IBIAS to IBMON Ratio
This example assumes that the nominal value of IBIAS is 8 mA
and that the IBIAS range for all operating conditions is 4 mA to
14 mA. The accuracy of the IBIAS to IBMON ratio is given in
the Table 1 and is plotted in Figure 40.
3.0 100
×
= ± 5.25%
100 8 mA
for the maximum IBIAS value. This gives a worse-case accuracy
for the IBMON output current of ±5.25% of the nominal IBIAS
value over all operating conditions. The IBMON output current
accuracy numbers can be combined with the accuracy numbers
for the 750 Ω IBMON resistor (RIBMON) and any other error
sources to calculate an overall accuracy for the IBMON voltage.
Rev. A | Page 17 of 20
ADN2530
OUTLINE DIMENSIONS
3.00
BSC SQ
0.60 MAX
0.45
PIN 1
INDICATOR
TOP
VIEW
13
12
2.75
BSC SQ
0.80 MAX
0.65 TYP
12° MAX
SEATING
PLANE
16
1
EXPOSED
PAD
0.50
BSC
0.90
0.85
0.80
0.50
0.40
0.30
PIN 1
INDICATOR
*1.65
1.50 SQ
1.35
9 (BOTTOM VIEW) 4
8
5
0.25 MIN
1.50 REF
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADN2530YCPZ-WP 1
ADN2530YCPZ-R21
ADN2530YCPZ-REEL71
1
Temperature Range
−40°C to +100°C
−40°C to +100°C
−40°C to +100°C
Package Description
16-Lead LFCSP_VQ, 50-Piece Waffle Pack
16-Lead LFCSP_VQ, 250-Piece Reel
16-Lead LFCSP_VQ, 1500-Piece Reel
Z = Pb-free part.
Rev. A | Page 18 of 20
Package Option
CP-16-3
CP-16-3
CP-16-3
Branding
F08
F08
F08
ADN2530
NOTES
Rev. A | Page 19 of 20
ADN2530
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05457–0–8/06(A)
Rev. A | Page 20 of 20