Order this document by MMBF170LT1/D SEMICONDUCTOR TECHNICAL DATA DRAIN 3 N–Channel 1 GATE 3 2 SOURCE 1 MAXIMUM RATINGS 2 Rating Symbol Value Unit Drain–Source Voltage VDSS 60 Vdc Drain–Gate Voltage VDGS 60 Vdc Gate–Source Voltage — Continuous — Non–repetitive (tp ≤ 50 ms) VGS VGSM ± 20 ± 40 Vdc Vpk ID IDM 0.5 0.8 Adc Symbol Max Unit PD 225 mW 1.8 mW/°C RqJA 556 °C/W TJ, Tstg – 55 to +150 °C Drain Current – Continuous Pulsed CASE 318 – 08, STYLE 21 SOT– 23 (TO – 236AB) THERMAL CHARACTERISTICS Characteristic Total Device Dissipation FR– 5 Board(1) TA = 25°C Derate above 25°C Thermal Resistance, Junction to Ambient Junction and Storage Temperature DEVICE MARKING MMBF170LT1 = 6Z ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Characteristic Symbol Min Max Unit V(BR)DSS 60 — Vdc IGSS — 10 nAdc Gate Threshold Voltage (VDS = VGS, ID = 1.0 mA) VGS(th) 0.8 3.0 Vdc Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 200 mA) rDS(on) — 5.0 ID(off) — 0.5 W mA Ciss — 60 pF td(on) — 10 ns td(off) — 10 OFF CHARACTERISTICS Drain–Source Breakdown Voltage (VGS = 0, ID = 100 mA) Gate–Body Leakage Current, Forward (VGSF = 15 Vdc, VDS = 0) ON CHARACTERISTICS (2) On–State Drain Current (VDS = 25 Vdc, VGS = 0) DYNAMIC CHARACTERISTICS Input Capacitance (VDS = 10 Vdc, VGS = 0 V, f = 1.0 MHz) SWITCHING CHARACTERISTICS (2) ((VDD = 25 Vdc,, ID = 500 mA,, Rgen = 50 W) Figure 1 Turn–On Delay Time Turn–Off Delay Time 1. FR– 5 = 1.0 0.75 0.062 in. 2. Pulse Test: Pulse Width 300 ms, Duty Cycle v v 2.0%. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company REV 2 Motorola Small–Signal Transistors, FETs and Diodes Device Data Motorola, Inc. 1996 1 MMBF170LT1 +25 V PULSE GENERATOR ton td(on) 125 W Vin 50 W 20 dB 50 W ATTENUATOR 40 pF TO SAMPLING SCOPE 50 W INPUT Vout OUTPUT INVERTED Vout tr 90% td(off) 90% 10% INPUT 90% 50% 50% 50 W 1 MW Vin toff tf 10% PULSE WIDTH (Vin AMPLITUDE 10 VOLTS) Figure 1. Switching Test Circuit Figure 2. Switching Waveform 2.0 1.0 VDS = 10 V TA = 25°C 1.6 VGS = 10 V 1.4 9V 1.2 I D, DRAIN CURRENT (AMPS) I D, DRAIN CURRENT (AMPS) 1.8 8V 1.0 7V 0.8 6V 0.6 0.4 5V 0.2 4V 3V 0 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VDS, DRAIN SOURCE VOLTAGE (VOLTS) 9.0 0.8 125°C 0.6 0.4 0.2 10 0 2.4 2.2 1.8 VGS = 10 V ID = 200 mA 1.6 1.4 1.2 1.0 0.8 0.6 0.4 – 60 – 20 + 20 + 60 T, TEMPERATURE (°C) + 100 Figure 5. Temperature versus Static Drain–Source On–Resistance 2 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 VGS, GATE SOURCE VOLTAGE (VOLTS) 9.0 10 Figure 4. Transfer Characteristics VGS(th) , THRESHOLD VOLTAGE (NORMALIZED) r DS(on) , STATIC DRAIN–SOURCE ON–RESISTANCE (NORMALIZED) Figure 3. Ohmic Region 2.0 25°C – 55°C + 140 1.2 1.05 VDS = VGS ID = 1.0 mA 1.1 1.10 1.0 0.95 0.9 0.85 0.8 0.75 0.7 – 60 – 20 + 20 + 60 T, TEMPERATURE (°C) + 100 Figure 6. Temperature versus Gate Threshold Voltage Motorola Small–Signal Transistors, FETs and Diodes Device Data + 140 MMBF170LT1 INFORMATION FOR USING THE SOT–23 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. 0.037 0.95 0.037 0.95 0.079 2.0 0.035 0.9 0.031 0.8 inches mm SOT–23 SOT–23 POWER DISSIPATION The power dissipation of the SOT–23 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA . Using the values provided on the data sheet for the SOT–23 package, PD can be calculated as follows: PD = TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 225 milliwatts. PD = 150°C – 25°C 556°C/W = 225 milliwatts The 556°C/W for the SOT–23 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 225 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–23 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. Motorola Small–Signal Transistors, FETs and Diodes Device Data 3 MMBF170LT1 PACKAGE DIMENSIONS A L 3 B S 1 V STYLE 21: PIN 1. GATE 2. SOURCE 3. DRAIN 2 DIM A B C D G H J K L S V G C D H J K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. INCHES MIN MAX 0.1102 0.1197 0.0472 0.0551 0.0350 0.0440 0.0150 0.0200 0.0701 0.0807 0.0005 0.0040 0.0034 0.0070 0.0180 0.0236 0.0350 0.0401 0.0830 0.0984 0.0177 0.0236 MILLIMETERS MIN MAX 2.80 3.04 1.20 1.40 0.89 1.11 0.37 0.50 1.78 2.04 0.013 0.100 0.085 0.177 0.45 0.60 0.89 1.02 2.10 2.50 0.45 0.60 CASE 318–08 ISSUE AE SOT–23 (TO–236AB) Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 4 ◊ *MMBF170LT1/D* MMBF170LT1/D Motorola Small–Signal Transistors, FETs and Diodes Device Data