AD ADG836YCP

0.5  CMOS 1.65 V TO 3.6 V
Dual SPDT/2:1 MUX
ADG836
FEATURES
0.5  Typical On Resistance
0.8  Maximum On Resistance at 125°C
1.65 V to 3.6 V Operation
Automotive Temperature Range: –40°C to +125°C
High Current Carrying Capability: 300 mA Continuous
Rail-to-Rail Switching Operation
Fast Switching Times <20 ns
Typical Power Consumption (<0.1 W)
APPLICATIONS
Cellular Phones
PDAs
MP3 Players
Power Routing
Battery-Powered Systems
PCMCIA Cards
Modems
Audio and Video Signal Routing
Communication Systems
FUNCTIONAL BLOCK DIAGRAM
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GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG836 is a low voltage CMOS device containing two
independently selectable single-pole, double-throw (SPDT)
switches. This device offers ultralow on resistance of less than
0.8  over the full temperature range. The ADG836 is fully
specified for 3.3 V, 2.5 V, and 1.8 V supply operation.
1. <0.8  over full temperature range of –40°C to +125°C.
Each switch conducts equally well in both directions when on
and has an input signal range that extends to the supplies. The
ADG836 exhibits break-before-make switching action.
The ADG836 is available in 10-lead MSOP and 3 mm  3 mm
12-lead LFCSP packages.
2. Single 1.65 V to 3.6 V operation.
3. Compatible with 1.8 V CMOS logic.
4. High current handling capability (300 mA continuous current
at 3.3 V).
5. Low THD + N (0.02% typ).
6. 3 mm  3 mm LFCSP package and 10-lead MSOP package.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks
and registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc. All rights reserved.
ADG836–SPECIFICATIONS1(V
DD
Parameter
+25C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match between
Channels (RON)
On Resistance Flatness (RFLAT (ON))
LEAKAGE CURRENTS
Source Off Leakage IS (OFF)
0.5
0.65
0.04
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
–40C
to +85C
–40C
to +125C
Unit
Test Conditions/Comments
0 V to VDD
V
VDD = 2.7 V
VDD = 2.7 V, VS = 0 V to VDD, IS = 10 mA;
Test Circuit 1
VDD = 2.7 V, VS = 0.65 V, IS = 10 mA
0.75
0.8
0.075
0.08
0.15
0.16
0.1
±0.2
±1
±0.2
±1
Channel On Leakage ID, IS (ON)
= 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted.)
VDD = 2.7 V, VS = 0 V to VDD,
IS = 10 mA
VDD = 3.6 V
VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V;
Test Circuit 2
VS = VD = 0.6 V or 3.3 V; Test Circuit 3
±10
±100
±15
±120
nA typ
nA max
nA typ
nA max
2
0.8
V min
V max
±0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 50 , CL = 35 pF
VS = 1.5 V/0 V; Test Circuit 4
RL = 50 , CL = 35 pF
VS = 1.5 V; Test Circuit 4
RL = 50 , CL = 35 pF
VS1 = VS2 = 1.5 V; Test Circuit 5
VS = 1.5 V, RS = 0 , CL = 1 nF;
Test Circuit 6
RL = 50 , CL = 5 pF, f = 100 kHz;
Test Circuit 7
S1A–S2A/S1B–S2B;
RL = 50 , CL = 5 pF, f = 100 kHz;
Test Circuit 10
S1A–S1B/S2A–S2B;
RL = 50 , CL = 5 pF, f = 100 kHz;
Test Circuit 9
RL = 32 , f = 20 Hz to 20 kHz,
VS = 2 V p-p
RL = 50 , CL = 5 pF; Test Circuit 8
RL = 50 , CL = 5 pF; Test Circuit 8
0.005
CIN, Digital Input Capacitance
 typ
 max
 typ
 max
 typ
 max
4
2
DYNAMIC CHARACTERISTICS
tON
Break-before-Make Time Delay (tBBM)
21
26
4
7
17
Charge Injection
40
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–67
dB typ
Channel-to-Channel Crosstalk
–90
dB typ
–67
dB typ
Total Harmonic Distortion (THD + N)
0.02
%
Insertion Loss
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
–0.05
57
25
75
dB typ
MHz typ
pF typ
pF typ
0.003
µA typ
µA max
tOFF
POWER REQUIREMENTS
IDD
28
29
8
9
5
1
4
VDD = 3.6 V
Digital Inputs = 0 V or 3.6 V
NOTES
1
Temperature range is as follows: Y version: –40°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG836
SPECIFICATIONS1 (V
DD
Parameter
= 2.5 V ± 0.2 V, GND = 0 V, unless otherwise noted.)
+25C
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match between
Channels (RON)
On Resistance Flatness (RFLAT (ON))
LEAKAGE CURRENTS
Source Off Leakage IS (OFF)
0.65
0.72
0.04
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
–40C
to +125C
Unit
0 V to VDD
V
0.8
0.88
0.08
0.085
0.23
0.24
0.16
±0.2
±0.4
±0.2
±0.6
Channel On Leakage ID, IS (ON)
–40C
to +85C
VDD = 2.3 V, VS = 0 V to VDD,
IS = 10 mA; Test Circuit 1
VDD = 2.3 V, VS = 0.7 V;
IS = 10 mA
VDD = 2.3 V, VS = 0 V to VDD,
IS = 10 mA
VDD = 2.7 V
VS = 0.6 V/2.4 V, VD = 2.4 V/0.6 V;
Test Circuit 2
VS = VD = 0.6 V or 2.4 V; Test Circuit 3
±4
±45
±12
±90
nA typ
nA max
nA typ
nA max
1.7
0.7
V min
V max
±0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 50 , CL = 35 pF
VS = 1.5 V/0 V; Test Circuit 4
RL = 50 , CL = 35 pF
VS = 1.5 V; Test Circuit 4
RL = 50 , CL = 35 pF
VS1 = VS2 = 1.5 V; Test Circuit 5
VS = 1.25 V, RS = 0 , CL = 1 nF;
Test Circuit 6
RL = 50 , CL = 5 pF, f = 100 kHz;
Test Circuit 7
S1A–S2A/S1B–S2B;
RL = 50 , CL = 5 pF, f = 100 kHz;
Test Circuit 10
S1A–S1B/S2A–S2B;
RL = 50 , CL = 5 pF, f = 100 kHz;
Test Circuit 9
RL = 32 , f = 20 Hz to 20 kHz,
VS = 1.5 V p-p
RL = 50 , CL = 5 pF; Test Circuit 8
RL = 50 , CL = 5 pF; Test Circuit 8
0.005
CIN, Digital Input Capacitance
 typ
 max
 typ
 max
 typ
 max
Test Conditions/Comments
4
2
DYNAMIC CHARACTERISTICS
tON
Break-before-Make Time Delay (tBBM)
23
29
5
7
17
Charge Injection
30
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–67
dB typ
Channel-to-Channel Crosstalk
–90
dB typ
–67
dB typ
Total Harmonic Distortion (THD + N)
0.022
%
Insertion Loss
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
–0.06
57
25
75
dB typ
MHz typ
pF typ
pF typ
0.003
µA typ
µA max
tOFF
POWER REQUIREMENTS
IDD
30
31
8
9
5
1.0
4.0
NOTES
1
Temperature range is as follows: Y version: –40°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. 0
–3–
VDD = 2.7 V
Digital Inputs = 0 V or 2.7 V
ADG836
SPECIFICATIONS1(V
DD
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match between
Channels (RON)
LEAKAGE CURRENTS
Source Off Leakage IS (OFF)
Channel On Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tON
= 1.65 V to 1.95 V, GND = 0 V, unless otherwise noted.)
+25C
1
1.4
2
0.1
±0.2
±0.4
±0.2
±0.6
–40C
to +85C
2.2
4
–40C
to +125C
Unit
0 V to VDD
V
2.2
4
 typ
 max
 max
 typ
VDD = 1.95 V
VS = 0.6 V/1.65 V, VD = 1.65 V/0.6 V;
Test Circuit 2
VS = VD = 0.6 V or 1.65 V; Test Circuit 3
±4
±25
±10
±75
0.65 VDD
0.35 VDD
V min
V max
±0.1
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 50 , CL = 35 pF
VS = 1.5 V/0 V; Test Circuit 4
RL = 50 , CL = 35 pF
VS = 1.5 V/0 V; Test Circuit 4
RL = 50 , CL = 35 pF
VS1 = VS2 = 1 V; Test Circuit 5
VS = 1 V, RS = 0 , CL = 1 nF;
Test Circuit 6
RL = 50 , CL = 5 pF, f = 100 kHz;
Test Circuit 7
S1A–S2A/S1B–S2B;
RL = 50 , CL = 5 pF, f = 100 kHz;
Test Circuit 10
S1A–S1B/S2A–S2B;
RL = 50 , CL = 5 pF, f = 100 kHz;
Test Circuit 9
RL = 32 , f = 20 Hz to 20 kHz,
VS = 1.2 V p-p
RL = 50 , CL = 5 pF; Test Circuit 8
RL = 50 , CL = 5 pF; Test Circuit 8
0.005
4
Break-before-Make Time Delay (tBBM)
Charge Injection
20
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
–67
dB typ
Channel-to-Channel Crosstalk
–90
dB typ
–67
dB typ
Total Harmonic Distortion, THD
0.14
%
Insertion Loss
–3 dB Bandwidth
CS (OFF)
CD, CS (ON)
–0.08
57
25
75
dB typ
MHz typ
pF typ
pF typ
0.003
µA typ
µA max
POWER REQUIREMENTS
IDD
VDD = 1.8 V, VS = 0 V to VDD, IS = 10 mA;
Test Circuit 1
VDD = 1.65 V, VS = 0 V to VDD, IS = 10 mA
VDD = 1.65 V, VS = 0.7 V, IS = 10 mA
nA typ
nA max
nA typ
nA max
28
37
7
9
21
tOFF
Test Conditions/Comments
38
39
10
11
5
1.0
4
VDD = 1.95 V
Digital Inputs = 0 V or 1.95 V
NOTES
1
Temperature range is as follows: Y version: –40°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. 0
ADG836
ABSOLUTE MAXIMUM RATINGS1
Table I. ADG836 Truth Table
(TA = 25°C, unless otherwise noted.)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Analog Inputs2 . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Inputs2 . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 4.6 V
or 10 mA, Whichever Occurs First
Peak Current, S or D
3.3 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA
2.5 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 mA
1.8 V Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 mA
(Pulsed at 1ms, 10% Duty Cycle Max)
Continuous Current, S or D
3.3 V Operation
300 mA
2.5 V Operation
275 mA
1.8 V Operation
250 mA
Operating Temperature Range
Automotive (Y Version) . . . . . . . . . . . . . . . . –40°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .150°C
MSOP Package
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 206°C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 44°C/W
LFCSP Package
JA Thermal Impedance (3-Layer Board) . . . . . . . . . 61.1°C/W
IR Reflow, Peak Temperature <20 sec . . . . . . . . . . . . . . . .235°C
Logic
Switch A
Switch B
0
1
Off
On
On
Off
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Only one absolute maximum rating
may be applied at any one time.
2
Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be
limited to the maximum ratings given.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding*
ADG836YRM
ADG836YRM-REEL
ADG836YRM-REEL7
ADG836YCP
ADG836YCP-REEL
ADG836YCP-REEL7
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
Mini Small Outline Package (MSOP)
Mini Small Outline Package (MSOP)
Mini Small Outline Package (MSOP)
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
Lead Frame Chip Scale Package (LFCSP)
RM-10
RM-10
RM-10
CP-12
CP-12
CP-12
S9A
S9A
S9A
S9A
S9A
S9A
*Branding on this package is limited to three characters due to space constraints.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily accumulate
on the human body and test equipment and can discharge without detection. Although the ADG836
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high
energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REV. 0
–5–
ADG836
PIN CONFIGURATIONS
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12-Lead LFCSP
(CP-12)
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TERMINOLOGY
VDD
Most positive power supply potential.
IDD
Positive supply current.
GND
Ground (0 V) reference.
S
Source terminal. May be an input or output.
D
Drain terminal. May be an input or output.
IN
Logic control input.
VD (VS)
Analog voltage on terminals D, S.
RON
Ohmic resistance between D and S.
RFLAT (ON)
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured
over the specified analog signal range.
RON
On resistance match between any two channels.
IS (OFF)
Source leakage current with the switch off.
ID (OFF)
Drain leakage current with the switch off.
ID, IS (ON)
Channel leakage current with the switch on.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
CS (OFF)
Off switch source capacitance. Measured with reference to ground.
CD (OFF)
Off switch drain capacitance. Measured with reference to ground.
CD, CS (ON)
On switch capacitance. Measured with reference to ground.
CIN
Digital input capacitance.
tON
Delay time between the 50% and the 90% points of the digital input and switch on condition.
tOFF
Delay time between the 50% and the 90% points of the digital input and switch off condition.
tBBM
On or off time measured between the 80% points of both switches when switching from one to another.
Charge Injection
A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal which is coupled through from one channel to another as a result of parasitic
capacitance.
–3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
THD + N
The ratio of the harmonics amplitude plus noise of a signal, to the fundamental.
–6–
REV. 0
Typical Performance Characteristics–ADG836
0.60
1.2
TA = 25C
VDD = 3.3V
0.55
VDD = 3V
1.0
VDD = 2.7V
ON RESISTANCE ()
ON RESISTANCE ()
0.50
0.45
0.40
VDD = 3.3V
VDD = 3.6V
0.35
0.8
+125C
+85C
0.6
0.4
+25C
0.30
0.20
0
0.5
1.0
1.5
2.0
VD, VS (V)
2.5
3.0
0
3.5
0.6
VDD = 2.5V
ON RESISTANCE ()
ON RESISTANCE ()
2.0
2.5
3.0
1.0
VDD = 2.3V
VDD = 2.7V
0.4
0.3
+125C
0.8
+85C
0.6
+25C
0.4
–40C
0.2
0
0.5
1.0
1.5
2.0
0
2.5
VD, VS (V)
0
0.5
1.0
1.5
1.4
TA = 25C
–40C
VDD = 1.8V
1.2
VDD = 1.65V
+25C
+125C
ON RESISTANCE ()
1.4
1.2
VDD = 1.8V
1.0
0.8
0.6
2.5
TPC 5. On Resistance vs. VD (VS) for Different
Temperature, 2.5 V
1.8
1.6
2.0
VD, VS (V)
TPC 2. On Resistance vs. VD (VS) VDD = 2.5 V ± 0.2 V
ON RESISTANCE ()
1.5
VDD = 2.5V
0.7
1.0
0.8
0.7
+85C
0.5
VDD = 1.95V
0.2
0.4
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0
2.0
VD, VS (V)
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VD, VS (V)
TPC 3. On Resistance vs. VD (VS), VDD = 1.8 V ± 0.15 V
REV. 0
1.0
1.2
TA = 25C
0.2
0.5
TPC 4. On Resistance vs. VD (VS) for Different
Temperatures, 3.3 V
0.8
0.5
0
VD, VS (V)
TPC 1. On Resistance vs. VD (VS) VDD = 2.7 V to 3.6 V
0.2
–40C
0.2
0.25
TPC 6. On Resistance vs. VD (VS) for
Different Temperatures, 1.8 V
–7–
1.8
ADG836
80
90
VDD = 3.3V
ID, IS (ON)
70
40
60
20
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TA = 25ºC
80
60
0
50
40
VCC = 3.3V
–20
–40
20
–60
–80
VCC = 2.5V
30
IS (OFF)
VCC = 1.8V
10
0
20
40
60
80
100
0
120
0
0.5
1.0
1.5
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TPC 7. Leakage Currents vs. Temperature, 3.3 V
60
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20
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CURRENT (nA)
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ID, IS (ON)
10
0
–10
–20
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IS (OFF)
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–30
20
40
60
80
100
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120
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TEMPERATURE (C)
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TPC 11. tON/tOFF Times vs. Temperature
TPC 8. Leakage Current vs. Temperature, 2.5 V
50
3.5
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30
0
3.0
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40
–40
2.5
TPC 10. Charge Injection vs. Source Voltage
VDD = 2.5V
50
2.0
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VDD = 1.8V
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40
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ATTENUATION (dB)
CURRENT (nA)
30
IS, ID (ON)
20
10
0
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TA = 25ºC
VCC = 3.3V/2.5V/1.8V
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IS (OFF)
–10
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–20
0
20
40
60
80
100
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120
TEMPERATURE (C)
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TPC 9. Leakage Current vs. Temperature, 1.8 V
TPC 12. Bandwidth
–8–
REV. 0
ADG836
0.10
0
VDD = 2.5V
TA = 25C
S1A–D1
32 LOAD
0.08 1.5V p-p
–10
TA = 25ºC
VCC = 3.3V/2.5V/1.8V
–30
THD + N (%)
ATTENUATION (dB)
–20
–40
–50
–60
0.06
0.04
0.02
–70
–80
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ATTENUATION (dB)
TA = 25ºC
VCC = 3.3V/2.5V/1.8V
–40
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–60
–70
–80
–90
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TPC 14. Crosstalk vs. Frequency
REV. 0
200
500
1k
2k
5k
10k
TPC 15. Total Harmonic Distortion + Noise
TPC 13. Off Isolation vs. Frequency
–100
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FREQUENCY (Hz)
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50
–9–
20k
ADG836
Test Circuits
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Test Circuit 2. Off Leakage
Test Circuit 3. On Leakage
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Test Circuit 4. Switching Times, tON, tOFF
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Test Circuit 5. Break-before-Make Time Delay, tBBM
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Test Circuit 6. Charge Injection
–10–
REV. 0
ADG836
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Test Circuit 9. Channel-to-Channel Crosstalk (S1A–S1B)
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Test Circuit 10. Channel-to-Channel Crosstalk (S1A–S2A)
Test Circuit 8. Bandwidth
REV. 0
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Test Circuit 7. Off Isolation
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–11–
ADG836
OUTLINE DIMENSIONS
10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
C04308–0–8/03(0)
3.00 BSC
6
10
4.90 BSC
3.00 BSC
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.00
0.27
0.17
SEATING
PLANE
0.80
0.60
0.40
8
0
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA
12-Lead Lead Frame Chip Scale Package [LFCSP]
(CP-12)
Dimensions shown in millimeters
3.00
BSC SQ
0.60 MAX
0.45
PIN 1
INDICATOR
0.75
0.55
0.35
2.75
BSC SQ
TOP
VIEW
9
10
11
12
BOTTOM
VIEW
8
7
6
12 MAX
SEATING
PLANE
4
2
3
0.50
BSC
0.80 MAX
0.65 TYP
1.00
0.85
0.80
5
1
PIN 1 INDICATOR
1.45
1.30 SQ*
1.15
0.25 MIN
0.05 MAX
0.02 NOM
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-1
EXCEPT FOR EXPOSED PAD DIMENSION
–12–
REV. 0