a FEATURES 5.5 ⍀ (Max) On Resistance 0.9 ⍀ (Max) On-Resistance Flatness 2.7 V to 5.5 V Single Supply ⴞ2.7 V to ⴞ5.5 V Dual Supply Rail-to-Rail Operation 10-Lead SOIC Package Typical Power Consumption (<0.01 W) TTL/CMOS Compatible Inputs APPLICATIONS Automatic Test Equipment Power Routing Communication Systems Data Acquisition Systems Sample and Hold Systems Avionics Relay Replacement Battery-Powered Systems CMOS ⴞ5 V/5 V 4 ⍀ Dual SPST Switches ADG621/ADG622/ADG623 FUNCTIONAL BLOCK DIAGRAM ADG621 ADG622 S1 S1 IN1 IN1 D1 D1 D2 D2 IN2 IN2 S2 S2 ADG623 S1 IN1 D1 D2 IN2 S2 SWITCHES SHOWN FOR A LOGIC "0" INPUT GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG621, ADG622, and the ADG623 are monolithic, CMOS SPST (single-pole, single-throw) switches. Each switch of the ADG621, ADG622, and ADG623 conducts equally well in both directions when on. 1. Low On Resistance (RON) (4 Ω typ) The ADG621/ADG622/ADG623 contain two independent switches. The ADG621 and ADG622 differ only in that both switches are normally open and normally closed respectively. In the ADG623, Switch 1 is normally open and Switch 2 is normally closed. The ADG623 exhibits break-before-make switching action. 2. Dual ± 2.7 V to ± 5.5 V or Single 2.7 V to 5.5 V 3. Low Power Dissipation. CMOS construction ensures low power dissipation. 4. Tiny 10-Lead µSOIC Package The ADG621/ADG622/ADG623 offers low on-resistance of 4 Ω, which is matched to within 0.25 Ω between channels. These switches also provide low power dissipation yet gives high switching speeds. The ADG621, ADG622, and ADG623 are available in a 10-lead µSOIC package. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 ADG621/ADG622/ADG623–SPECIFICATIONS DUAL SUPPLY1 (VDD = +5 V ⴞ 10%, VSS = –5 V ⴞ 10%, GND = 0 V. All specifications –40ⴗC to +85ⴗC unless otherwise noted.) B Version –40ⴗC to +25ⴗC +85ⴗC Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) 4 5.5 On Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) 0.25 0.35 0.9 ± 0.01 ± 0.25 ± 0.01 ± 0.25 ± 0.01 ± 0.25 Unit VSS to VDD V 7 Ω typ Ω max 0.4 0.9 1.5 Ω typ Ω max Ω typ Ω max Test Conditions/Comments VDD = +4.5 V, VSS = –4.5 V VS = ± 4.5 V, IS = –10 mA, Test Circuit 1 VS = ± 4.5 V, IS = –10 mA VS = ± 3.3 V, IS = –10 mA VDD = +5.5 V, VSS = –5.5 V VS = ± 4.5 V, VD = ⫿4.5 V, Test Circuit 2 VS = ± 4.5 V, VD = ⫿4.5 V, Test Circuit 2 VS = VD = ± 4.5 V, Test Circuit 3 ±1 nA typ nA max nA typ nA max nA typ nA max 2.4 0.8 V min V max ± 0.1 µA typ µA max pF typ VIN = VINL or VINH 110 ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation –65 dB typ Channel-to-Channel Crosstalk –90 dB typ Bandwidth –3 dB CS (OFF) CD (OFF) CD, CS (ON) 230 20 20 70 MHz typ pF typ pF typ pF typ RL = 300 Ω, CL = 35 pF VS = 3.3 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS = 3.3 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.3 V, Test Circuit 5 VS = 0 V, RS = 0 Ω, CL = 1 nF, Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 8 RL = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 10 RL = 50 Ω, CL = 5 pF, Test Circuit 9 f = 1 MHz f = 1 MHz f = 1 MHz 0.001 µA typ µA max µA typ µA max Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH ±1 ±1 0.005 CIN, Digital Input Capacitance 2 2 DYNAMIC CHARACTERISTICS tON tOFF Break-Before-Make Time Delay, tBBM (ADG623 Only) Charge Injection POWER REQUIREMENTS IDD 75 120 45 70 30 155 85 10 1.0 ISS 0.001 1.0 VDD = +5.5 V, VSS = –5.5 V Digital Inputs = 0 V or 5.5 V Digital Inputs = 0 V or 5.5 V NOTES 1 Temperature ranges are as follows: B Version, –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. –2– REV. 0 ADG621/ADG622/ADG623 SINGLE SUPPLY1 (VDD = +5 V ⴞ 10%, VSS = 0 V, GND = 0 V. All specifications –40ⴗC to +85ⴗC unless otherwise noted.) Parameter B Version – 40ⴗC to +25ⴗC +85ⴗC ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (∆RON) On-Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source OFF Leakage IS (OFF) 7 10 0.5 0.75 0.5 ± 0.01 ± 0.25 ± 0.01 ± 0.25 ± 0.01 ± 0.25 Unit 0 V to VDD V 12.5 Ω typ Ω max 1 0.5 1 Ω typ Ω max Ω typ Ω max Test Conditions/Comments VDD = 4.5 V, VSS = 0 V VS = 0 V to 4.5 V, IS = –10 mA, Test Circuit 1 VS = 0 V to 4.5 V, IS = –10 mA VS = 1.5 V to 3.3 V, IS = –10 mA VDD = 5.5 V VS = 1 V/4.5 V, VD = 4.5 V/1 V, Test Circuit 2 VS = 1 V/4.5 V, VD = 4.5 V/1 V, Test Circuit 2 VS = VD = 1 V/4.5 V, Test Circuit 3 ±1 nA typ nA max nA typ nA max nA typ nA max 2.4 0.8 V min V max ± 0.1 µA typ µA max pF typ VIN = VINL or VINH 6 ns typ ns max ns typ ns max ns typ ns min pC typ Off Isolation –65 dB typ Channel-to-Channel Crosstalk –90 dB typ Bandwidth –3 dB CS (OFF) CD (OFF) CD, CS (ON) 230 20 20 70 MHz typ pF typ pF typ pF typ RL = 300 Ω, CL = 35 pF VS = 3.3 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF VS = 3.3 V, Test Circuit 4 RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3.3 V, Test Circuit 5 VS = 0 V; RS = 0 Ω, CL = 1 nF, Test Circuit 6 RL = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 7 RL = 50 Ω, CL = 5 pF, f = 1 MHz, Test Circuit 9 RL = 50 Ω, CL = 5 pF, Test Circuit 8 f = 1 MHz f = 1 MHz f = 1 MHz 0.001 µA typ µA max Drain OFF Leakage ID (OFF) Channel ON Leakage ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS2 tON tOFF Break-Before-Make Time Delay, tBBM (ADG623 Only) Charge Injection POWER REQUIREMENTS IDD ±1 ±1 0.005 2 120 210 50 75 70 260 100 10 1.0 NOTES 1 Temperature ranges are as follows: B Version, –40°C to +85°C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice. REV. 0 –3– VDD = 5.5 V Digital Inputs = 0 V or 5.5 V ADG621/ADG622/ADG623 ABSOLUTE MAXIMUM RATINGS 1 Table I. Truth Table for the ADG621/ADG622 (TA = +25°C unless otherwise noted) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.5 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6.5 V Analog Inputs2 . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V Digital Inputs2 . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V or 30 mA, Whichever Occurs First Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA (Pulsed at 1 ms, 10% Duty Cycle max) Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 50 mA Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C µSOIC Package θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W Lead Temperature, Soldering (10 seconds) . . . . . . . . . . . 300°C IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . 220°C ADG621 INx ADG622 INx Switch x Condition 0 1 1 0 OFF ON Table II. Truth Table for the ADG623 IN1 IN2 Switch S1 Switch S2 0 0 1 1 0 1 0 1 OFF OFF ON ON ON OFF ON OFF NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 2 Overvoltages at IN, S, or D will be clamped by internal diodes. Current should be limited to the maximum ratings given. ORDERING GUIDE Model Option Temperature Range Description Package Branding Information* ADG621BRM ADG622BRM ADG623BRM –40°C to +85°C –40°C to +85°C –40°C to +85°C µSOIC (microSmall Outline IC) µSOIC (microSmall Outline IC) µSOIC (microSmall Outline IC) RM-10 RM-10 RM-10 SXB SYB SZB *Branding on µSOIC packages is limited to three characters due to space constraints. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG621/ADG622/ADG623 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 ADG621/ADG622/ADG623 PIN CONFIGURATION 10-Lead SOIC (RM-10) S1 1 D1 2 IN2 3 GND 4 VSS 5 10 ADG621/ ADG622/ ADG623 TOP VIEW (Not to Scale) VDD 9 IN1 8 D2 7 S2 6 NC NC = NO CONNECT TERMINOLOGY VDD Most Positive Power Supply Potential. VSS Most Negative Power Supply in a Dual Supply Application. In single supply applications, this should be tied to ground at the device. Ground (0 V) Reference Positive Supply Current Negative Supply Current Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input Ohmic resistance between D and S. On resistance match between any two Channels i.e., RON max – RON min. Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. Source Leakage Current with the switch “OFF.” Drain Leakage Current with the switch “OFF.” Channel Leakage Current with the switch “ON.” Analog Voltage on Terminals D, S. Maximum Input Voltage for Logic “0.” Minimum Input Voltage for Logic “1.” Input Current of the Digital Input “OFF” Switch Source Capacitance “OFF” Switch Drain Capacitance “ON” Switch Capacitance Delay between applying the digital control input and the output switching on. Delay between applying the digital control input and the output switching off. “OFF” time or “ON” time measured between the 90% points of both switches, when switching from one address state to another. A measure of the Glitch Impulse transfered from the Digital input to the Analog output during switching. A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. A measure of unwanted signal coupling through an “OFF” switch. The frequency response of the “ON” switch. The loss due to the ON resistance of the Switch. GND IDD ISS S D IN RON ∆RON RFLAT(ON) IS (OFF) ID (OFF) ID, IS (ON) VD (VS) VINL VINH IINL(IINH) CS (OFF) CD (OFF) CD, CS (ON) tON tOFF tBBM Charge Injection Crosstalk Off Isolation Bandwidth Insertion Loss REV. 0 –5– ADG621/ADG622/ADG623 –Typical Performance Characteristics 10 8 TA = 25ⴗC VDD = 5V VSS = 0V 9 VDD, V SS = ⴞ2.5V 7 8 VDD, V SS = ⴞ3V ON RESISTANCE – ⍀ ON RESISTANCE – ⍀ 6 5 VDD, V SS = ⴞ3.3V 4 3 VDD, V SS = ⴞ4.5V VDD, V SS = ⴞ5V TA = +85ⴗC 7 TA = +25ⴗC 6 TA = –40ⴗC 5 4 3 2 2 1 0 –5 1 –4 –3 –2 –1 0 1 VD, VS – V 2 3 4 0 5 2 4 5 0.5 TA = 25ⴗC VSS = 0V VDD = 2.7V 0.4 0.3 16 LEAKAGE CURRENT – nA VDD = 3V 12 VDD = 3.3V VDD = 4.5V 8 VDD = 5V 0 1 2 3 4 0.2 IS (OFF) 0.1 0 –0.1 ID, IS (ON) 5 VD, VS – V TPC 2. On Resistance vs. VD (VS). (Single Supply) 30 40 50 60 TEMPERATURE – ⴗC 70 80 TPC 5. Leakage Currents vs. Temperature. (Dual Supply) 0.5 6 VDD = +5V VSS = –5V 0.4 5 LEAKAGE CURRENT – nA 0.3 TA = +85ⴗC 4 TA = +25ⴗC 3 TA = –40ⴗC 2 –4 –3 –2 –1 0 1 VD, VS – V 2 3 4 0.2 IS (OFF) 0.1 0 –0.1 ID, IS (ON) ID (OFF) –0.2 –0.3 VDD = 5V VSS = 0V –0.4 VD = 4.5V/1V VS = 1V/4.5V –0.5 0 10 20 1 0 –5 ID (OFF) –0.2 –0.3 VDD = 5V VSS = 0V –0.4 VD = ⴞ4.5V VS = ⴟ4.5V –0.5 0 10 20 4 ON RESISTANCE – ⍀ 3 TPC 4. On Resistance vs. VD (VS) for Different Temperature. (Single Supply) 20 ON RESISTANCE – ⍀ 1 VD, VS – V TPC 1. On Resistance vs. VD (VS). (Dual Supply) 0 0 5 TPC 3. On Resistance vs. VD (VS) for Different Temperatures. (Dual Supply) 30 40 50 60 TEMPERATURE – ⴗC 70 80 TPC 6. Leakage Currents vs. Temperature. (Single Supply) –6– REV. 0 ADG621/ADG622/ADG623 250 0 VDD = +5V VSS = –5V TA = 25ⴗC TA = 25ⴗC –10 –20 VDD = +5V VSS = –5V ATTENUATION – dB CHARGE INJECTION – pC 200 150 100 VDD = 5V VSS = 0V –30 –40 –50 –60 –70 50 –80 0 –5 –4 –3 –2 –1 0 VS 1 2 4 3 0.2 5 TPC 7. Charge Injection vs. Source Voltage VDD ⴝ 5V VSS ⴝ 0V 120 VDD ⴝ +5V VSS ⴝ –5V tON 100 –4 ATTENUATION – dB TIME – ns VDD = +5V VSS = –5V TA = 25ⴗC –2 140 80 60 tOFF 40 VDD ⴝ 5V VSS ⴝ 0V 20 0 –40 –20 0 20 40 TEMPERATURE – C VDD ⴝ +5V VSS ⴝ –5V 60 –20 –30 –40 –50 –60 –70 VDD = +5V VSS = –5V TA = 25ⴗC 10 FREQUENCY – MHz –10 1 10 FREQUENCY – MHz 100 TPC 11. On Response vs. Frequency –10 1 –8 0.2 80 0 –80 –6 –12 TPC 8. tON / tOFF Times vs. Temperature ALTERNATION – dB 100 0 160 100 TPC 9. OFF Isolation vs. Frequency REV. 0 10 FREQUENCY – MHz TPC 10. Crosstalk vs. Frequency 180 0.2 1 –7– 1000 ADG621/ADG622/ADG623 Test Circuits IDS V1 IS (OFF) S VS D VS RON = V1/IDS Test Ciruit 1. On Resistance S NC A VD D NC = NO CONNECT Test Ciruit 2. Off Leakage A VD Test Ciruit 3. On Leakage VSS VDD 0.1F 0.1F VDD VIN ADG621 VSS S VS ID (ON) ID (OFF) S A D VOUT D RL 300⍀ IN VIN ADG622 50% 50% 50% 50% CL 35pF 90% 90% VOUT GND tON tOFF Test Ciruit 4. Switching Times VDD VSS 0.1F 0.1F VDD VS1 VS2 VIN VSS S1 D1 S2 D2 IN1, IN2 VOUT1 VOUT2 RL1 300⍀ VOUT1 CL1 35pF 50% 90% 90% 0V CL2 35pF RL2 300Ω VIN 50% 0V GND VOUT2 90% 90% 0V tBBM tBBM Test Ciruit 5. Break-Before-Make Time Delay, tBBM (ADG623 Only) RS VS VDD VSS VDD VSS S D SW ON SW OFF VIN VOUT CL 1nF IN VOUT QINJ = CL ⴛ ∆VOUT GND ∆VOUT Test Ciruit 6. Charge Injection –8– REV. 0 ADG621/ADG622/ADG623 VSS VDD VDD NETWORK ANALYZER VSS VDD S RL 50⍀ GND OFF ISOLATION = 20 LOG S VOUT 50⍀ VS VIN GND VOUT INSERTION LOSS = 20 LOG VS Test Ciruit 7. Off Isolation VDD NETWORK ANALYZER 0.1F VSS VDD RL 50⍀ D1 S1 S2 D2 R 50⍀ R 50⍀ IN VS GND CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG RL 50⍀ VOUT VS Test Ciruit 8. Channel-to-Channel Crosstalk –9– VOUT VOUT WITH SWITCH VOUT WITHOUT SWITCH Test Ciruit 9. Bandwidth VSS 0.1F REV. 0 NETWORK ANALYZER D VIN 50⍀ VSS IN VS D VOUT 0.1F VDD 50⍀ 50⍀ IN VSS 0.1F 0.1F 0.1F ADG621/ADG622/ADG623 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 10-Lead SOIC Package (RM-10) 0.122 (3.10) 0.114 (2.90) 10 6 0.122 (3.10) 0.114 (2.90) 0.199 (5.05) 0.187 (4.75) 1 5 PIN 1 0.0197 (0.50) BSC 0.037 (0.94) 0.031 (0.78) 0.120 (3.05) 0.112 (2.85) 0.120 (3.05) 0.112 (2.85) 0.043 (1.10) MAX 6ⴗ 0.006 (0.15) 0.012 (0.30) SEATING PLANE 0.009 (0.23) 0ⴗ 0.002 (0.05) 0.006 (0.15) 0.005 (0.13) –10– 0.028 (0.70) 0.016 (0.40) REV. 0 –11– –12– PRINTED IN U.S.A. C02616–.8–10/01(0)