bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 Tablet PC and Netbook 2-Series Cell Li-Ion Battery Gas Gauge and Protection Check for Samples: bq28400 FEATURES • 1 • • • • • • • • • • Fully Integrated Gas Gauge and Analog Monitoring with Protection in a Single Package 2-Series Cell Li-Ion or Li-Polymer Battery Packs Flexible Memory Architecture with Integrated Flash Memory Zero-Volt and Pre-Charge Mode Full Array of Programmable Protection: – OV (Overvoltage) – UV (Undervoltage) – SC (Short Circuit) – OT (Overtemperature) – CIM (Cell Imbalance) Accurate CEDV Gauging Algorithm with Self Discharge Compensation High Accuracy Analog Interface with Two Independent ADCs: – High Resolution 16-Bit Integrator for Coulomb Counting – 16-Bit Delta-Sigma ADC with a 16-Channel Multiplexer for Voltage, Current, and Temperature High Side Protection FET Drive Fully Integrated Internal Clock Synthesizer with No External Components Required Two-Wire SMBus v1.1 Compliant Communications • • • Reduced Power Modes (Typical Battery Pack Operating Range Conditions) – Low Power – Shutdown 20-Pin TSSOP Package (RoHS-Compliant) JEITA/Enhanced Charging Supports SHA-1 Authentication Responder APPLICATIONS • • • • Tablet PCs Slate PCs Netbooks/Notebooks Smartbooks DESCRIPTION The bq28400 device is a fully integrated gas gauge and analog monitoring management solution that provides protection and control for 2-series cell Li-Ion battery packs in a single TSSOP package. Implementing the optimum balance of quick response analog hardware-based monitoring and control along with an integrated fast CPU provides the ideal pack-based or in-system Li-Ion battery solution. The bq28400 also provides flexible user programmable settings stored in flash memory for control of critical system parameters such as overcurrent, short circuit, under/overvoltage, and over/undertemperature conditions. The bq28400 communicates with the system host via a two-wire SMBus 1.1 compatible interface, providing high-accuracy reporting and control of battery pack operation. The FET drive and TSSOP package enable a lower cost and small footprint solution along with a simple layout and routing on narrow pack PCBs. AVAILABLE OPTIONS TA –40°C to 85°C (1) (2) (3) PACKAGE (1) 20-PIN TSSOP (PW) Tube bq28400PW (2) 20-PIN TSSOP (PW) Tape and Reel bq28400PWR (3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. A single tube quantity is 50 units. A single reel quantity is 2000 units. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated bq28400 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. BLOCK DIAGRAM and TYPICAL IMPLEMENTATION DSG Fuse Drive FUSE SMBC System Interface Protection Configuration, Status and Control Registers Program Memory User Settings Data Flash Cell Balancing Drive and Cell Selection Multiplexer SMBD Host Interface & Data Management BAT VC1 VC2 VSS CB_EN Standard 15-bit Delta-Sigma A to D Converter bq29200 2nd Level Voltage Protection + Auto Cell Balance Pch FET Drive Pre-Charge Control I/O Power Control , LDO ZVCHG CHG PRES TS1 RB1 VSS PACK REG27 PACK + Cell Voltage Translation Integrating Delta -Sigma A to D Converter Over Current and Short Circuit Protection RSNS SRP PACK – SRN bq28400 2 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 bq28400 PW PACKAGE (TOP VIEW) BAT 1 20 PACK DSG 2 19 CHG VC1 3 18 ZVCHG VC2 4 17 FUSE VSS 5 16 REG27 SRP 6 15 VSS SRN 7 14 RBI TS1 8 13 PRES CB_EN 9 12 SMBC SMBD 10 11 NC PIN FUNCTIONS (1) PIN NAME PIN NUMBER TYPE (1) BAT 1 P Alternate supply input DSG 2 O P-channel discharge FET gate drive VC1 3 AI Sense input for the most positive cell. Also external cell balancing drive output for the most positive cell VC2 4 AI Sense input for the lowest cell. Also external cell balancing drive output for the lowest cell DESCRIPTION VSS 5 P Device ground SRP 6 AI Differential Coulomb Counter input or SRP oversampled ADC input SRN 7 AI Differential Coulomb Counter input or SRN oversampled ADC input TS1 8 I Thermistor 1 input. Connect NTC from this pin to VSS pin CB_EN 9 O Output signal to control cell balancing SMBD 10 I/OD SBS data NC 11 — SMBC 12 I/OD No connection, leave floating PRES 13 I System present RBI 14 P RAM backup pin to provide backup potential to the internal DATA RAM if power is momentarily lost, by using a capacitor attached between RBI and VSS SBS clock VSS 15 P Device ground REG27 16 P 2.7-V regulator. Connect a capacitor between REG27 and VSS FUSE 17 O Push-pull fuse circuit drive ZVCHG 18 O P-channel precharge FET gate drive CHG 19 O P-channel charge FET gate drive PACK 20 P Alternate supply input P = Power Connection, O = Digital Output, AI = Analog Input, I = Digital Input, I/OD = Digital Input/Output 3 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 www.ti.com THERMAL INFORMATION bq28400 THERMAL METRIC (1) PW UNITS 20 PINS Junction-to-ambient thermal resistance (2) qJA 91.7 (3) qJC(top) Junction-to-case(top) thermal resistance qJB Junction-to-board thermal resistance yJT Junction-to-top characterization parameter yJB Junction-to-board characterization parameter qJC(bottom) (1) (2) (3) (4) (5) (6) (7) 20.4 (4) 45.6 (5) Junction-to-case(bottom) thermal resistance °C/W 0.5 (6) 43.3 (7) n/a For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining qJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature (unless otherwise noted) (1) Value/Unit Supply voltage range, VMAX PACK w.r.t. VSS –0.3 to 34 V VVC2 –0.3 to VVC2 + 8.5 or 34 V, whichever is lower VC1, BAT VC2 VVSRP –0.3 to VVSRP + 8.5 V SRP, SRN –0.3 to VREG27 General Purpose open-drain I/O pins: SMBD, SMBC Input voltage range, VIN General Purpose push-pull I/O pins: TS1, PRES, CB_EN –0.3 V to VREG27 + 0.3 V Input voltage range to all other pins, VIN relative to VSS –0.3 V to VREG27 + 0.3 V DSG, CHG, ZVCHG RBI, REG27 –0.3 to 2.75 V Maximum Operational VSS current, ISS 50 mA Ambient Temperature, TA –20 to 110°C Storage temperature range, TSTG ESD Machine Model (1) (2) –0.3 to BAT –0.3 to [BAT or PACK] (whichever is lower) FUSE ESD Human Body Model (2) VSS –0.3 V to 6 V –65 to 150°C All pins except VC1 and VC2 2 kV VC1 and VC2 1 kV All pins 200 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. 4 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PIN Supply voltage V(STARTUP) BAT Minimum startup voltage VIN MIN NOM MAX PACK Input Voltage Range 3.8 VVC2 + 5 Start up voltage at PACK 5.5 V VVC2 VVC2 + 5 V VC2 VVSRP VVSRP + 5 V VC1 – VC2 5.2 SRP to SRN External 2.7 V REG capacitor TOPR Operating temperature V VC1, BAT 0 PACK C(REG27) UNIT VBAT + 5 5 V 18.75 V 1 V –0.3 1 µF –20 85 °C ELECTRICAL CHARACTERISTICS Typical values stated where TA = 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA = –20ºC to 85ºC and VBAT = VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted) TEST CONDITION (1) PARAMETER MIN TYP MAX UNIT General Purpose I/O VIH High-level input voltage SMBD, SMBC, PRES VIL Low-level input voltage SMBD, SMBC, PRES VOH Output voltage high PRES, IL = –0.5 mA 2 V 0.8 VREG27 – 0.5 V VBAT = 3.8 V to 9 V, CL = 1 nF 3 VBAT – 0.3 8.6 VBAT = 9 V to 10 V, CL = 1 nF 7.5 8 9 VOH(FUSE) High level Fuse output tR(FUSE) FUSE output rise time CL = 1 nF, VOH(FUSE) = 0 V to 5 V IO(FUSE) FUSE output current FUSE active ZO(FUSE) FUSE output impedance VFUSE_DET FUSE Detect Input Voltage VOL Low-level output voltage CIN Input capacitance I(VOUT) VOUT source currents VO active, VO = VREG27 – 0.6 V ILKG(VOUT) VOUT leakage current VO inactive ILKG Input leakage current SMBD, SMBC, PRES, TS1 RPD(SMBx) SMBD and SMBC, pull-down resistor TA = –20°C to 100°C RPAD Pad resistance 10 –3 0.8 V V µs mA 2 6 kΩ 2 3.2 V 0.4 V SMBD, SMBC, TS1, IL = 7 mA 5 pF –3 mA –0.2 0.2 µA 1 µA 950 1300 kΩ TS1 87 110 Ω Normal Mode No flash memory write, No I/O activity 400 µA ILPM Low-Power Mode CPU=HALT CHG=DSG=PCHG=OFF LDO ON but no load, no communication, BAT = 7.2 V 55 µA ISHUTDOWN Shutdown Mode TA = –20°C to 110°C 0.5 1 µA 600 Supply Current ICC REG27 Power On Reset VREG27IT– Negative-going voltage input, at REG27 2.22 2.29 2.34 V VREG27IT+ Positive-going voltage input, at REG27 2.25 2.5 2.6 V Flash Data retention (1) 10 Years By default: SMBus has internal pull-down. 5 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values stated where TA = 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA = –20ºC to 85ºC and VBAT = VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted) TEST CONDITION (1) PARAMETER Flash programming write-cycles tROWPROG Row programming time tMASSERASE Mass-erase time tPAGEERASE Page-erase time ICC(PROG) Flash-write supply current ICC(ERASE) Flash-erase supply current MIN TYP MAX 20k UNIT Cycles 2 ms 250 25 4 6 TA = –40°C to 0°C 8 22 TA = 0°C to 85°C 3 15 VRBI > V(RBI)MIN, VREG27 < VREG27IT–, TA = 70°C to 110°C 20 1500 mA RAM Backup RBI data-retention input current I(RBI) V(RBI) nA VRBI > V(RBI)MIN, VREG27 < VREG27IT–, TA = –20°C to 70°C RBI data-retention voltage (2) 500 1 V Internal LDO VREG Regulator output voltage Regulator Output Current IREG IREG27 = 10 mA, TA = –20°C to 85°C 2.5 PACK and BAT ≤ 4.5 V, TA = –20°C to 110°C 3 4.5 V < PACK and BAT ≤ 6.8 V 10 6.8 V < PACK and BAT ≤ 18.7 5 V, TA = –20°C to 70°C 16 2.7 2.75 V mA ΔV(REGTEMP) Regulator output change with temperature IREG = 10 mA, TA = –20°C to 85°C ΔV(REGLINE) Line regulation IREG = 10 mA ±2 ±4 mV ΔV(REGLOAD) Load regulation IREG = 0.2 to 10 mA ±20 ±40 mV I(REGMAX) Current limit 50 mA (2) ±0. 5% 25 Specified by design. Not production tested. 6 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) Typical values stated where TA = 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA = –20ºC to 85ºC and VBAT = VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted) TEST CONDITION (1) PARAMETER MIN TYP MAX VWAKE = 1.2 mV 0.2 1.2 2 VWAKE = 2.4 mV 0.4 2.4 3.6 VWAKE = 5 mV 2 5 6.8 VWAKE = 10 mV 5.3 10 13 UNIT SRx Wake from Sleep VWAKE_ACR Accuracy of VWAKE VWAKE_TCO Temperature drift of VWAKE accuracy 0.5 tWAKE Time from application of current and wake of bq28400 0.2 mV %/°C 1 ms Coulomb Counter Input voltage range –0.20 Conversion time Single conversion Effective resolution Single conversion Integral nonlinearity TA = –20 to 85°C Offset error (3) Bits ±0.007 TA = –20 to 85°C ±0.034 %FSR 0.3 0.5 µV/°C 0.2% 0.8% 10 (4) –0.8% Full-scale error drift Effective input resistance µV 150 ADC enabled V ms 15 Offset error drift Full-scale error 0.25 250 2.5 PPM/°C MΩ ADC Input voltage range for TS1 –0.2 Conversion time 31.5 Resolution (no missing codes) Offset error 15 Bits ±0.020 70 Offset error drift Full-scale error Bits –0.1 V to 0.8 x Vref (5) 160 25 VIN = 1 V –0.8% ±0.2% Full –scale error drift %FSR µV µV/°C 0.4% 150 Effective input resistance V ms 16 Effective resolution Integral nonlinearity 0.8 x VREG27 8 PPM/°C MΩ External Cell Balance Drive RBAL_drive Internal pull-down resistance for external cell balance Cell balance ON for VC1, VCx – VCx + 4 V, where x = 1 to 2 3.7 Cell balance ON for VC2, VCx – VCx + 4 V, where x = 1 to 2 1.75 TA = –10ºC to 60ºC ±10 ±20 TA = –20ºC to 85ºC ±10 ±35 kΩ Cell Voltage Monitor CELL Voltage Measurement Accuracy (3) (4) (5) mV Post-Calibration Performance Uncalibrated performance. This gain error can be eliminated with external calibration. Channel to Channel Offset 7 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Typical values stated where TA = 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA = –20ºC to 85ºC and VBAT = VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted) TEST CONDITION (1) PARAMETER MIN TYP MAX UNIT Internal Temperature Sensor TINT Temperature sensor accuracy ±3% °C Thermistor Measurement Support RERR Internal resistor drift R Internal resistor ±230 18 PPM/°C 20 kΩ Internal Thermal Shutdown (6) TMAX Maximum REG27 temperature TRECOVER Recovery hysteresis temperature 125 (6) 175 °C 10 Current Protection Thresholds V(OCD) OCD detection threshold voltage range, typical ΔV(OCDT) OCD detection threshold voltage program step V(SCCT) SCC detection threshold voltage range, typical ΔV(SCCT) SCC detection threshold voltage program step V(SCDT) SCD detection threshold voltage range, typical ΔV(SCDT) SCD detection threshold voltage program step V(OFFSET) SCD, SCC, and OCD offset V(Scale_Err) SCD, SCC, and OCD scale error 50 200 mV 10 –100 mV –300 mV –50 100 mV 450 mV 50 mV –10 10 –10% 10% mV Current Protection Timing t(OCDD) Overcurrent in discharge delay t(OCDD_STEP) OCDD Step options 1 t(SCDD) Short circuit in discharge delay t(SCDD_STEP) SCDD Step options t(SCCD) Short circuit in charge delay t(SCCD_STEP) SCCD Step options t(DETECT) Current fault detect time VSRP-SRN = VTHRESH + 12.5 mV, TA = –20˚C to 85˚C tACC Overcurrent and short circuit delay time accuracy Accuracy of typical delay time with no WDI input 31 ms 2 0 ms 1830 µs 122 0 µs 915 µs 61 35 –50% µs 160 µs 50% P-CH FET Drive VO(FETON) VO(FETOFF) tr tf (6) (7) Output voltage, charge and discharge FETs on Output voltage, charge and discharge FETs off Rise time Fall time VO(FETONDSG) = V(BAT) – V(DSG), RGS = 1 MΩ, TA = –20 to 110°C, BAT = 7.2 V (7) 6 6.5 BAT VO(FETONCHG) = V(PACK) – V(CHG), RGS = 1 MΩ, TA = –20 to 110°C, PACK = 7.2 V (7) 6 6.5 PACK V VO(FETOFFDSG) = V(BAT) – V(DSG), TA = –20°C to 110°C, BAT = 7.2 V 0.2 V VO(FETOFFCHG) = V(PACK) – V(CHG), TA = –20°C to 110°C, PACK = 7.2 V 0.2 V CL = 4700 pF CL = 4700 pF VDSG: 10% to 90% 40 200 VCHG: 10% to 90% 40 200 VDSG : 90% to 10% 40 200 VCHG: 90% to 10% 40 200 V µs Specified by design. Not production tested. For a VBAT or VPACK input range of 3.8 V to 18.75 V, MIN VO(FETON) voltage is 9 V or V(BAT) – 1 V, whichever is less. 8 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 ELECTRICAL CHARACTERISTICS (continued) Typical values stated where TA = 25ºC and VBAT = VPACK = 7.2 V, Min/Max values stated where TA = –20ºC to 85ºC and VBAT = VPACK = 3.8 V to 18.75 V over operating free-air temperature range (unless otherwise noted) TEST CONDITION (1) PARAMETER MIN TYP MAX UNIT 9 9.5 10 V VBAT – 0.5 V 200 µs Pre-Charge/ZVCHG FET Drive V(PreCHGON) VO(PreCHGON) = V(PACK) –V(ZVCHG), pre-charge FET on (8) RGS = 1 MΩ, VPACK = 10 V V(PreCHGOFF) Output voltage, pre-charge FET off RGS = 1 MΩ, TA = –20°C to 110°C tr Rise time CL = 4700 pF, RG = 5.1 kΩ VZVCHG: 10% to 90% 80 tf Fall time CL = 4700 pF, RG = 5.1 kΩ VZVCHG: 90% to 10% 1.7 fSMB SMBus operating frequency Slave mode, SMBC 50% duty cycle fMAS SMBus master clock frequency Master mode, no clock low slave extend tBUF Bus free time between start and stop tHD:STA Hold time after (repeated) start tSU:STA Repeated start setup time tSU:STO Stop setup time (8) ms SMBus tHD:DAT Data hold time tSU:DAT Data setup time tTIMEOUT Error signal/detect tLOW Clock low period tHIGH kHz µs 4 µs 4.7 µs 4 µs Transmit mode 300 ns 250 Clock high period See (10) tLOW:SEXT Cumulative clock low slave extend time See tLOW:MEXT Cumulative clock low master extend time tf Clock/data fall time kHz 4.7 0 (9) Clock/data rise time 100 51.2 Receive mode See tr 10 25 ns 35 4.7 4 ms µs 50 µs (11) 25 ms See (12) 10 ms See (13) 300 ns See (14) 1000 ns (8) For a VBAT or VPACK input range of 3.8 V to 18.75 V, MIN VO(FETON) voltage is 9 V or V(BAT) – 1 V, whichever is less. (9) The bq28400 times out when any clock low exceeds tTIMEOUT. (10) tHIGH:MAX is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 µs causes reset of any transaction involving bq28400 that is in progress. (11) tLOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. (12) tLOW:MEXT is the cumulative time a master device is allowed to extend the clock cycles in one message from initial start to the stop. (13) Rise time tr = VILMAX – 0.15) to (VIHMIN + 0.15). (14) Fall time tf = 0.9VDD to (VILMAX – 0.15). 9 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 www.ti.com PIN EQUIVALENT CIRCUITS VC1,VC2 BAT BAT DSG 1 MΩ ESD BAT DSG VC1 and VC2 REG27 REG27 57 Ω SRP SRN TS1 50 Ω 50 Ω 10 Ω 20 Ω 264Ω SRP and SRN TS1 REG27 REG27 PACK SMBD SMBC ZVCHG 1 KΩ 50 Ω 1 KΩ INT EV 50 Ω 10 Ω 50 Ω 264 W 264 W SMBD and SMBC PRES 10 ZVCHG Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 BAT PACK BAT 2 KW FUSE PACK REF + - REG27 1 KW ESD 7.5 V 10 KW 1 KW REG27 FUSE PACK PACK REG27 CHG 1.25 KW 10 W ESD RBI CHG RBI 11 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 www.ti.com TIMING CIRCUITS tr t SU(STO) tf tf tHD(STA) tBUF t HIGH SMBC SMBC SMBD SMBD P tr S t LOW tHD(DAT) Start and Stop Condition t SU(DAT) Wait and Hold Condition tSU(STA) t TIMEOUT SMBC SMBC SMBD SMBD S Timeout Condition Repeated Start Condition Figure 1. Timing Conditions GENERAL OVERVIEW The bq28400 has a flexible architecture that enables development of numerous battery-management solutions. The device is a fully integrated battery manager, as shown in the functional block diagram, and performs necessary calculations and control for a fully functional 2-series cell battery management system. The device provides flexible user settings that are stored in flash memory. The bq28400 determines battery capacity by monitoring the amount of charge input or removal from 2-series cell Li-Ion rechargeable batteries via a small value series sense resistor. The device then controls and reports the battery status using corrections for environmental and operating conditions. Additional control and monitoring is implemented for individual cell voltages, temperature, and current. 12 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 FEATURE SET Safety Features The bq28400 supports a wide range of battery and system protection features that can be configured. The primary safety features include: • • • • • Cell over/undervoltage protection Overcurrent during charge and discharge Short circuit Overtemperature during charge and discharge Device watchdog timer The secondary safety features used to indicate more serious faults which can be used to control FET state or blow an in-line fuse to permanently disable the battery pack include: • Safety overvoltage • Safety undervoltage • Safety overcurrent in charge and discharge • Safety overtemperature in charge and discharge • Charge, pre-charge, and discharge FET fault • Cell imbalance detection Charge Control The bq28400 charge control features include: • • • • • Reporting charging current needed for constant current charging and charging voltage needed for constant voltage charging to a smart charger using SMBus communications Supports pre-charging/zero-volt charging Supports fast charging Supports charge inhibit and charge suspend if battery pack temperature is out of temperature range Reports charging fault and also indicate charge status via charge and discharge alarms Gas Gauging The device uses advanced Compensated End-of-Discharge Voltage (CEDV) technology to measure and calculate the available charge capacity in battery cells under system use and environmental conditions. The device accumulates a measure of charge and discharge currents, then compensates the charge current measurement for temperature and the state-of-charge of the battery. The bq28400 further estimates battery self-discharge, adjusts the self-discharge estimation for temperature, and then updates internal status registers. These internal registers are made available to the system host via the two-wire SMBus. The internal general-purpose SRAM can be powered by the RBI pin of the bq28400 if power is lost. Typically, a 0.1-µF capacitor provides the necessary voltage to the SRAM array during inadvertent momentary power loss. See the bq28400 technical reference guide for further details. Lifetime Data Logging The bq28400 maintains the highest temperature value from the last device reset. Power Modes The bq28400 supports three power modes to reduce power consumption: • • In Normal Mode, the device performs measurements, calculations, protection decisions, and data updates in 1-second intervals. Between these intervals, the device is in a reduced power stage. In Sleep Mode, the bq28400 performs measurements, calculations, protection decisions and data updates in longer intervals. Between these intervals, the device is in a reduced power stage. – A wake function operates so that an exit from Sleep mode occurs when current flow, detection of failure, 13 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 • www.ti.com or SMBus activity detected. In Shutdown Mode, the bq28400 is completely disabled by turning off all FETs and powering down the bq28400. CONFIGURATION Oscillator Function The bq28400 fully integrates the system oscillator; therefore, no external components are required for this feature. System Present Operation The device checks the PRES pin periodically. If the PRES pin input is pulled to ground by the external system, the bq28400 detects this event as the presence of the system. 2-Series Cell Configuration The bq28400 supports 2-series cell battery pack configurations. Cell Balancing Configuration If cell balancing is required, the bq28400 cell balance control enables a weak, internal pull-down for each VCx pin. The purpose of this weak pull-down is to enable an external FET for current bypass. Series resistors placed between the input VCx pins and the positive battery cell terminals control the VGS of the external FET. Alternatively, CB_EN output can be used with the bq29200 device to control the auto cell-balancing feature for the system (see Figure 5). Further details are provided in the APPLICATION INFORMATION section of this document. BATTERY PARAMETER MEASUREMENTS The bq28400 uses an integrating delta-sigma analog-to-digital converter (ADC) for current measurement, and a second delta-sigma ADC for individual cell voltage, battery voltage, and temperature measurements. The individual cell voltages, Voltage, Current, AverageCurrent, and Temperature are updated in 1-second intervals during normal operation. Charge and Discharge Counting The integrating ADC measures the charge and discharge flow of the battery by monitoring a small-value sense resistor between the SRP and SRN pins. The bq28400 integrating ADC measures bipolar signals across the SRP and SRN pins from –0.20 V to 0.25 V induced by current through the sense resistor (typically 5 mΩ to 20 mΩ). Charge activity is detected when VSR = VSRP – VSRN is positive and discharge activity when VSR = VSRP – VSRN is negative. The bq28400 continuously integrates the signal over time, using an internal counter and updates RemainingCapacity with the charge or discharge amount every second. Voltage While monitoring the SRP and SRN pins for charge and discharge currents, the bq28400 monitors the individual series cell voltages. The internal bq28400 ADC then measures the voltage, scales, applies offsets, and calibrates it appropriately. NOTE For accurate differential voltage sensing, the VSS ground should be connected directly to the most negative terminal of the battery stack, not to the positive side of the sense resistor. This minimizes the voltage drop across the PCB trace. Voltage Calibration and Accuracy The bq28400 is calibrated for voltage prior to shipping from TI. The bq28400 voltage measurement signal chain (ADC, high voltage translation, circuit interconnect) is calibrated for each cell. The external filter resistors, connected from each cell to the VCx input of the bq28400, are required to be 1 kΩ. If different voltage accuracy is desired, customer voltage calibration is required. 14 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 Current The bq28400 uses the SRP and SRN inputs to measure and calculate the battery charge and discharge current using a 5-mΩ to 20-mΩ typical sense resistor. Temperature The bq28400 has an internal temperature sensor and input pin for an external temperature sensor. The bq28400 can be configured to use either the internal or external temperature sensor. The default setting for the bq28400 is for a Semitec 103AT thermistor as input to the TS1 pin. Reporting of measured temperature is available by way of the SBS Temperature command. 15 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 www.ti.com COMMUNICATIONS The bq28400 uses SMBus v1.1 in Slave Mode per the SBS specification. SBS Commands Table 1. SBS COMMANDS SBS Command Mode Format Min Value Max Value Default Value 0x00 R/W ManufacturerAccess H2 0x0000 0xffff — 0x03 0x08 R/W BatteryMode H2 0x0000 0xe383 — R Temperature U2 0 65535 — 0.1°K 0x09 R Voltage U2 0 65535 — mV 0x0a R Current I2 –32768 32767 — mA 0x0b R AverageCurrent I2 –32768 32767 — mA 0x0c R MaxError U1 0 100 — % 0x0d R RelativeStateOfCharge U1 0 100 — % 0x0f R/W RemainingCapacity U2 0 65535 — mAh or 10 mWh 0x10 R FullChargeCapacity U2 0 65535 7200 mAh 0x14 R ChargingCurrent U2 0 65534 2500 mA 0x15 R ChargingVoltage U2 0 65534 12600 mV 0x16 R BatteryStatus U2 0x0000 0xdbff — 0x17 R/W CycleCount U2 0 65535 0 0x18 R/W DesignCapacity U2 0 65535 7200 mAh 0x19 R/W DesignVoltage U2 0 65535 10800 mV 0x1a R/W SpecificationInfo H2 0x0000 0xffff 0x0031 0x1b R/W ManufactureDate U2 — — 0 0x1c R/W SerialNumber H2 0x0000 0xffff 0x0001 0x20 R/W ManufacturerName S12 — — Texas Inst. ASCII 0x21 R/W DeviceName S8 — — bq28400 ASCII 0x22 R/W DeviceChemistry S5 — — LION ASCII 0x23 R/W ManufacturerData S9 — — — ASCII 0x2f R/W Authenticate S21 — — — ASCII 0x3e R CellVoltage2 U2 0 65535 — mV 0x3f R CellVoltage1 U2 0 65535 — mV Name Unit ASCII Extended SBS Commands Table 2 shows the extended SBS commands for the device. Table 2. Extended SBS Commands SBS Cmd Mode Name Format Size in Bytes Min Value Max Value Default Value 0x61 R/W FullAccessKey hex 4 0x00000000 0xffffffff — 0x63 R/W AuthenKey3 hex 4 0x00000000 0xffffffff — 0x64 R/W AuthenKey2 hex 4 0x00000000 0xffffffff — 0x65 R/W AuthenKey1 hex 4 0x00000000 0xffffffff — 0x66 R/W AuthenKey0 hex 4 0x00000000 0xffffffff — 16 Unit Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 APPLICATION INFORMATION Run Time to Empty To predict how much run time the battery pack can supply to the host system, a “Run Time To Empty” value can be calculated. The SBS host system needs to read, store, and update the following values during a discharging period and average them over a user-determined period of time: • DSG bit of the BatteryStatus register (ensure that it is in discharge mode) • AverageCurrent (mA) – Positive value = charge current – Negative value = discharge current – One minute rolling average of current (the user can accumulate this time for improved granularity) • RemainingCapacity (mAh) Then calculating: RunTimeToEmpty = RemainingCapacity(avg mAh) ÷ AverageCurrent(avg mA) (The result will be in hours. For minutes, the user can take the above results and divide by 60.) Charging Time to Full To predict how much charging time before the battery pack is fully charged, a “Run Time To Full” value can be calculated. The SBS host system needs to read, store, and update the following values during a charging period and average them over a user-determined period of time: • DSG bit of the BatteryStatus register (specify in charge mode) • AverageCurrent (mA) – Positive value = charge current – Negative value = discharge current – One minute rolling average of current (the user can accumulate this time for improved granularity) • RemainingCapacity (mAh) Then calculating: RunTimeToFull = [FullChargeCapacity(avg mAh) – RemainingCapacity(avg mAh)] ÷ AverageCurrent(avg mA) Remaining Capacity Alert To provide enough time for action to be taken when the battery is below a pre-determined capacity, the user may implement a remaining capacity alarm alert in the SMBus host system. To do this, an SMBus read of the RemainingCapacity value should be completed then compared by the SMBus host to a user-selected value. If the read RemainingCapacity value is < the user's Remaining Capacity, then the host system should instruct the user of what action is needed. Remaining Time Alert Similar to the Remaining Capacity notification, the system operation may need an alarm notification based on time rather than remaining capacity. To do this, a determination of the EndTimeToEmpty (as discussed below) and compared by SMBus host to a user-selected remaining time limit value. If the RemainingTimeLimit value is < EndTimeToEmpty, then the host system should instruct the user of the action to be taken. 17 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 www.ti.com Cell Balancing Cell balancing increases the useful life of battery packs. Cell-to-cell differences in self-discharge, capacity, and impedance can lead to different charge states among the cells; however, the charger terminates the charge based on the summed voltage only, which may leave some cells undercharged and others overcharged. To remedy this imbalance and to achieve the goal of having all cells reach 100% state-of-charge at charge termination, it is necessary to reduce the charge added to the overcharged cells by creating a current bypass during charging. Cell balancing in the bq28400 is accomplished by connecting an external parallel bypass load to each cell and enabling the bypass load depending on each individual cell's charge state. The bypass load is typically formed by a P-CH MOSFET and a resistor. The series resistors that connect the cell tabs to VC1~VC2 pins of the bq28400 are required to be 1 kΩ. The bq28400 balances the cells during charge by discharging those cells above the threshold set in Cell Balance Threshold, if the maximum difference in cell voltages exceeds the value programmed in Cell Balance Min. During cell balancing, the bq28400 measures the cell voltages at an interval set in Cell Balance Interval. On the basis of the cell voltages, the bq28400 either selects the appropriate cell to discharge or adjusts the cell balance threshold up by the value programmed in Cell Balance Window when all cells exceed the cell balance threshold or the highest cell exceeds the cell balance threshold by the cell balance window. Cell balancing only occurs when charging current is detected and the cell balance threshold is reset to the value in Cell Balance Threshold at the start of every charge cycle. The threshold is only adjusted once during any balance interval. Sense Time Cell Balance tS Interval VREG Bypass is Active Cell Balance Min Higher Cell Voltage Cell Balance Window Cell Balance Threshold Middle Cell Voltage Lowest Cell Voltage Figure 2. Cell Balance The bq28400 supports cell balancing using an external MOSFET, as illustrated in Figure 3. Figure 3 shows an example of a cell-balancing circuit for a 2-series cell application. In this circuit, Q1 and Q2 are the external MOSFETs—specifically, Si1023 P-channel MOSFETs. These FETs were chosen because of its low gate-to-source threshold voltage. 18 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 CHG FET DSG FET PACK+ CHG 1 KW DSG VC1 0.1 µ F Q1 Cell 1 100 W 1 KW VC2 0.1 µ F Q2 Cell 2 100 W VSS NOTE: Q1 and Q2 are Si1023 type P-CH FETs Figure 3. Internal Cell Balancing Control Circuit PACK + Fuse FUSE DSG ZVCHG PRES CHG TS1 RB1 VSS REG27 PACK 1k 220 k BAT 1k OUT VC2 VC1 SMBD 0.1 µF 1k SMBC bq29200 VDD VC1 bq28400 0.1 µF VC2 0.1 µF CB_EN VC1_CB VSS 360 CD GND 0.22 µF SRN PACK – SRP CB_EN RSNS Figure 4. External Auto Cell Balancing Circuit Layout Recommendations For an accurate differential voltage sensing, the VSS ground should be connected directly to the most negative terminal of the battery stack, not to the positive side of the sense resistor. This minimizes the voltage drop across the PCB trace. 19 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 bq28400 www.ti.com 1 SLUSA61A – OCTOBER 2010 – REVISED DECEMBER 2010 Figure 5. Application Schematic 20 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): bq28400 PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Qty Drawing Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) BQ28400PW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ28400 BQ28400PWR ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ28400 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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