LT4254 Positive High Voltage Hot Swap Controller with Open-Circuit Detect U FEATURES DESCRIPTIO TM The LT®4254 is a high voltage Hot Swap controller that allows a board to be safely inserted and removed from a live backplane. An internal driver controls the high side N-channel MOSFET gate for supply voltages ranging from 10.8V to 36V. The part features an open-circuit detect (OPEN) output that indicates abnormally low load current conditions. Allows Safe Board Insertion and Removal from a Live Backplane Controls Supply Voltage from 10.8V to 36V Foldback Current Limiting Open Circuit and Overcurrent Fault Detect Drives an External N-Channel MOSFET Automatic Retry or Latched Off Operation After Overcurrent Fault Programmable Supply Voltage Power-Up Rate Undervoltage and Overvoltage Protection Open MOSFET Detection ■ ■ ■ ■ ■ ■ ■ ■ ■ The LT4254 features an adjustable analog foldback current limit. If the supply remains in current limit for more than a programmable time, the N-channel MOSFET shuts off, the PWRGD output goes low and the LT4254 either automatically restarts after a time-out delay or latches off until the UV pin is cycled low. The RETRY pin sets whether the part will automatically restart after an overcurrent fault or if it will latch off until the UV pin is cycled low. U APPLICATIO S ■ ■ ■ ■ ■ Hot Board Insertion Electronic Circuit Breaker/Power Bussing Industrial High Side Switch/Circuit Breaker 24V Industrial/Alarm Systems 12V and 24V Distributed Power Systems The PWRGD output indicates when the output voltage rises above a programmed level. An external resistor string from VCC provides programmable undervoltage and overvoltage protection. The LT4254 is available in a 16-lead SSOP package. , LTC and LT are registered trademarks of Linear Technology Corporation. Hot Swap is a trademark of Linear Technology Corporation. U TYPICAL APPLICATIO 24V, 2A Hot Swap Controller R5 0.025Ω VIN 24V Q1 IRF530 D1 CMPZ5241B 11V (SHORT PIN) 16 VCC R1 324k 1 C3 0.1µF R2 40.2k R3 40.2k SENSE GATE UV 13 LT4254 2 4 10 GND 15 C2 33nF OV OPEN TIMER FB RETRY PWRGD GND 8 10 R6 10Ω CL R8 140k GATE 20V/DIV 5 PWRGD UV = 20V OV = 40V PWRGD = 18V VCC 20V/DIV VOUT 20V/DIV R9 40.2k 7 PWRGD 20V/DIV CONTACT BOUNCE R4 27k R7 100Ω C1 10nF LT4254 Start-Up Behavior VOUT 24V 1.5A 4254 TA01 2.5ms/DIV 4245 TA02 4254f 1 LT4254 U W W W ABSOLUTE AXI U RATI GS (Note 1) Supply Voltage (VCC) .................................. – 0.3 to 44V Input Voltage (SENSE, PWRGD) ................. – 0.3 to 44V Input Voltage (GATE) .................................. – 0.3 to 50V Input Voltage (FB, UV, OPEN) ..................... – 0.3 to 44V Input Voltage (OV) ...................................... – 0.3 to 18V Input Voltage (RETRY) ............................... – 0.3 to 15V Minimum Input Voltage (TIMER) ......................... – 0.3V Maximum Input Current (TIMER) ....................... 100µA Operating Temperature LT4254C ................................................. 0°C to 70°C LT4254I ............................................. – 40°C to 85°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U W U PACKAGE/ORDER I FOR ATIO ORDER PART NUMBER TOP VIEW UV 1 16 VCC OV 2 15 SENSE NC 3 14 NC OPEN 4 13 GATE PWRGD 5 12 NC NC 6 11 NC RETRY 7 10 FB GND 8 9 LT4254CGN LT4254IGN GN PART MARKING 4254 4254I TIMER GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125°C, θJA = 130°C/W Consult LTC Marketing for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 24V unless otherwise noted. SYMBOL PARAMETER VCC Operating Voltage CONDITIONS ICC Operating Current VUVLH Undervoltage Threshold VUVHYS Hysteresis IINUV UV Input Current UV = 4.5V UV = 0V VOVHL Overvoltage Threshold VCC Low-to-High Transition VOVHYS Hysteresis IINOV OV Input Current VOPEN Open-Circuit Voltage Threshold (VCC – VSENSE) VOLOPEN OPEN Output Low Voltage IINOPEN MIN ● TYP 10.8 1.9 VCC Low-to-High Transition MAX UNITS 36 V 3 mA 3.96 4 4.04 V 0.25 0.4 0.55 V –0.1 –1.5 –1 –3 µA µA 3.96 4 4.04 V 0.25 0.4 0.55 V 0.1 1 µA 2 3.5 5 mV IO = 2mA IO = 5mA 0.20 0.75 0.5 1.3 V V Leakage Current VOPEN = 5V 0.1 1 µA VSENSETRIP SENSE Pin Trip Voltage (VCC – VSENSE) FB = 0V FB ≥ 2V 12 50 25 60 mV mV IINSNS SENSE Pin Input Current 40 70 µA IPU GATE Pull-Up Current – 35 – 55 µA IPD GATE Pull-Down Current Any Fault, VGATE = 3V mA ∆VGATE External N-Channel Gate Drive (Note 2) VFB FB Voltage Threshold VFBHYS FB Hysteresis Voltage VOLPGD PWRGD Output Low Voltage ● ● 0V ≤ OV < 6.5V ● Charge Pump On, ∆VGATE = 7V ● ● 5.5 40 ● –15 40 60 80 VGATE – VCC, 12V ≤ VCC ≤ 20V 20V ≤ VCC ≤ 36V ● ● 4.5 10 8.8 11 12.5 12.5 V V FB High-to-Low Transition FB Low-to-High Transition ● ● 3.96 4.20 4 4.45 4.04 4.65 V V 0.3 0.45 0.60 V 0.25 0.63 0.4 1.0 V V IO = 1.6mA IO = 5mA 4254f 2 LT4254 ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VCC = 24V unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX 0.1 10 –1 –0.1 – 60 – 120 ● 1 ● 1.5 ● IPWRGD PWRGD Pin Leakage Current VPWRGD = 36V IINFB FB Input Current FB = 4.5V ITIMERPU TIMER Pull-Up Current ● ITIMERPD TIMER Pull-Down Current DTIMER Duty Cycle (RETRY Mode) VRETRY(TH) RETRY Threshold IINRTR RETRY Input Current RETRY = GND tPHLUV UV Low to GATE Low CGATE = 100pF 1.7 µs tPLHUV UV High to GATE High CGATE = 100pF 6 µs tPHLFB FB Low to PWRGD Low 0.8 µs tPLHFB FB High to PWRGD High 3.2 µs tPHLSENSE (VCC – VSENSE) High to GATE Low µA µA –180 µA 3 5 µA 3 4.5 % 0.4 0.8 1.2 V –120 –85 –40 µA VCC – VSENSE = 275mV Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. UNITS 2.5 µs 4 Note 2: An internal clamp limits the GATE pin to a maximum of 11V above VCC (under normal operating conditions). Driving this pin to a voltage beyond the clamp voltage may damage the part. U W TYPICAL PERFOR A CE CHARACTERISTICS SENSE Pin Regulation Voltage vs Temperature, FB = 0V SENSE Pin Regulation Voltage vs Temperature, FB > 2V 15 13 11 9 7 5 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 4254 G01 ICC vs VCC 60 3.0 55 2.5 ICC (mA) SENSE REGULATION VOLTAGE (mV) SENSE REGULATION VOLTAGE (mV) 17 50 45 40 –50 –25 TA = 25°C 2.0 1.5 75 0 25 50 TEMPERATURE (°C) 100 125 4254 G02 1.0 10.8 15.8 25.8 20.8 VCC (V) 30.8 36 4254 G03 4254f 3 LT4254 U W TYPICAL PERFOR A CE CHARACTERISTICS VCC = 24V ICC (mA) 1.8 VCC = 36V VCC = 10.8V 1.6 1.4 1.2 1.0 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 125 PWRGD THRESHOLD VOLTAGE LOW-TO-HIGH (V) 2.0 4.46 4.44 4.42 4.40 4.38 4.36 4.34 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 4254 G04 125 4.02 4.01 4.00 3.99 3.98 3.97 3.96 –50 –25 GATE Pin Pull-Up Current vs Temperature 75 –10 70 380 360 340 320 300 –50 –25 0 25 75 50 TEMPERATURE (°C) 100 IGATE DOWN (mA) 80 IGATE PULL-UP CURRENT (µA) 0 –5 400 –15 –20 –25 –30 –40 45 VGATE – VCC vs Temperature –25 0 25 75 50 TEMPERATURE (°C) 100 VGATE – VCC (V) VGATE –VCC (V) VCC = 10.8V 14 12.5 12 12.0 VCC = 24V, 36V 11.5 VCC = 20V 11.0 6 10.5 5 75 50 25 TEMPERATURE (°C) 0 100 125 4254 G10 100 10.0 –50 –25 125 GATE Drive vs VCC 13.0 GATE DRIVE (VGATE – VCC) (V) VCC = 18V VCC = 12V 75 50 25 TEMPERATURE (°C) 0 4254 G09 VGATE – VCC vs Temperature 9 4 – 50 – 25 40 – 50 – 25 125 10 7 55 4254 G08 12 8 60 50 4254 G07 11 65 –35 –45 –50 125 125 GATE Pin Pull-Down Current vs Temperature 460 420 100 4254 G06 480 440 50 25 75 0 TEMPERATURE (°C) 4254 G05 FB Pin Hysteresis vs Temperature PWRGD HYSTERESIS (mV) FB Pin Threshold Voltage (Highto-Low) vs Temperature PWRGD THRESHOLD VOLTAGE HIGH-TO-LOW (V) FB Pin Threshold Voltage (Lowto-High) vs Temperature ICC vs Temperature TA = 25°C 10 8 6 4 2 50 25 75 0 TEMPERATURE (°C) 100 125 0 10.8 20.8 30.8 36 VCC (V) 4254 G11 4254 G12 4254f 4 LT4254 U W TYPICAL PERFOR A CE CHARACTERISTICS TIMER Pin Pull-Down Current vs Temperature 4.0 3.4 –85 3.5 3.2 –105 –115 –125 –135 –145 –50 –25 50 25 0 75 TEMPERATURE (°C) 100 3.0 ITIMER DOWN (µA) –95 2.5 2.0 1.5 1.0 0 – 50 – 25 125 75 50 25 TEMPERATURE (°C) 0 100 4.8 TA = 25°C ITIMER UP (µA) 4.4 –116 4.2 –118 100 –120 10.8 125 15.8 25.8 20.8 VCC (V) 30.8 4.01 450 3.97 3.64 3.63 3.62 3.61 3.60 3.59 3.58 – 50 – 25 125 4254 G19 75 50 25 TEMPERATURE (°C) 0 400 350 300 200 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 100 125 OV Threshold Voltage (Low-toHigh) vs Temperature 250 100 3.65 4254 G18 OV THRESHOLD VOLTAGE (LOW-TO-HIGH) (V) 500 UV HYSTERESIS (mV) UV THRESHOLD VOLTAGE LOW-TO-HIGH (V) 4.02 36 30.8 3.66 UV Hysteresis vs Temperature 3.98 25.8 4254 G17 UV Threshold Voltage (Low-toHigh) vs Temperature 3.99 20.8 4254 G15 36 4254 G16 4.00 15.8 UV Threshold Voltage (High-toLow) vs Temperature –114 50 25 75 0 TEMPERATURE (°C) 2.4 VCC (V) –112 3.96 –50 –25 2.6 2.0 10.8 125 UV THRESHOLD VOLTAGE HIGH-TO-LOW (V) –110 50 25 0 75 TEMPERATURE (°C) 2.8 ITIMER Up vs VCC 5.0 4.0 –50 –25 3.0 4254 G14 Timer Shutdown Threshold vs Temperature 4.6 TA = 25°C 2.2 0.5 4254 G13 TIMER SHUTDOWN THRESHOLD VOLTAGE (V) TIMER Pin Pull-Down Current vs VCC –75 TIMER PULL-DOWN CURRENT (µA) TIMER PULL-UP CURRENT (µA) TIMER Pin Pull-Up Current vs Temperature 125 4254 G20 4.02 4.01 4.00 3.99 3.98 3.97 3.96 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 4257 G21 4254f 5 LT4254 U W TYPICAL PERFOR A CE CHARACTERISTICS OV Hysteresis vs Temperature 3.70 OPEN Output Voltage vs ILOAD 10 500 450 3.60 3.55 400 350 75 0 25 50 TEMPERATURE (°C) 100 125 4 2 200 –50 –25 0 50 25 75 0 TEMPERATURE (°C) 100 4254 G22 125 0 2 4 6 8 ILOAD (mA) 10 12 4254 G24 4254 G23 OPEN Pin Threshold Voltage vs Temperature PWRGD Output Voltage vs ILOAD 6 5.0 TA = 25°C 5 4.5 PWRGD VOL (V) OPEN THRESHOLD VOLTAGE (mV) 6 300 250 3.50 –50 –25 TA = 25°C 8 OPEN VOL (V) 3.65 OV HYSTERESIS (mV) OV THRESHOLD VOLTAGE (HIGH-TO-LOW) (V) OV Threshold Voltage (High-toLow) vs Temperature 4.0 4 3 2 3.5 1 3.0 –50 –25 0 75 0 25 50 TEMPERATURE (°C) 100 125 4254 G25 0 2 4 6 8 ILOAD (mA) 10 12 4254 G26 U U U PI FU CTIO S VCC: Input Supply Voltage. The positive supply input ranges from 10.8V to 36V for normal operation. ICC is typically 1.9mA. An internal circuit disables the LT4254 for inputs less than 9.8V (typ). GND: Device Ground. This pin must be tied to a ground plane for best performance. FB: Power Good Comparator Input. FB monitors the output voltage through an external resistive divider. When the voltage on the FB pin is lower than the high-to-low threshold of 4V, the PWRGD pin is pulled low and released when the FB pin is pulled above the 4.45V low-to-high threshold. The FB pin also affects foldback current limit (see Figure␣ 7 and related discussion). To disable PWRGD monitoring, connect FB to the output voltage and float the PWRGD pin. TIMER: Timing Input. An external timing capacitor from TIMER to GND programs the maximum time the part is allowed to remain in current limit. When the part goes into current limit, a 120µA pull-up current source starts to charge the timing capacitor. When the voltage on the TIMER pin 4254f 6 LT4254 U U U PI FU CTIO S reaches 4.65V (typ), the GATE pin is pulled low; the TIMER pull-up current will be turned off and the capacitor is discharged by a 3µA pull-down current. When the TIMER pin falls below 0.65V (typ), the GATE pin turns on again if the RETRY pin is high (if the RETRY pin is low, the UV pin must be pulsed low to reset the internal fault latch before the GATE pin will turn on). If the RETRY pin is grounded and the UV pin is not cycled low, the GATE pin remains latched off and the TIMER pin will be discharged near ground. The UV pin must be cycled low after the TIMER pin has discharged below 0.65V (typ) to reset the part. If the RETRY pin is floating or connected to a voltage above its 1.2V threshold, the LT4254 automatically restarts after a current fault. Under an output short-circuit condition, the LT4254 cycles on and off with a 3% on-time duty cycle. RETRY: Current Fault Retry. RETRY commands the operational mode of the current limit. If the RETRY pin is floating, the LT4254 automatically restarts after a current fault. If it is connected to a voltage below 0.4V, the part latches off after a current fault (which requires that the UV pin be cycled low in order to start normal operation again). GATE: High Side Gate Drive for the External N-Channel MOSFET. An internal charge pump guarantees at least 10V of gate drive for VCC supply voltages above 20V and 4.5V gate drive for VCC supply voltages between 10.8V and 20V. The rising slope of the voltage on GATE is set by an external capacitor connected from the GATE pin to GND and an internal 35µA pull-up current source from the charge pump output. If the current limit is reached, the GATE pin voltage is adjusted to maintain a constant voltage across the sense resistor while the timing capacitor starts to charge. If the TIMER pin voltage ever exceeds 4.65V, the GATE pin is pulled low. The GATE pin is also pulled to GND whenever the UV pin is pulled low, or the VCC supply voltage drops below the externally programmed undervoltage threshold or above the overvoltage threshold. The GATE pin is clamped internally to a maximum voltage of 11V (typ) above VCC under normal operating conditions. Driving this pin beyond the clamp voltage may damage the part. A zener diode is needed between the gate and source of the external MOSFET to protect its gate oxide under instantaneous short-circuit conditions. See Applications Information. SENSE: Current Limit Sense. A sense resistor is placed in the supply path between VCC and SENSE. The current limit circuit regulates the voltage across the sense resistor (VCC – SENSE) to 50mV while in current limit when FB is 2V or higher. If FB drops below 2V, the regulated voltage across the sense resistor decreases linearly and stops at 15mV when FB is 0V. The OPEN output also uses SENSE to detect when the output current is less than (3.5mV)/R5. To defeat current limit, connect SENSE to VCC. PWRGD: Open Collector Output to GND. PWRGD is pulled low whenever the voltage on FB falls below the high-to-low threshold voltage. It goes into a high impedance state when the voltage on FB exceeds the low-to-high threshold voltage. An external pull-up resistor can pull PWRGD to a voltage higher or lower than VCC. To disable PWRGD, float this pin and connect FB to the output voltage. UV: Undervoltage Sense. UV is an input that enables the output voltage. When the UV pin is driven above 4V, the GATE pin starts charging and the output turns on. When the UV pin goes below 3.6V, the GATE pin discharges and the output shuts off. Pulsing the UV pin to ground after a current limit fault cycle (TIMER pin dischaged to below 0.65V typ) resets the fault latch (when RETRY pin is low, commanding latch off operation) and allows the part to turn back on. To disable UV sensing, connect the pin to VCC through a 10k resistor. OV: Overvoltage Sense. OV is an input that disables the output voltage. If OV ever goes above 4V, the GATE pin is discharged and the output shuts off. When OV goes below 3.6V, the GATE pin starts charging and the output turns back on. To disable OV sensing, connect pin to ground. OPEN: Open Circuit Detect Output. This pin is an open collector output that releases and is pulled high through an external resistor if the load current is less than (3.5mV/R5). If not used, leave this pin disconnected. 4254f 7 LT4254 W BLOCK DIAGRA VCC SENSE 16 15 +OPENCIRCUIT DETECT 3.5mV 4 OPEN – VP VP GEN FB 10 – 12mV ~ 50mV CURRENT LIMIT CHARGE PUMP AND GATE DRIVER + + FOLDBACK REF GEN 2V + – 4V RETRY 7 UV 1 OV 2 VCC 13 GATE 4V 5 PWRGD 9 TIMER – – INTERNAL UV 9.8V + 4V – UV 0.65V LOGIC + + TIMER LOW – VP – 120µA OV + 4V + TIMER HIGH 4.65V – 3µA 8 4254 BD GND 4254f 8 LT4254 TEST CIRCUIT PWRGD OPEN –+ 3V 24V VCC +– SENSE FB GATE OV TIMER UV RETRY GND 100pF 3V +– 4254 TC Figure 1 W UW TI I G DIAGRA S 4V 4V 3.6V UV 3.65V FB tPHLUV tPLHUV tPLHFB tPHLFB 2V GATE PWRGD 2V 1V 4254 F02 1V 4254 F03 Figure 2. UV to GATE Timing Figure 3. VOUT to PWRGD Timing VCC – SENSE 50mV tPHLSENSE VCC GATE 4254 F04 Figure 4. SENSE to GATE Timing U W U U APPLICATIO S I FOR ATIO Hot Circuit Insertion When circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge. The transient currents can permanently damage the connector pins and glitch the system supply, causing other boards in the system to reset. The LT4254 is designed to turn on a board’s supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. The device also provides undervoltage and overvoltage as well as overcurrent protection while a power good output signal indicates when the output supply voltage is ready with a high output. Power-Up Sequence An external N-channel MOSFET pass transistor (Q1) is placed in the power path to control the power up of the supply voltage (Figure 5). Resistor R5 provides current detection and capacitor C1 controls the GATE slew rate. 4254f 9 LT4254 U U W U APPLICATIO S I FOR ATIO Q1 IRF530 R5 0.025Ω VIN 24V D1 CMPZ5241B 11V (SHORT PIN) 16 VCC R1 324k 1 15 SENSE GATE UV 13 LT4254 C3 0.1µF R2 40.2k R3 40.2k 2 4 10 GND C2 33nF OV OPEN TIMER FB RETRY PWRGD GND 8 10 R6 10Ω CL VOUT 24V 1.5A R8 140k R7 100Ω C1 10nF R4 27k R9 40.2k 7 5 PWRGD 4254 F05 UV = 20V OV = 40V PWRGD = 18V Figure 5. 2A, 24V Application Resistor R7 compensates the current control loop while R6 prevents high frequency oscillations in Q1. When the power pins first make contact, transistor Q1 is held off. If the voltage on the VCC pin is between the externally programmed undervoltage and overvoltage thresholds, and the voltage on the TIMER pin is less than 4.65V (typ), transistor Q1 will be turned on (Figure 6). The voltage at the GATE pin rises with a slope equal to 35µA/ C1 and the supply inrush current is set at: IINRUSH = CL • 35µA/C1 If the voltage across the current sense resistor R5 reaches VSENSETRIP, the inrush current will be limited by the internal current limit circuitry. The voltage on the GATE pin is adjusted to maintain a constant voltage across the sense resistor and the TIMER pin begins to charge. When the FB pin voltage goes above the low-to-high VFB threshold, the PWRGD pin goes high. Short-Circuit Protection The LT4254 features a programmable foldback current limit with an electronic circuit breaker that protects against short circuits or excessive load currents. The current limit is set by placing a sense resistor (R5) between VCC and SENSE. To limit excessive power dissipation in the pass transistor and to reduce voltage spikes on the input supply during short-circuit conditions at the output, the current folds IOUT 500mA/DIV PWRGD 20V/DIV VOUT 20V/DIV GATE 20V/DIV 2.5ms/DIV 4254 F06 Figure 6. Start-Up Waveforms back as a function of the output voltage, which is sensed internally on the FB pin. When the voltage at the FB pin is 0V, the current limit circuit drives the GATE pin to force a constant 12mV drop across the sense resistor. As the output at the FB pin increases, the voltage across the sense resistor increases until the FB pin reaches 2V, at which point the voltage across the sense resistor is held constant at 50mV (see Figure 7). The current limit threshold is calculated as: ILIMIT = 50mV/R5 where R5 is the sense resistor. For a 0.025Ω sense resistor, the current limit is set at 2000mA and folds back to 600mA when the output is shorted to ground. Thus, MSOFET dissipation under shortcircuit conditions is reduced from 36W to12W. See the 4254f 10 LT4254 U U W U APPLICATIO S I FOR ATIO VCC – VSENSE RESPONSE TIME (µs) 12 50mV 10 8 6 4 2 12mV 0V 2V FB 0 50 4254 F07 100 150 VCC – VSENSE (mV) 200 4254 F08 Figure 7. Current Limit Sense Voltage vs Feedback Pin Voltage Figure 8. Response Time to Overcurrent Layout Considerations section for important information about board layout to minimize current limit threshold error. The TIMER pin must never be pulled high by a low impedance because whenever the TIMER pin voltage rises above the upper threshold (typically 4.65V) the pin characteristics change from a high impedance current source to a low impedance. If the pin must be pulled high by a logic signal, then a resistor must be put in series with the TIMER pin to limit the current to approximately 100 microamperes. The resistance should be chosen as follows: The LT4254 also features a variable overcurrent response time. The time required for the part to regulate the GATE pin voltage is a function of the voltage across the sense resistor connected between the VCC pin and the SENSE pin. This helps to eliminate sensitivity to current spikes and transients that might otherwise unnecessarily trigger a current limit response and increase MOSFET dissipation. Figure 8 shows the response time as a function of the overdrive at the SENSE pin. TIMER The TIMER pin provides a method for programming the maximum time the part is allowed to operate in current limit. When the current limit circuitry is not active, the TIMER pin is pulled to GND by a 3µA current source. When the current limit circuitry becomes active, a 120µA pull-up current source is connected to the TIMER pin and the voltage will rise with a slope equal to 117µA/CTIMER as long as the circuitry stays active. Once the desired maximum current limit time is known, the capacitor value is: C(nF) = 25 • t(ms) Whenever the TIMER pin reaches 4.65V (typ), the internal fault latch is set causing the GATE to be pulled low and the TIMER pin to be discharged to GND by the 3µA current source. The part is not allowed to turn on again until the voltage at the TIMER pin falls below 0.65V (typ). RSERIES = (VLOGIC – 4.65V)/100µA Whenever the GATE pin is commanded off by any fault condition, it is discharged with a high current, turning off the external MOSFET. The waveform in Figure 9 shows how the output latches off following a short-circuit. The drop across the sense resistor is held at 12mV as the timer ramps up. Since the output did not rise bringing FB above 2V and the current is still 12mV/R5, the circuit latches off. Automatic Restart If the RETRY pin is floating, then the functionality is as described in the previous section. When the voltage at the TIMER pin ramps back down to 0.65V (typ), the LT4254 turns on again. If the short-circuit condition at the output still exists, the cycle will repeat itself indefinitely. The duty cycle under short-circuit conditions is 3% which prevents Q1 from overheating. Latch Off Operation If the RETRY pin is grounded, the LT4254 will latch off after a current fault. After the part latches off, it may be 4254f 11 LT4254 U W U U APPLICATIO S I FOR ATIO Latch Off Operation Automatic Restart Operation (Short-Ciruit Output) IOUT 500mA/DIV IOUT 500mA/DIV TIMER 5V/DIV VOUT 20V/DIV VOUT 20V/DIV TIMER 5V/DIV GATE 1V/DIV GATE 20V/DIV 2.5ms/DIV 2.5ms/DIV 4254 F09 Figure 9. Latch Off Waveforms commanded to start back up. This can be commanded by cycling the UV pin to ground and then back high (this command can only be accepted after the TIMER pin discharges below the 0.65V typ threshold, so as to prevent overheating transistor Q1). Therefore, using the RETRY pin only, the LT4254 will either latch off after an overcurrent fault condition or it will go into a hiccup mode. Undervoltage and Overvoltage Detection The LT4254 uses the UV and OV pins to monitor the VCC voltage and allow the user the greatest flexibility for setting the operational thresholds. The UV and OV pins are internally connected to an analog window comparator. Any time that the UV pin goes below 3.6V or the OV pin goes above 4V, the gate will be pulled low until the UV/OV pin voltages return to the normal operation voltage window (4V and 3.65V, respectively). Power Good Detection The LT4254 includes a comparator for monitoring the output voltage. The output voltage is sensed through the FB pin via an external resistor string. The comparator’s output (PWRGD pin) is an open collector capable of operating from a pull-up as high as 36V. The PWRGD pin can be used to directly enable/disable a power module with an active high enable input. Figure␣ 11 shows how to use the PWRGD pin to control an active low enable input power module. Signal inversion is accomplished by transistor Q2 and R10. 4254 F10 Figure 10. RETRY Waveforms Open FET Detection The LT4254 can be used to detect the presence of an open FET. When the voltage across the sense resistor is less than 3.5mV, the open collector pull-down device is shut off allowing the OPEN pin to be externally pulled high. An open FET condition is signalled when the OPEN pin is high and the PWRGD pin is low (after the part has completed its start-up cycle). This open FET condition can be falsely signalled during start-up if the load is not activated until after PWRGD goes high. To avoid this false indication, the OPEN and PWRGD pins should not be polled for a period of time, t STARTUP, given by: 3 • VCC • C1 = tSTARTUP 35µA This can be accomplished either by a microcontroller (if available) or by placing an RC filter as shown in Figure 12. Once the OPEN voltage exceeds the monitoring logic threshold, VTHRESH, and PWRGD is low, an open FET condition is signalled. In order to prevent a false indication, the RC product should be set with the following equation: RC > 3 • VCC • C1 VLOGIC 35µA ln VLOGIC – VTHRESH Another condition that can cause a false indication is if the LT4254 goes into current limit during start-up. This will cause tSTARTUP to be longer than calculated. Also, if the 4254f 12 LT4254 U U W U APPLICATIO S I FOR ATIO R5 100mΩ Q1 IRF530 VCC 16 VCC R1 324k 1 C3 0.1µF R2 40.2k 4 10 C2 33nF GND GATE 13 FB OV OPEN TIMER CL R6 10Ω VLOGIC R10 27k R7 100Ω LT4254 2 R3 40.2k 15 SENSE UV VOUT D1 CMPZ5241B 11V (SHORT PIN) RETRY PWRGD GND 8 10 7 C1 10nF R8 140k PWRGD R9 40.2k R4 27k 5 Q2 UV = 20V OV = 40V PWRGD = 18V 4254 F11 Figure 11. Active Low Enable PWRGD Application VLOGIC LT4254 R OPEN TO MONITORING LOGIC 4 INTERNAL OPEN COLLECTOR PULL-DOWN suppressor (Transorb) at the input can also prevent damage from voltage transients. GATE Pin C 4254 F12 Figure 12. Delay Circuit for OPEN FET Detection LT4254 stays in current limit long enough for the TIMER pin to fully charge up to its threshold, the LT4254 will either latch off (RETRY = 0) or go into the current limit hiccup mode (RETRY = floating). In either case, an open FET condition will be falsely signalled. If the LT4254 does go into current limit during start-up, C1 can be increased (see Power-Up Sequence). A curve of gate drive vs VCC is shown in Figure 13. The GATE pin is clamped to a maximum voltage of 12V above the VCC voltage. This clamp is designed to withstand the internal charge pump current. An external zener diode should be used if the possibility exists for an instantaneous low resistance short on VOUT to occur. At a minimum input supply voltage of 12V, the minimum gate drive voltage is 4.5V. When the input supply voltage is higher than 20V, the gate drive voltage is at least 10V and a 12 11 Supply Transient Protection ∆VGATE (V) The LT4254 is 100% tested and guaranteed to be safe from damage with supply voltages up to 44V. However, voltage transients above 44V may damage the part. During a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage transients which could exceed 44V. To minimize the voltage transients, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a 0.1µF bypass capacitor should be placed between VCC and GND. A surge 10 9 8 7 6 5 4 ∆VGATE = VGATE – VCC 10 20 30 40 VCC (V) 4254 F13 Figure 13. ∆VGATE vs VCC 4254f 13 LT4254 U U W U APPLICATIO S I FOR ATIO Q1 IRF530 R5 0.033Ω VCC 16 VCC R1 324k 1 C3 0.1µF 2 4 10 GND GATE 13 C2 33nF OV OPEN TIMER R6 10Ω R8 140k R7 100Ω LT4254 R2 40.2k R3 40.2k 15 SENSE UV VOUT CL 100µF D1 CMPZ5241B 11V (SHORT PIN) FB RETRY PWRGD GND 8 10 C1 10nF R9 40.2k 7 R4 27k 5 4254 F14 UV = 20V OV = 40V PWRGD = 18V Figure 14. Negative Output Voltage Protection Diode Application standard threshold MOSFET can be used. In applications from 12V to 15V range, a logic level MOSFET must be used. that have very large output capacitors, this could cause damage to the LT4254. Therefore, the maximum output capacitance that can be used with the LT4254 is 1000µF. In some applications it may be possible for the VOUT pin to ring below ground (due to the parasitic trace inductance). Higher current applications, especially where the output load is physically far away from the LT4254 will be more susceptible to these transients. This is normal and the LT4254 has been designed to allow for some ringing below ground. However, if the application is such that VOUT can ring more than 1V below ground, damage may occur to the LT4254 and an external diode from ground (anode) to VOUT (cathode) will have to be added to the circuit as shown in Figure 14 (it is critical that the reverse breakdown voltage of the diode be higher than the highest expected VCC voltage). A capacitor placed from ground to VOUT directly at the LT4254 pins can help reduce the amount of ringing on VOUT but it may not be enough for some applications. In applications utilizing very large external N-channel MOSFETs, the possibility exists for the MOSFET to turn on when initially inserted into a live backplane (before the LT4254 becomes active and pulls down on GATE). This is due to the drain to gate capacitance forcing current into R7 and C1 when the drain voltage steps up from ground to VCC with an extremely fast rise time. To alleviate this situation, a Schottky diode should be put across R7 with the cathode connected to C1 as shown in Figure 16. During a fault condition, the LT4254 pulls down on the GATE pin with a switch capable of sinking about 55mA. Once the GATE voltage drops below the output voltage by a diode forward voltage, the external zener will forward bias and the output will also be discharged to GND. In addition to the GATE capacitance, the output capacitance will be discharged through the LT4254. In applications Layout Considerations To achieve accurate current sensing, a Kelvin connection to the current sense resistor (R5 in typical application circuit) is recommended. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530µΩ/o. Small resistances can cause large errors in high current applications. Noise immunity will be improved significantly by locating resistor dividers close to the pins with short VCC and GND traces. A 0.1µF decoupling capacitor from UV to GND is also required. Figure 15 shows a layout that meets these requirements. 4254f 14 LT4254 U U W U APPLICATIO S I FOR ATIO VCC VCC SHORT PIN R2 R1 R5 RSENSE R3 1 UV VCC 16 2 OV SENSE 15 3 NC 4 OPEN LT4254 NC 14 GATE 13 5 PWRGD NC 12 6 NC NC 11 7 RETRY FB 10 8 GND TIMER 9 R7 C1 R6 R8 C2 VOUT Q1 D1 R4 VIA PWRGD R9 OPEN 2ND LAYER METAL GND GND 4254 F15 Figure 15. Recommended Component Placement U PACKAGE DESCRIPTIO GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ± .0015 .150 – .157** (3.810 – 3.988) .0250 TYP RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 × 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .053 – .068 (1.351 – 1.727) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.270) NOTE: 1. CONTROLLING DIMENSION: INCHES INCHES 2. DIMENSIONS ARE IN (MILLIMETERS) 3. DRAWING NOT TO SCALE .008 – .012 (0.203 – 0.305) .0250 (0.635) BSC *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE GN16 (SSOP) 0502 4254f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 15 LT4254 U TYPICAL APPLICATIO Q1 IRF530 R5 0.033Ω VCC 16 VCC R1 324k 1 C3 0.1µF R2 40.2k 4 10 C2 33nF GND GATE 13 FB OV OPEN TIMER R6 10Ω R8 140k R7 100Ω LT4254 2 R3 40.2k 15 SENSE UV VOUT CL 100µF D1 CMPZ5241B 11V (SHORT PIN) RETRY PWRGD GND 8 10 C1 10nF R9 40.2k 7 R4 27k 5 4254 F16 UV = 20V OV = 40V PWRGD = 18V Figure 16. High dV/dT MOSFET Turn-On Protection Circuit RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1641-1/LT1641-2 Positive 48V Hot Swap Controller in SO-8 9V to 80V Operation, Active Current Limit, Autoretry/Latchoff LTC4211 Single Hot Swap Controller with Multifunction Current Control 2.5V to 16.5V, Active Inrush Limiting, Dual Level Cicuit Breaker LTC4251 – 48V Hot Swap Controller in SOT-23 Floating Supply from –15V, Active Current Limiting, Fast Circuit Breaker LTC4252-1/LTC4252-2 – 48V Hot Swap Controller in MSOP Floating Supply from –15V, Active Current Limiting, Power Good Output LTC4253 Floating Supply from –15V, Active Current Limiting, Enables Three DC/DC Converters – 48V Hot Swap Controller and Supply Sequencer 4254f 16 Linear Technology Corporation LT/TP 0303 2K • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2003 This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.