AD ADG725BCP

PRELIMINARY TECHNICAL DATA
16-/32- Channel, Serially Controlled 4 Ω
1.8 V to 5.5 V, ±2.5 V, Analog Multiplexers
ADG725/ADG731
Preliminary Technical Data
=
FEATURES
3-Wire SPI Serial Interface
1.8 V to 5.5 V Single Supply
±2.5 V Dual Supply Operation
4 Ω On Resistance
0.5 Ω On Resistance Flatness
7mm x 7mm 48 lead Chip Scale Package (CSP)
or 48 lead TQFP package.
Rail to Rail Operation
Power On Reset
Fast Switching Times
Single 32 to 1 Channel Multiplexer
Dual/Differential 16 to 1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent devices with Parallel Interface
See ADG726/ADG732
FUNCTIONAL BLOCK DIAGRAMS
ADG731
S1
The ADG725/ADG731 are monolithic CMOS 32
channel/dual 16 channel analog multiplexers with a
serially controlled 3-wire interface. The ADG732 switches
one of thirty-two inputs (S1-S32) to a common output, D.
The ADG725 can be configured as a dual mux switching
one of sixteen inputs to one output or a differential mux
switching one of sixteen inputs to a differential output.
These mulitplexers utilize a 3-wire serial interface that is
compatible with SPITM, QSPITM, MICROWIRETM and
some DSP interface standards. On power-up, the internal
shift register contains all zeros and all switch are in the
OFF state.
These multiplexers are designed on an enhanced submicron process that provides low power dissipation yet gives
high switching speed, very low on resistance and leakage
currents. They operate from single supply of 1.8V to 5.5V
and ±2.5 V dual supply, making them ideally suited to a
variety of applications. On resistance is in the region of a
few Ohms and is closely matched between switches and
very flat over the full signal range. These parts can operate
equally well as either Multiplexers or De-Multiplexers
S1A
DA
S16A
D
S1B
DB
S32
S16B
INPUT SHIFT
REGISTER
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay replacement
Audio and Video Switching
Battery Powered Systems
Medical Instrumentation
Automatic Test Equipment
GENERAL DESCRIPTION
ADG725
SCLK DIN SYNC
INPUT SHIFT
REGISTER
SCLK DIN SYNC
and have an input signal range which extends to the supplies. In the OFF condition, signal levels up to the
supplies are blocked. All channels exhibit break before
make switching action preventing momentary shorting
when switching channels.
They are available in either 48 lead CSP or TQFP
package.
PRODUCT HIGHLIGHTS
1.
2.
3-Wire Serial Interface.
+1.8 V to +5.5 V Single or ±2.5 V Dual Supply
operation. These parts are specified and guaranteed
with +5 V ±10%, +3 V ±10% single supply and
±2.5 V ±10% dual supply rails.
3.
On Resistance of 4 Ω.
4.
Guaranteed Break-Before-Make Switching Action.
5.
7mm x 7mm 48 lead Chip Scale Package (CSP)
or 48 lead TQFP package.
REV. PrD May 2002
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
ADG725/ADG731–SPECIFICATIONS1(V
B Version
–40°C
+25oC
to +85°C
Parameter
ANALOG SWITCH
Analog Signal Range
On-Resistance (RON)
0 V to VDD
4
5.5
On-Resistance Match Between
Channels (∆RON)
On-Resistance Flatness (RFLAT(ON))
6
0.3
0.8
0.5
1
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG725
ADG731
Channel ON Leakage ID, IS (ON)
ADG725
ADG726
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
= 5V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)
Units
V
Ω
Ω
Ω
Ω
Ω
Ω
typ
max
typ
max
typ
max
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD , IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
VDD = 5.5 V
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 3
±2.5
±5
2.4
0.8
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
RL = 300 Ω, CL = 35 pF,Test Circuit 5;
VS1 = 3 V/0 V, VS32 = 0 V/3V
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Test Circuit 9
±0.5
±2.5
±5
5
typ
max
typ
max
max
typ
max
max
Test Conditions/Comments
nA
nA
nA
nA
nA
nA
nA
nA
0.005
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
tTRANSITION
±0.01
±0.25
±0.05
±0.5
±1
±0.05
±0.5
±1
DD
VD = VS = 1 V, or 4.5V;
Test Circuit 4
2
40
Break-Before-Make Time Delay, tD
30
Charge Injection
±5
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
-60
dB typ
Channel to Channel Crosstalk
-60
dB typ
34
18
13
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, Test Circuit 10
180
360
pF typ
pF typ
f = 1 MHz
f = 1 MHz
200
400
pF typ
pF typ
f = 1 MHz
f = 1 MHz
10
µA typ
µA max
60
1
-3 dB Bandwidth
ADG725
ADG731
C S (OFF)
C D (OFF)
ADG725
ADG731
CD, CS (ON)
ADG725
ADG731
POWER REQUIREMENTS
IDD
20
f = 1 MHz
VDD = +5.5 V
Digital Inputs = 0 V or +5.5 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. PrD
PRELIMINARY TECHNICAL DATA
1(VDD = 3V ± 10%, VSS = 0V, GND = 0 V, unless otherwise noted)
ADG725/ADG731
SPECIFICATIONS
B Version
–40°C
+25oC
to +85°C
Parameter
ANALOG SWITCH
Analog Signal Range
On-Resistance (R ON)
0 V to VDD
7
11
On-Resistance Match Between
Channels (∆RON)
On-Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source OFF Leakage I S (OFF)
Drain OFF Leakage ID (OFF)
ADG725
ADG731
Channel ON Leakage ID, IS (ON)
ADG725
ADG731
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
±0.01
±0.25
±0.05
±0.5
±1
±0.05
±0.5
±1
12
0.4
1
3
±0.5
±2.5
±5
±2.5
±5
2.0
0.8
±0.1
DYNAMIC CHARACTERISTICS
tTRANSITION
V
Ω
Ω
Ω
Ω
Ω
typ
max
typ
max
max
nA
nA
nA
nA
nA
nA
nA
nA
typ
max
typ
max
max
typ
max
max
Test Conditions/Comments
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD , IDS = 10 mA
VS = 0 V to VDD, IDS = 10 mA
VDD = 3.3 V
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = 1 V/3 V, VD = 3 V/1 V;
Test Circuit 3
VS = VD = +1 V or +3 V;
Test Circuit 4
V min
V max
0.005
C IN, Digital Input Capacitance
Units
5
µA typ
µA max
pF typ
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF Test Circuit 5
VS1 = 2 V/0 V, VS32 = 0 V/2 V
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
2
45
Break-Before-Make Time Delay, t D
30
Charge Injection
±5
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
-60
dB typ
Channel to Channel Crosstalk
-60
dB typ
34
18
13
MHz typ
MHz typ
pF typ
f = 1 MHz
180
360
pF typ
pF typ
f = 1 MHz
f = 1 MHz
200
400
pF typ
pF typ
f = 1 MHz
f = 1 MHz
10
µA typ
µA max
75
1
-3 dB Bandwidth
ADG725
ADG731
C S (OFF)
C D (OFF)
ADG725
ADG731
CD, CS (ON)
ADG725
ADG731
POWER REQUIREMENTS
IDD
20
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. PrD
–3–
RL = 50 Ω, CL = 5 pF, Test Circuit 10
VDD = +3.3 V
Digital Inputs = 0 V or +3.3 V
PRELIMINARY TECHNICAL DATA
1 Dual Supply
ADG725/ADG731–SPECIFICATIONS
(V = +2.5 V ±10%, V = -2.5 V ±10%, GND = 0 V, unless otherwise noted)
DD
SS
B Version
–40°C
+25oC
to +85°C
Parameter
ANALOG SWITCH
Analog Signal Range
On-Resistance (R ON)
VSS to VDD
4
5.5
On-Resistance Match Between
Channels (∆RON)
On-Resistance Flatness (RFLAT(ON))
6
0.3
0.8
0.5
1
LEAKAGE CURRENTS
Source OFF Leakage I S (OFF)
Drain OFF Leakage ID (OFF)
Channel ON Leakage ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
V
Ω
Ω
Ω
Ω
Ω
Ω
typ
max
typ
max
typ
max
VS = VSS to VDD, IDS = 10 mA;
Test Circuit 1
VS = VSS to VDD, IDS = 10 mA
VS = VSS to VDD, IDS = 10 mA
VDD = +2.75 V, VSS = -2.75 V
VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V;
Test Circuit 2
VS = +2.25 V/-1.25 V, VD = -1.25 V/+2.25 V;
Test Circuit 3
±2.5
±5
1.7
0.7
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
RL = 300 Ω, CL = 35 pF Test Circuit 5
VS1 = 1.5 V/0 V,VS32 = 0 V/1.5 V
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 6
VS = 0 V, RS = 0 Ω, CL = 1 nF; Test 7
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
±0.5
±2.5
±5
5
typ
max
typ
max
max
typ
max
max
Test Conditions/Comments
nA
nA
nA
nA
nA
nA
nA
nA
0.005
C IN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS
tTRANSITION
±0.01
±0.25
±0.05
±0.5
±1
±0.01
±0.5
±1
Units
VS = VD = +2.25 V/-1.25 V, Test Circuit 4
2
40
Break-Before-Make Time Delay, t D
15
Charge Injection
Off Isolation
±8
-60
ns typ
ns max
ns typ
ns min
pC typ
dB typ
Channel to Channel Crosstalk
-60
dB typ
34
18
13
MHz typ
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, Test Circuit 10
180
360
pF typ
pF typ
f = 1 MHz
f = 1 MHz
200
400
pF typ
pF typ
f = 1 MHz
f = 1 MHz
10
µA
µA
µA
µA
60
1
-3 dB Bandwidth
ADG725
ADG731
C S (OFF)
C D (OFF)
ADG725
ADG731
CD, CS (ON)
ADG725
ADG731
POWER REQUIREMENTS
IDD
20
ISS
10
20
typ
max
typ
max
VDD = +2.75 V
Digital Inputs = 0 V or +2.75 V
VSS = -2.75 V
Digital Inputs = 0 V or +2.75 V
NOTES
1
Temperature range is as follows: B Version: –40°C to +85°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TIMING CHARACTERISTICS1,2
Parameter
Limit at TMIN, TMAX
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
33
13
13
13
40
5
4.5
33
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Cycle time
SCLK High Time
SCLK Low Time
SYNC to SCLK falling edge setup time
Minimum SYNC low time
Data Setup Time
Data Hold Time
Minimum SYNC high time
min
min
min
min
min
min
min
min
NOTES
1
See Figure 1.
2
All input signals are specified with tr =tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
t1
SCLK
t8
t2
t4
t3
t5
SYNC
t6
DIN
t7
DB7
DB0
Figure 1. 3-Wire Serial Interface Timing Diagram.
EN
CSA CSB
X
A3
A2
A1
A0
EN
CS
X
A4
A3
A2
A1
A0
DATA BITS
DATA BITS
Figure 2. ADG725 Input Shift Register Contents
REV. PrD
DB0 (LSB)
DB7 (MSB)
DB0 (LSB)
DB7 (MSB)
Figure 3. ADG731 Input Shift Register Contents
–5–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
ABSOLUTE MAXIMUM RATINGS 1
(TA = +25°C unless otherwise noted)
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs2
+7 V
–0.3 V to +7 V
+0.3 V to -7 V
VSS - 0.3 V to VDD +0.3 Vor
30 mA, Whichever Occurs First
Digital Inputs 2
-0.3V to VDD +0.3 V or
30 mA, Whichever Occurs First
Peak Current, S or D
60mA
(Pulsed at 1 ms, 10% Duty Cycle max)
Continuous Current, S or D
30mA
Operating Temperature Range
Industrial (B Version)
–40°C to +85°C
Storage Temperature Range
–65°C to +150°C
Junction Temperature
+150°C
TBD°C/W
48 lead CSP θJA Thermal Impedance
48 lead TQFP θJA Thermal Impedance
TBD°C/W
Lead Temperature, Soldering (10seconds)
300°C
IR Reflow, Peak Temperature
+220°C
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Only one absolute maximum rating may
be applied at any one time.
2
Overvoltages at SCLK, SYNC, DIN, RS, S or D will be clamped by internal diodes.
Current should be limited to the maximum ratings given.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG725/ADG731 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model
Temperature Range
ADG725BCP
ADG725BSU
ADG731BCP
ADG731BSU
-40
-40
-40
-40
o
C
C
o
C
o
C
o
to
to
to
to
+85
+85
+85
+85
o
C
C
o
C
o
C
o
Package Description
Package Option
Chip
Thin
Chip
Thin
CP-48
SU-48
CP-48
SU-48
Scale
Quad
Scale
Quad
Package (CSP)
Flatpack
Package (CSP)
Flatpack
–6–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
PIN FUNCTION DESCRIPTION
ADG725
ADG731
Mnemonic Function
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of
the serial clock input. These devices can accomodate serial input rates of up to
30MHz.
Active low control input that clears the input register and turns all switches to the
OFF condition.
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of
the serial clock input.
Source. May be an input or output.
Drain. May be an input or output.
Power Supply Input. These parts can be operated from a supply of +1.8V to +5.5V
and dual supply of +/-2.5V.
Ground reference.
Active Low Control Input. This is the frame synchronization signal for the input
data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input
shift register is enabled. An 8-bit counter is also enabled. Data is transferred on the
falling edges of the following clocks. After 8 falling clock edges, switch conditions
are automaticaly updated. SYNC may be used to frame the signal, or just pulled low
for a short period of time to enable the counter and input buffers.
RS
DIN
SXX
DX
VDD
GND
SYNC
S13B
S14B
S15B
S16A
DB
NC
DA
NC
S16A
S15A
48 47 46 45 44 43 42 41 40 39 38 37
48 47 46 45 44 43 42 41 40 39 38 37
36 S28
S12A 1
35 S27
S11A 2
S10 3
34 S26
S10A 3
S9 4
33 S25
S9A 4
S8 5
32 S24
S8A 5
31 S23
S7A 6
ADG725
30 S22
S6A 7
29 S21
S5A 8
TOP VIEW
(Not to Scale)
S4 9
28 S20
S4A 9
S3 10
27 S19
S3A 10
27 S3B
S2 11
26 S18
S2A 11
26 S2B
S1 12
25 S17
S1A 12
–7–
31 S7B
30 S6B
28 S4B
25 S1B
VSS
GND
NC
NC
13 14 15 16 17 18 19 20 21 22 23 24
NC
NC = NO CONNECT
VSS
GND
NC
SCLK
DIN
SYNC
NC
NC
13 14 15 16 17 18 19 20 21 22 23 24
VDD
VDD
NC = NO CONNECT
32 S8B
29 S5B
SCLK
S5 8
DIN
TOP VIEW
(Not to Scale)
SYNC
S6 7
33 S9B
NC
ADG731
35 S11B
34 S10B
NC
S7 6
36 S12B
PIN 1
IDENTIFIER
VDD
VDD
PIN 1
IDENTIFIER
NC
S11 2
NC
S12 1
REV. PrD
S14A
S13A
S29
S30
S31
S32
NC
D
NC
NC
S16
S15
S14
S13
PIN CONFIGURATIONS
CSP & TQFP
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
Table 1. ADG725 Truth Table
A3
A2
A1
A0
EN
CSA CSB
Switch Condition
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Retains previous switch condition
All Switches OFF
S1A - DA, S1B - DB
S2A - DA, S2B - DB
S3A - DA, S3B - DB
S4A - DA, S4B - DB
S5A - DA, S5B - DB
S6A - DA, S6B - DB
S7A - DA, S7B - DB
S8A - DA, S8B - DB
S9A - DA, S9B - DB
S10A - DA, S10B - DB
S11A - DA, S11B - DB
S12A - DA, S12B - DB
S13A - DA, S13B - DB
S14A - DA, S14B - DB
S15A - DA, S15B - DB
S16A - DA, S16B - DB
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 2. ADG731 Truth Table
A4
A3
A2
A1
A0
E N C S Switch Condition
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Retains previous switch condition
All Switches OFF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
X = Don’t Care
–8–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TERMINOLOGY
VDD
VSS
IDD
ISS
GND
S
D
IN
VD (VS)
RON
∆R ON
RFLAT(ON)
I S (OFF)
I D (OFF)
ID, IS (ON)
VINL
VINH
IINL(IINH)
C S (OFF)
C D (OFF)
C D ,C S (ON)
CIN
tTRANSITION
tOPEN
Most positive power supply potential.
Most Negative power supply in a dual supply application. In single supply applications, connect to GND.
Positive supply current.
Negative supply current.
Ground (0 V) reference.
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input.
Analog voltage on terminals D, S
Ohmic resistance between D and S.
On resistance match between any two channels, i.e. RONmax - RONmin
Flatness is defined as the difference between the maximum and minimum value of on-resistance as mea
sured over the specified analog signal range.
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
Channel leakage current with the switch “ON.”
Maximum input voltage for logic “0”.
Minimum input voltage for logic “1”.
Input current of the digital input.
“OFF” switch source capacitance. Measured with reference to ground.
“OFF” switch drain capacitance. Measured with reference to ground.
“ON” switch capacitance. Measured with reference to ground.
Digital input capacitance.
Delay time measured between the 50% and 90% points of the SYNC and the switch “ON” condi
tion when switching from one address state to another.
“OFF” time measured between the 80% points of both switches when switching from one address state to
another.
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
Charge
Injection
Off Isolation A measure of unwanted signal coupling through an “OFF” switch.
Crosstalk
A measure of unwanted signal is coupled through from one channel to another as a result of parasitic
capacitance.
On Response The Frequency response of the “ON” switch.
Insertion
Loss
The loss due to the ON resistance of the switch.
REV. PrD
–9–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TYPICAL PERFORMANCE CHARACTERISTICS
TBD
TBD
TBD
TPC 1. On Resistance vs. VD(VS) for for
Single Supply
TPC 4. On Resistance vs. VD(VS) for
Different Temperatures, Single
Supply
TPC 7. Leakage Currents vs. VD(VS)
TBD
TBD
TBD
TPC 2. On Resistance vs. VD(VS) for
Dual Supply
TPC 5. On Resistance vs. VD(VS) for
Different Temperatures, Dual Supply
TPC 8. Leakage Currents vs. VD(VS)
TBD
TBD
TPC 6. Leakage Currents vs. VD(VS)
TPC 9. Leakage Currents vs.
Temperature
TBD
TPC 3. On Resistance vs. VD(VS) for
Different Temperatures, Single
Supply
–10–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TBD
TBD
TBD
TPC 10. Leakage Currents vs.
Temperature
TPC 13. TON/TOFF Times vs.
Temperature
TPC 16. On Response vs. Frequency
TBD
TBD
TPC 11. Supply Currents vs. Input
Switching Frequency
TPC 14. Off Isolation vs. Frequency
TBD
TBD
TPC 12. Charge Injection vs. Source
Voltage
TPC 15. Crosstalk vs. Frequency
REV. PrD
–11–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
GENERAL DESCRIPTION
The ADG725 and ADG731 are serially controlled, 32
channel and dual/differential 16 channel multiplexers respectively.
POWER ON RESET
On power up of the device, all switches will be in the
OFF condition and the internal shift register is filled with
zeros and will remain so until a valid write takes place.
SERIAL INTERFACE
The ADG725 and ADG731 have a three wire serial interface (SYNC, SCLK, and DIN), which is compatible with
SPI, QSPI, MICROWIRE interface standards and most
DSP’s. Figure 1 shows the timing diagram of a typical
write sequence.
Data is written to the 8-bit shift register via DIN under
the control of the SYNC and SCLK signals.
When SYNC goes low, the input shift register is enabled.
An 8-bit counter is also enabled. Data from DIN is
clocked into the shift register on the falling edge of
SCLK. Figures 2 & 3 show the contents of the input shift
registers for these devices. When the part has received
eight clock cycles after SYNC has been pulled low, the
switches are automatically updated with the new
configuration and the input shift register is disabled. With
SYNC held high, any further data or noise on the DIN
line will have no effect on the shift register.
The ADG725 CSA and CSB data bits allow the user the
flexibility to change the configuration of either or both
banks of the multiplexer.
–12–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
Test Circuits
I DS
VDD
VSS
V
DD
V
SS
V1
S1
D
S2
D
S
ID (OFF)
A
S32
VD
VS
GND
VS
R O N = V 1/IDS
Test Circuit 3. ID (OFF)
Test Circuit 1. On Resistance.
IS (OFF)
VDD
VSS
V
DD
V
SS
S1
VSS
V
DD
V
SS
D
S1
D
S2
VS
VDD
A
S32
VD
S32
VS
GND
GND
VD
Test Circuit 4. ID (ON)
Test Circuit 2. IS (OFF).
VDD
VSS
V
DD
V
SS
S1
SYNC
50%
50%
VS1
0V
S2 THRU S31
ADG731*
VS32
S32
VS1
D
90%
VOUT
CL
35pF
RL
300 Ω
GND
V OUT
90%
VS32
tTRANSITION
* SIMILAR CONNECTION FOR ADG725
tTRANSITION
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION.
V DD
VSS
VDD
VSS
S1
SYNC
VS
0V
S2 THRU S31
ADG731*
S32
VS
D
GND
VOUT
RL
300Ω
CL
35pF
VOUT
80%
80%
t OPEN
*SIMILAR CONNECTION FOR ADG725
Test Circuit 6. Break Before Make Delay, tOPEN.
REV. PrD
ID (ON)
–13–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
VDD
VSS
V
VSS
DD
SYNC
ADG731*
RS
D
S
VOUT
CL
1nF
VS
V OUT
GND
∆ VOUT
QINJ = CL x ∆ VOUT
*SIMILAR CONNECTION FOR ADG725
Test Circuit 7. Charge Injection.
VDD
VSS
0.1µ F
0.1µ F
VDD VSS
NETWORK
ANALYZER
VSS
VDD
S
VDD VSS S1
50 Ω
50 Ω
S2
VS
NETWORK
ANALYZER
50 Ω
ADG731* S32
D
RL
50 Ω
ADG731*
GND
VS
VOUT
D
GND
OFF ISOLATION = 20 LOG
RL
50 Ω
VOUT
VOUT
VS
*SIMILAR CONNECTION FOR ADG725
*SIMILAR CONNECTION FOR ADG725
CHANNEL TO CHANNEL CROSSTALK=
20LOG 10(VOUT /VS)
Test Circuit 8. OFF Isolation
VDD
50Ω
Test Circuit 9. Channel-to-Channel Crosstalk.
VSS
0.1µ F
0.1µ F
NETWORK
ANALYZER
VSS
VDD
S
50 Ω
VS
D
RL
50 Ω
ADG731*
GND
INSERTION LOSS = 20 LOG
VOUT
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
*SIMILAR CONNECTION FOR ADG725
Test Circuit 10. Bandwidth
–14–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead CSP
(CP-48)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
0.024 (0.60)
0.017 (0.42)
37
0.009 (0.24)
0.276(7.0)
BSC SQ
PIN 1
INDICATOR
0.010 (0.25)
MIN
48
1
36
0.266 (6.75)
BSC SQ
TOP
VIEW
25
24
0.020 (0.50)
0.016 (0.40)
0.012 (0.30)
o
12
13
0.217 (5.5)
REF
0.028 (0.70) MAX
0.026 (0.65) NOM
0.002 (0.05)
0.0004 (0.01)
0.012 (0.30) 0.020 (0.50) 0.008(0.20) 0.0 (0.0)
BSC
0.009 (0.23)
REF
0.007 (0.18)
12 MAX
0.035 (0.90) MAX
0.033 (0.85) NOM
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
48-Lead TQFP
(SU-48)
0.047 (1.20) MAX
0.276 (7.0) BSC
0.018 (0.45)
37
48
36
1
0.276 (7.0) BSC
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.006 (0.15)
0.002 (0.05)
0° – 7°
12
0° MIN
0.008 (0.20)
0.004 (0.09)
REV. PrD
13
0.019 (0.5)
BSC
–15–
25
24
0.011 (0.27)
0.006 (0.17)
0.354 (9.00) BSC
0.030 (0.75)
0.354 (9.00) BSC
0.041 (1.05)
0.037 (0.95)
0.207 (5.25)
0.201 (5.10) SQ
0.195 (4.95)
BOTTOM
VIEW