MOTOROLA MC14490DW

SEMICONDUCTOR TECHNICAL DATA
L SUFFIX
CERAMIC
CASE 620
The MC14490 is constructed with complementary MOS enhancement
mode devices, and is used for the elimination of extraneous level changes
that result when interfacing with mechanical contacts. The digital contact
bounce eliminator circuit takes an input signal from a bouncing contact and
generates a clean digital signal four clock periods after the input has
stabilized. The bounce eliminator circuit will remove bounce on both the
“make” and the “break” of a contact closure. The clock for operation of the
MC14490 is derived from an internal R–C oscillator which requires only an
external capacitor to adjust for the desired operating frequency (bounce
delay). The clock may also be driven from an external clock source or the
oscillator of another MC14490 (see Figure 5).
NOTE: Immediately after power–up, the outputs of the MC14490 are in
indeterminate states.
•
•
•
•
•
•
•
•
•
•
•
•
P SUFFIX
PLASTIC
CASE 648
DW SUFFIX
SOIC
CASE 751G
Diode Protection on All Inputs
Six Debouncers Per Package
Internal Pullups on All Data Inputs
Can Be Used as a Digital Integrator, System Synchronizer, or Delay
Line
Internal Oscillator (R–C), or External Clock Source
TTL Compatible Data Inputs/Outputs
Single Line Input, Debounces Both “Make” and “Break” Contacts
Does Not Require “Form C” (Single Pole Double Throw) Input Signal
Cascadable for Longer Time Delays
Schmitt Trigger on Clock Input (Pin 7)
Supply Voltage Range = 3.0 V to 18 V
Chip Complexity: 546 FETs or 136.5 Equivalent Gates
ORDERING INFORMATION
MC14490P
MC14490L
MC14490DW
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
+VDD
DATA
4–BIT STATIC SHIFT REGISTER
Ain 1
SHIFT
OSCin 7
OSCout 9
OSCILLATOR
AND
TWO–PHASE
CLOCK GENERATOR
Bin 14
Cin 3
Din 12
Ein 5
Fin 10
φ1
LOAD
φ1 φ2
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
φ1
φ2
VDD = PIN 16
VSS = PIN 8
φ1 φ2
2 Bout
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
13 Cout
IDENTICAL TO ABOVE STAGE
4 Dout
IDENTICAL TO ABOVE STAGE
IDENTICAL TO ABOVE STAGE
15 Aout
1/2–BIT
DELAY
11 Eout
6 Fout
REV 3
1/94
MOTOROLA
Motorola, Inc. 1995
CMOS LOGIC DATA
MC14490
297
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol
Parameter
VDD
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Value
Unit
PIN ASSIGNMENT
– 0.5 to + 18.0
V
Ain
1
16
VDD
– 0.5 to VDD + 0.5
V
Bout
2
15
Aout
Iin
Input Current (DC or Transient), per Pin
± 10
mA
Cin
3
14
Bin
PD
Power Dissipation, per Package†
500
mW
4
13
Cout
Tstg
Storage Temperature
– 65 to + 150
_C
Dout
Ein
5
12
Din
Fout
6
11
Eout
OSCin
7
10
Fin
VSS
8
9
TL
Lead Temperature (8–Second Soldering)
260
_C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 MW/_C From 65_C To 125_C
Ceramic “L” Packages: – 12 mW/_C From 100_C to 125_C
OSCout
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
25_C
125_C
Min
Max
Min
Typ #
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vin = 0 or VDD
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
(VO = 0.5 or 4.5 Vdc) “1 Level”
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH
Output Drive Current
Oscillator Output
(VOH = 2.5 V)
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
– 55_C
VDD
Vdc
Vdc
IOH
Vdc
mAdc
Source
Debounce Outputs
(VOH = 2.5 V)
(VOH = 4.6 V)
(VOH = 9.5 V)
(VOH = 13.5 V)
Oscillator Output
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
Sink
5.0
5.0
10
15
– 0.6
– 0.12
– 0.23
– 1.4
—
—
—
—
– 0.5
– 0.1
– 0.2
– 1.2
– 1.5
– 0.3
– 0.8
– 3.0
—
—
—
—
– 0.4
– 0.08
– 0.16
– 1.0
—
—
—
—
5.0
5.0
10
15
– 0.9
– 0.19
– 0.6
1.8
—
—
—
—
– 0.75
– 0.16
– 0.5
– 1.5
– 2.2
– 0.46
– 1.2
– 4.5
—
—
—
—
– 0.6
– 0.12
– 0.4
– 1.2
—
—
—
—
5.0
10
15
0.36
0.9
4.2
—
—
—
0.3
0.75
3.5
0.9
2.3
10
—
—
—
0.24
0.6
2.8
—
—
—
5.0
10
15
2.6
4.0
12
—
—
—
2.2
3.3
10
4.0
9.0
35
—
—
—
1.8
2.7
8.1
—
—
—
IOL
Debounce Outputs
(VOL = 0.4 V)
(VOL = 0.5 V)
(VOL = 1.5 V)
mAdc
Input Current
Debounce Inputs (Vin = VDD)
IIH
15
—
2.0
—
0.2
2.0
—
11
µAdc
Input Current Oscillator — Pin 7
(Vin = VSS or VDD)
Iin
15
—
± 620
—
± 255
± 400
—
± 250
µAdc
Pullup Resistor Source Current
Debounce Inputs
(Vin = VSS)
IIL
5.0
10
15
175
340
505
375
740
1100
140
280
415
190
380
570
255
500
750
70
145
215
225
440
660
µAdc
Input Capacitance
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Vin = VSS or VDD, Iout = 0 µA)
ISS
5.0
10
15
—
—
—
150
280
840
—
—
—
40
90
225
100
225
650
—
—
—
90
180
550
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
MC14490
298
MOTOROLA CMOS LOGIC DATA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (CL = 50 pF, TA = 25_C)
VDD
Vdc
Min
Typ #
Max
Unit
5.0
10
15
—
—
—
180
90
65
360
180
130
ns
5.0
10
15
—
—
—
100
50
40
200
100
80
ns
5.0
10
15
—
—
—
60
30
20
120
60
40
5.0
10
15
—
—
—
285
120
95
570
240
190
tPLH
5.0
10
15
—
—
—
370
160
120
740
320
240
Clock Frequency (50% Duly Cycle)
(External Clock)
fcl
5.0
10
15
—
—
—
2.8
6
9
1.4
3.0
4.5
MHz
Setup Time (See Figure 1)
tsu
5.0
10
15
100
80
60
50
40
30
—
—
—
ns
Maximum External Clock Input
Rise and Fall Time
Oscillator Input
tr, tf
5.0
10
15
Characteristic
Symbol
Output Rise Time
All Outputs
tTLH
Output Fall Time
Oscillator Output
tTHL
tTHL
Debounce Outputs
Propagation Delay Time
Oscillator Input to Debounce Outputs
ns
tPHL
Oscillator Frequency
OSCout
Cext ≥ 100 pF*
ns
No Limit
fosc, typ
Note: These equations are intended to be a design guide.
Laboratory experimentation may be required. Formulas
are typically ± 15% of actual frequencies.
Hz
1.5
Cext (in µF)
4.5
Cext (in µF)
5.0
10
6.5
Cext (in µF)
15
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
*POWER–DOWN CONSIDERATIONS
Large values of Cext may cause problems when powering down the MC14490 because of the amount of energy stored in the
capacitor. When a system containing this device is powered down, the capacitor may discharge through the input protection
diodes at Pin 7 or the parasitic diodes at Pin 9. Current through these internal diodes must be limited to 10 mA, therefore the
turn–off time of the power supply must not be faster than t = (VDD – VSS) Cext / (10 mA). For example, If VDD – VSS = 15 V and
Cext = 1 µF, the power supply must turn off no faster than t = (15 V) (1 µF) / 10 mA = 1.5 ms. This is usually not a problem
because power supplies are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of the power supply to zero volts occurs, the MC14490 may sustain damage. To avoid this possibility, use external clamping diodes, D1 and D2, connected as shown in Figure 2.
0V
tPLH
Aout
VDD
50%
OSCin
50%
90%
10%
D1
tr
Aout
tPHL
90%
10%
OSCin
50%
Ain
50%
9
OSCout
VDD
0V
tsu
D2
VDD
7
50%
tf
OSCin
Cext
VDD
MC14490
VDD
0V
Figure 1. Switching Waveforms
MOTOROLA CMOS LOGIC DATA
Figure 2. Discharge Protection During Power Down
MC14490
299
THEORY OF OPERATION
After some time period of N clock periods, the contact is
opened and at N + 1 a low is loaded into the first bit. Just after
N + 1, when the input bounces low, all bits are set to a high. At
N + 2 nothing happens because the input and output are low
and all bits of the shift register are high. At time N + 3 and
thereafter the input signal is a high, clean signal. At the positive edge of N + 6 the output goes high as a result of four lows
being shifted into the shift register.
Assuming the input signal is long enough to be clocked
through the Bounce Eliminator, the output signal will be no
longer or shorter than the clean input signal plus or minus
one clock period.
The amount of time distortion between the input and output
signals is a function of the difference in bounce characteristics on the edges of the input signal and the clock frequency.
Since most relay contacts have more bounce when making
as compared to breaking, the overall delay, counting bounce
period, will be greater on the leading edge of the input signal
than on the trailing edge. Thus, the output signal will be
shorter than the input signal — if the leading edge bounce is
included in the overall timing calculation.
The only requirement on the clock frequency in order to
obtain a bounce free output signal is that four clock periods
do not occur while the input signal is in a false state. Referring to Figure 3, a false state is seen to occur three times at
the beginning of the input signal. The input signal goes low
three times before it finally settles down to a valid low state.
The first three low pulses are referred to as false states.
If the user has an available clock signal of the proper frequency, it may be used by connecting it to the oscillator input
(pin 7). However, if an external clock is not available the user
can place a small capacitor across the oscillator input and
output pins in order to start up an internal clock source (as
shown in Figure 4). The clock signal at the oscillator output
pin may then be used to clock other MC14490 Bounce Eliminator packages. With the use of the MC14490, a large number of signals can be cleaned up, with the requirement of
only one small capacitor external to the Hex Bounce Eliminator packages.
The MC14490 Hex Contact Bounce Eliminator is basically
a digital integrator. The circuit can integrate both up and
down. This enables the circuit to eliminate bounce on both
the leading and trailing edges of the signal, shown in the timing diagram of Figure 3.
Each of the six Bounce Eliminators is composed of a
4–1/2–bit register (the integrator) and logic to compare the
input with the contents of the shift register, as shown in Figure 4. The shift register requires a series of timing pulses in
order to shift the input signal into each shift register location.
These timing pulses (the clock signal) are represented in the
upper waveform of Figure 3. Each of the six Bounce Eliminator circuits has an internal resistor as shown in Figure 4. A
pullup resistor was incorporated rather than a pulldown resistor in order to implement switched ground input signals, such
as those coming from relay contacts and push buttons. By
switching ground, rather than a power supply lead, system
faults (such as shorts to ground on the signal input leads) will
not cause excessive currents in the wiring and contacts. Signal lead shorts to ground are much more probable than
shorts to a power supply lead.
When the relay contact is closed, (see Figure 4) the low
level is inverted, and the shift register is loaded with a high on
each positive edge of the clock signal. To understand the operation, we assume all bits of the shift register are loaded
with lows and the output is at a high level.
At clock edge 1 (Figure 3) the input has gone low and a
high has been loaded into the first bit or storage location of
the shift register. Just after the positive edge of clock 1, the
input signal has bounced back to a high. This causes the
shift register to be reset to lows in all four bits — thus starting
the timing sequence over again.
During clock edges 3 to 6 the input signal has stayed low.
Thus, a high has been shifted into all four shift register bits
and, as shown, the output goes low during the positive edge
of clock pulse 6.
It should be noted that there is a 3–1/2 to 4–1/2 clock period delay between the clean input signal and output signal. In
this example there is a delay of 3.8 clock periods from the
beginning of the clean input signal.
1
2
3
4
5
6
N+1
N+3
N+5
N+7
OSCin OR OSCout
INPUT
OUTPUT
CONTACT
OPEN
CONTACT
BOUNCING
CONTACT CLOSED
(VALID TRUE SIGNAL)
CONTACT OPEN
CONTACT
BOUNCING
Figure 3. Timing Diagram
MC14490
300
MOTOROLA CMOS LOGIC DATA
+VDD
PULLUP RESISTOR
(INTERNAL)
Ain
1
“FORM A”
CONTACT
OSCin 7
Cext
OSCout
9
DATA
4–BIT STATIC SHIFT REGISTER
SHIFT
OSCILLATOR
AND
TWO–PHASE
CLOCK GENERATOR
15
1/2 BIT
DELAY
Aout
LOAD
φ1 φ2
φ1
φ1 φ2
φ2
Figure 4. Typical “Form A” Contact Debounce Circuit
(Only One Debouncer Shown)
OPERATING CHARACTERISTICS
The single most important characteristic of the MC14490
is that it works with a single signal lead as an input, making
it directly compatible with mechanical contacts (Form A
and B).
The circuit has a built–in pullup resistor on each input. The
worst case value of the pullup resistor (determined from the
Electrical Characteristics table) is used to calculate the contact wetting current. If more contact current is required, an
external resistor may be connected between VDD and the
input.
Because of the built–in pullup resistors, the inputs cannot
be driven with a single standard CMOS gate when VDD is below 5 V. At this voltage, the input should be driven with paral-
leled standard gates or by the MC14049 or MC14050
buffers.
The clock input circuit (pin 7) has Schmitt trigger shaping
such that proper clocking will occur even with very slow clock
edges, eliminating any need for clock preshaping. In addition, other MC14490 oscillator inputs can be driven from a
single oscillator output buffered by an MC14050 (see Figure 5). Up to six MC14490s may be driven by a single buffer.
The MC14490 is TTL compatible on both the inputs and
the outputs. When VDD is at 4.5 V, the buffered outputs can
sink 1.6 mA at 0.4 V. The inputs can be driven with TTL as a
result of the internal input pullup resistors.
OSCin 7
Cext
OSCin
FROM CONTACTS
7
9
MC14490
NO CONNECTION
9 OSCout
1/6 MC14050
FROM
CONTACTS
OSCout
TO SYSTEM
LOGIC
MC14490
NO CONNECTION
9 OSCout
OSCin 7
FROM CONTACTS
TO SYSTEM
LOGIC
MC14490
TO SYSTEM
LOGIC
Figure 5. Typical Single Oscillator Debounce System
MOTOROLA CMOS LOGIC DATA
MC14490
301
TYPICAL APPLICATIONS
ASYMMETRICAL TIMING
MULTIPLE TIMING SIGNALS
In applications where different leading and trailing edge
delays are required (such as a fast attack/slow release
timer.) Clocks of different frequencies can be gated into the
MC14490 as shown in Figure 6. In order to produce a slow
attack/fast release circuit leads A and B should be interchanged. The clock out lead can then be used to feed clock
signals to the other MC14490 packages where the asymmetrical input/output timing is required.
As shown in Figure 8, the Bounce Eliminator circuits can
be connected in series. In this configuration each output is
delayed by four clock periods relative to its respective input.
This configuration may be used to generate multiple timing
signals such as a delay line, for programming other timing
operations.
One application of the above is shown in Figure 9, where it
is required to have a single pulse output for a single operation (make) of the push button or relay contact. This only
requires the series connection of two Bounce Eliminator circuits, one inverter, and one NOR gate in order to generate
the signal AB as shown in Figures 9 and 10. The signal AB is
four clock periods in length. If the inverter is switched to the A
output, the pulse AB will be generated upon release or break
of the contact. With the use of a few additional parts many
different pulses and waveshapes may be generated.
IN
OSCin
OUT
MC14490
OSCout
MC14011B
15
1
A
EXTERNAL
CLOCK
B.E. 1
B
fC
÷N
Ain
fC/N
14
Figure 6. Fast Attack/Slow Release Circuit
B.E. 2
2
Bin
13
3
LATCHED OUTPUT
B.E. 3
The contents of the Bounce Eliminator can be latched by
using several extra gates as shown in Figure 7. If the latch
lead is high the clock will be stopped when the output goes
low. This will hold the output low even though the input has
returned to the high state. Any time the clock is stopped the
outputs will be representative of the input signal four clock
periods earlier.
IN
Aout
Cout
Cin
12
B.E. 4
4
Dout
Din
5
B.E. 5
11
Eout
Ein
OUT
10
MC14490
OSCin
Bout
OSCout
B.E. 6
6
Fout
Fin
MC14011B
CLOCK
OSCin
7
CLOCK
9
OSCout
LATCH = 1
UNLATCH = 0
Figure 8. Multiple Timing Circuit Connections
Figure 7. Latched Output Circuit
MC14490
302
MOTOROLA CMOS LOGIC DATA
IN
BE 1
OUT
A
A
IN
OUT
BE 2
B
AB
B
A ≡ ACTIVE LOW
B ≡ ACTIVE LOW
Figure 9. Single Pulse Output Circuit
OSCin OR
OSCout
INPUT
A
B
C
D
E
F
AB
AB
Figure 10. Multiple Output Signal Timing Diagram
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATA
MC14490
303
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–B–
C
L
DIM
A
B
C
D
E
F
G
H
K
L
M
N
–T–
K
N
SEATING
PLANE
M
E
F
J
G
D
16 PL
0.25 (0.010)
16 PL
0.25 (0.010)
M
T A
T B
M
S
INCHES
MIN
MAX
0.750
0.785
0.240
0.295
–––
0.200
0.015
0.020
0.050 BSC
0.055
0.065
0.100 BSC
0.008
0.015
0.125
0.170
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
19.05
19.93
6.10
7.49
–––
5.08
0.39
0.50
1.27 BSC
1.40
1.65
2.54 BSC
0.21
0.38
3.18
4.31
7.62 BSC
0_
15 _
0.51
1.01
S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
16
9
1
8
B
F
C
L
S
–T–
K
H
G
D
J
16 PL
0.25 (0.010)
MC14490
304
SEATING
PLANE
M
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MOTOROLA CMOS LOGIC DATA
OUTLINE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751G–02
ISSUE A
–A–
16
9
–B–
8X
P
0.010 (0.25)
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
M
B
M
8
16X
J
D
0.010 (0.25)
M
T A
B
S
S
F
R X 45 _
C
–T–
14X
G
K
SEATING
PLANE
M
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15
10.45
7.40
7.60
2.35
2.65
0.35
0.49
0.50
0.90
1.27 BSC
0.25
0.32
0.10
0.25
0_
7_
10.05
10.55
0.25
0.75
INCHES
MIN
MAX
0.400
0.411
0.292
0.299
0.093
0.104
0.014
0.019
0.020
0.035
0.050 BSC
0.010
0.012
0.004
0.009
0_
7_
0.395
0.415
0.010
0.029
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided
in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
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MOTOROLA CMOS LOGIC DATA
◊
*MC14490/D*
MC14490
MC14490/D
305