MOTOROLA 145406

MOTOROLA
Order this document
by MC145406/D
SEMICONDUCTOR TECHNICAL DATA
MC145406
Driver/Receiver
EIA 232–E and CCITT V.28 (Formerly RS–232–D)
P SUFFIX
PLASTIC
CASE 648
The MC145406 is a silicon–gate CMOS IC that combines three drivers
and three receivers to fulfill the electrical specifications of standards
E I A 2 3 2 – E a n d C C I T T V. 2 8 . T h e d r i v e r s f e a t u r e t r u e T T L i n p u t
compatibility, slew–rate–limited output, 300–Ω power–off source impedance, and output typically switching to within 25% of the supply rails. The
receivers can handle up to ± 25 V while presenting 3 to 7 kΩ impedance.
Hysteresis in the receivers aids reception of noisy signals. By combining
both drivers and receivers in a single CMOS chip, the MC145406 provides
efficient, low–power solutions for EIA 232–E and V.28 applications.
16
1
DW SUFFIX
SOG
CASE 751G
16
Drivers
• ± 5 V to ±12 V Supply Range
• 300–Ω Power–Off Source Impedance
• Output Current Limiting
• TTL Compatible
• Maximum Slew Rate = 30 V/µs
1
SD SUFFIX
SSOP
CASE 940B
Receivers
• ± 25 V Input Voltage Range When VDD = 12 V, VSS = – 12 V
• 3 to 7 kΩ Input Impedance
• Hysteresis on Input Switchpoint
PIN ASSIGNMENT
BLOCK DIAGRAM
*
Rx
VDD
RECEIVER
VDD
VDD
Rx1
VCC
15 kΩ
VCC
Tx1
+
DO
–
5.4 k
Rx2
VSS
1.0 V
Tx2
1.8 V
Rx3
HYSTERESIS
VDD
Tx3
LEVEL
SHIFT
Tx
2
16
3
4
D
7
14
13
R
5
6
15
R
D
12
11
R
D
10
VCC
DO1
DI1
DO2
DI2
DO3
DI3
DRIVER
VSS
VCC
300 Ω
1
+
–
8
9
GND
D = DRIVER
R = RECEIVER
DI
1.4 V
VSS
*Protection circuit
 Motorola, Inc. 1995
MOTOROLA
REV 4
1/95
MC145406
1
MAXIMUM RATINGS (Voltage polarities referenced to GND)
Rating
Symbol
Value
Unit
DC Supply Voltages (VDD ≥ VCC)
VDD
VSS
VCC
– 0.5 to + 13.5
+ 0.5 to – 13.5
– 0.5 to + 6.0
V
Input Voltage Range
Rx1–3 Inputs
DI1–3 Inputs
VIR
V
(VSS – 15) to (VDD + 15)
– 0.5 to (VCC + 0.5)
DC Current Per Pin
± 100
mA
Power Dissipation
PD
1.0
W
Operating Temperature Range
TA
– 40 to + 85
°C
Tstg
– 85 to + 150
°C
Storage Temperature Rate
This device contains protection circuitry to protect the inputs against damage due to high static
voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum rated
voltages to this high impedance circuit. For proper
operation, it is recommended that the voltages at
the DI and DO pins be constrained to the range
GND ≤VDI ≤ VCC and GND≤ VDO ≤ VCC. Also, the
voltage at the Rx pin should be constrained to
(VSS – 15 V) ≤ VRx1–3 ≤ (VDD + 15 V), and Tx
should be constrained to VSS ≤ VTx1–3 ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., GND or VCC for
DI and Ground for Rx.)
DC ELECTRICAL CHARACTERISTICS (All polarities referenced to GND = 0 V, TA = – 40 to + 85°C)
Symbol
Min
Typ
Max
DC Supply Voltage
VDD
VSS
VCC (VDD ≥ VCC)
VDD
VSS
VCC
4.5
– 4.5
4.5
5 to 12
– 5 to – 12
5.0
13.2
– 13.2
5.5
Quiescent Supply Current (Outputs unloaded, inputs low)
VDD = + 12 V
VSS = – 12 V
VCC = + 5 V
IDD
ISS
ICC
—
—
—
140
340
300
400
600
450
Parameter
Unit
V
µA
RECEIVER ELECTRICAL SPECIFICATIONS
(Voltage polarities referenced to GND = 0 V, VDD = + 5 to + 12 V, VSS = – 5 to – 12 V, VDD ≥ VCC, TA = – 40 to + 85°C)
Characteristic
Symbol
Min
Typ
Max
Unit
Input Turn–on Threshold
VDO1–DO3 = VOL, VCC = 5.0 V ± 5%
Rx1–Rx3
Von
1.35
1.80
2.35
V
Input Turn–off Threshold
VDO1–DO3 = VOH, VCC = 5.0 V ± 5%
Rx1–Rx3
Voff
0.75
1.00
1.25
V
Input Threshold Hysteresis
VCC = 5.0 V ± 5%
Rx1–Rx3
Von–Voff
0.6
0.8
—
V
Input Resistance
(VSS – 15 V) ≤ VRx1–Rx3 ≤ (VDD + 15 V)
Rx1–Rx3
Rin
3.0
5.4
7.0
kΩ
4.9
3.8
4.9
4.3
—
—
—
—
—
0.01
0.02
0.5
0.1
0.5
0.7
High–Level Output Voltage (VRx1–Rx3 = – 3 V to (VSS – 15 V))*
VOH
DO1–DO3
IOH = – 20 µA, VCC = + 5.0 V
IOH = – 1 mA, VCC = + 5.0 V
Low–Level Output Voltage (VRx1–Rx3 = + 3 V to (VDD + 15 V))* DO1–DO3
IOL = + 20 µA, VCC = + 5.0 V
IOL = + 2 mA, VCC = + 5.0 V
IOL = + 4 mA, VCC = + 5.0 V
V
VOL
V
* This is the range of input voltages as specified by EIA 232–E to cause a receiver to be in the high or low logic state.
MC145406
2
MOTOROLA
ELECTRICAL SPECIFICATIONS (Voltage polarities referenced to GND = 0 V, VCC = + 5 V ± 5%, TA = – 40 to + 85°C)
Characteristic
Digital Input Voltage
Logic 0
Logic 1
DI1–DI3
Input Current
VDI1–DI3 = VCC
DI1–DI3
Symbol
Min
Typ
Max
VIL
VIH
—
2.0
—
—
0.8
—
Iin
—
—
± 1.0
3.5
4.3
9.2
3.9
4.7
9.5
—
—
—
– 4.0
– 4.5
– 10.0
– 4.3
– 5.2
– 10.3
—
—
—
300
—
—
—
—
± 22
± 60
± 60
± 100
V
Output High Voltage (VDI1–3 = Logic 0, RL = 3.0 kΩ)
Tx1–Tx3
VDD = + 5.0 V, VSS = – 5.0 V
VDD = + 6.0 V, VSS = – 6.0
VDD = + 12.0 V, VSS = – 12.0 V
VOH
Output Low Voltage* (VDI1–3 = Logic 1, RL = 3.0 kΩ)
Tx1–Tx3
VDD = + 5.0 V, VSS = – 5.0 V
VDD = + 6.0 V, VSS = – 6.0 V
VDD = + 12.0 V, VSS = – 12.0 V
VOL
Off Source Resistance (Figure 1)
VDD = VSS = GND = 0 V, VTx1–Tx3 = ± 2.0 V
Tx1–Tx3
Output Short–Circuit Current (VDD = + 12.0 V, VSS = – 12.0 V)
Tx1–Tx3
Tx1–Tx3 shorted to GND**
Tx1–Tx3 shorted to ± 15.0 V***
Unit
µA
V
V
ISC
Ω
mA
* The voltage specifications are in terms of absolute values.
** Specification is for one Tx output pin to be shorted at a time. Should all three driver outputs be shorted simultaneously, device power dissipation
limits will be exceeded.
*** This condition could exceed package limitations.
SWITCHING CHARACTERISTICS (VCC = + 5 V ± 5%, TA = – 40 to + 85°C; See Figures NO TAG and NO TAG)
Drivers
Characteristic
Propagation Delay Time
Low–to–High
Symbol
Min
Typ
Max
Tx1–Tx3
RL = 3 kΩ, CL = 50 pF
High–to–Low
Unit
ns
tPLH
—
300
500
—
300
500
tPHL
RL = 3 kΩ CL = 50 pF
Output Slew Rate
Tx1–Tx3
Minimum Load
RL = 7 kΩ, CL = 0 pF, VDD = + 6 to + 12 V, VSS = – 6 to – 12 V
SR
V/µs
—
±9
± 30
4
—
—
—
—
—
Symbol
Min
Typ
Max
tPLH
—
150
425
Maximum Load
RL = 3 kΩ, CL = 2500 pF
VDD = + 12 V, VSS = – 12 V
VDD = + 5 V, VSS = – 5 V
Receivers (CL = 50 pF)
Characteristic
Propagation Delay Time
Low–to–High
DO1–DO3
High–to–Low
Unit
ns
tPHL
—
150
425
Output Rise Time
DO1–DO3
tr
—
250
400
ns
Output Fall Time
DO1–DO3
tf
—
40
100
ns
MOTOROLA
MC145406
3
PIN DESCRIPTIONS
1
VDD
14
16
VCC
DI1
VDD
Positive Power Supply (Pin 1)
3
Tx1
The most positive power supply pin, which is typically + 5
to + 12V.
12 DI2
10
Vin = ± 2 V
Tx2 5
DI3
The most negative power supply pin, which is typically – 5
to – 12 V.
7
Tx3
VSS
Negative Power Supply (Pin 8)
VSS GND
8
9
VCC
Digital Power Supply (Pin 16)
Vin
Rout =
I
The digital supply pin, which is connected to the logic
power supply (maximum + 5.5 V). V CC must be less than
or equal to V DD .
Figure 1. Power–Off Source Resistance (Drivers)
GND
Ground (Pin 9)
Ground return pin is typically connected to the signal
ground pin of the EIA 232–E connector (Pin 7) as well as to
the logic power supply ground.
DRIVERS
DI1–DI3
3V
Rx1, Rx2, Rx3
Receive Data Input (Pins 2, 4, 6)
0V
These are the EIA 232–E receive signal inputs whose
voltages can range from (VDD + 15 V) to (VSS – 15 V). A voltage between + 3 and (VDD + 15 V) is decoded as a space
and causes the corresponding DO pin to swing to ground (0
V); a voltage between – 3 and (VDD – 15 V) is decoded as a
mark and causes the DO pin to swing up to VCC. The actual
turn–on input switchpoint is typically biased at 1.8 V above
ground, and includes 800mV of hysteresis for noise rejection. The nominal input impedance is 5 kΩ. An open or
grounded input pin is interpreted as a mark, forcing the DO
pin to VCC.
50%
tf
tr
VOH
90%
Tx1–Tx3
10%
VOL
tPLH
tPHL
RECEIVERS
+3V
Rx1–Rx3
50%
0V
tPHL
tPLH
VOH
90%
DO1–DO3
50%
10%
tf
VOL
tr
Figure 2. Switching Characteristics
DRIVERS
3V
Tx1–Tx3
–3V
tSLH
SLEW RATE (SR) =
3V
–3V
tSHL
– 3 V – (3 V)
3 V – ( – 3 V)
OR
tSLH
tSHL
Figure 3. Slew–Rate Characterization
MC145406
4
DO1, DO2, DO3
Data Output (Pins 11, 13, 15)
These are the receiver digital output pins, which swing
from VCC to GND. A space on the Rx pin causes DO to produce a logic 0; a mark produces a logic 1. Each output pin is
capable of driving one LSTTL input load.
DI1, DI2, DI3
Data Input (Pins 10, 12,14)
These are the high–impedance digital input pins to the
drivers. TTL compatibility is accomplished by biasing the input switchpoint at 1.4 V above GND. However, 5–V CMOS
compatibility is maintained as well. Input voltage levels on
these pins must be between VCC and GND.
Tx1, Tx2, Tx3
Transmit Data Output(Pins 3, 5, 7)
These are the EIA 232–E transmit signal output pins,
which swing toward VDD and VSS. A logic 1 at a DI input
causes the corresponding Tx output to swing toward VSS. A
logic 0 causes the output to swing toward VDD (the output
voltages will be slightly less than VDD or VSS depending upon
the output load). Output slew rates are limited to a maximum
of 30 V per µs. When the MC145406 is off (VDD = VSS = VCC
= GND), the minimum output impedance is 300 Ω.
MOTOROLA
APPLICATIONS INFORMATION
The MC145406 has been designed to meet the electrical
specifications of standards EIA 232–E and CCITT V.28.
EIA 232–E defines the electrical and physical interface between Data Communication Equipment (DCE) and Data
Terminal Equipment (DTE). A DCE is connected to a DTE
using a cable that typically carries up to 25 leads. These
leads, referred to as interchange circuits, allow the transfer
of timing, data, control, and test signals. Electrically this
transfer requires level shifting between the TTL/CMOS logic levels of the computer or modem and the high voltage levels of EIA 232–E, which can range from ± 3 to ± 25 V. The
MC145406 provides the necessary level shifting as well as
meeting other aspects of the EIA 232–E specification.
DRIVERS
As defined by the specification, an EIA 232–E driver presents a voltage of between ± 5 to ± 15 V into a load of between 3 to 7 kΩ. A logic 1 at the driver input results in a
voltage of between – 5 to – 15 V. A logic 0 results in a voltage
between + 5 to + 15V. When operating VDD and VSS at ± 7 to
± 12 V, the MC145406 meets this requirement. When operating at ± 5 V, the MC145406 drivers produce less than
± 5 V at the output (when terminated), which does not meet
EIA 232–E specification. However, the output voltages when
using a ± 5 V power supply are high enough (around
± 4 V) to permit proper reception by an EIA 232–E receiver,
and can be used in applications where strict compliance to
EIA 232–E is not required.
Another requirement of the MC145406 drivers is that
they withstand a short to another driver in the EIA 232–E
cable. The worst–case condition that is permitted by
EIA 232–E is a ± 15 V source that is current limited to 500
mA. The MC145406 drivers can withstand this condition
momentarily. In most short circuit conditions the source
driver will have a series 300 Ω output impedance needed
to satisfy the EIA 232–E driver requirements. This will reduce the short circuit current to under 40 mA which is an
acceptable level for the MC145406 to withstand.
Unlike some other drivers, the MC145406 drivers feature
an internally–limited output slew–rate that does not exceed
30 V per µs.
RECEIVERS
The job of an EIA 232–E receiver is to level–shift voltages
in the range of – 25 to + 25 V down to TTL/CMOS logic levels (0 to + 5 V). A voltage of between – 3 and – 25 V on Rx1
is defined as a mark and produces a logic 1 at DO1. A voltage between + 3 and + 25 V is a space and produces a logic
zero. While receiving these signals, the Rx inputs must present a resistance between 3 and 7 kΩ. Nominally, the input resistance of the Rx1–Rx3 inputs is 5.4 kΩ.
The input threshold of the Rx1–Rx3 inputs is typically
biased at 1.8 V above ground (GND) with typically 800 mV of
hysteresis included to improve noise immunity. The 1.8 V
MOTOROLA
bias forces the appropriate DO pin to a logic 1 when its Rx
input is open or grounded as called for in the EIA 232–E
specification. Notice that TTL logic levels can be applied to
the Rx inputs in lieu of normal EIA 232–E signal levels. This
might be helpful in situations where access to the modem or
computer through the EIA 232–E connector is necessary
with TTL devices. However, it is important not to connect the
EIA 232–E outputs (Tx1–Tx3) to TTL inputs since TTL operates off + 5 V only, and may be damaged by the high output
voltage of the MC145406.
The DO outputs are to be connected to a TTL or CMOS
input (such as an input to a modem chip). These outputs
will swing from VCC to ground, allowing the designer to operate the DO and DI pins from digital power supply. The Tx
and Rx sections are independently powered by VDD and
VSS so that one may run logic at + 5 V and the EIA 232–E
signals at ± 12 V.
POWER SUPPLY CONSIDERATIONS
Figure 4 shows a technique to guard against excessive
device current.
The diode D1 prevents excessive current from flowing
through an internal diode from the V CC pin to the VDD pin
when VDD < VCC by approximately 0.6 V. This high current
condition can exist for a short period of time during power
up/down. Additionally, if the + 12 V supply is switched off
while the + 5 V is on and the off supply is a low impedance
to ground, the diode D1 will prevent current flow through
the internal diode.
The diode D2 is used as a voltage clamp, to prevent VSS
from drifting positive to VCC, in the event that power is removed from VSS (Pin 12). If VSS power is removed, and the
impedance from the V SS pin to ground is greater than
approximately 3 kΩ, this pin will be pulled to VCC by internal
circuitry causing excessive current in the VCC pin.
If by design, neither of the above conditions are allowed
to exist, then the diodes D1 and D2 are not required.
ESD PROTECTION
ESD protection on IC devices that have their pins accessible to the outside world is essential. High static voltages applied to the pins when someone touches them either directly
or indirectly can cause damage to gate oxides and transistor
junctions by coupling a portion of the energy from the I/O pin
to the power supply buses of the IC. This coupling will usually
occur through the internal ESD protection diodes. The key to
protecting the IC is to shunt as much of the energy to ground
as possible before it enters the IC. Figure 4 shows a technique which will clamp the ESD voltage at approximately ±
15 V using the MMVZ15VDLT1. Any residual voltage which
appears on the supply pins is shunted to ground through the
capacitors C1–C3. This scheme has provided protection to
the interface part up to ± 10 kV, using the human body model
test.
MC145406
5
VDD
MMBZ15VDLT × 6
TO
CONNECTOR
D1
IN4001
VCC
0.1 µF
0.1 µF
C1
C2
1
16
RxI
2
15
TxO
3
14
RxI
4
TxO
5
12
RxI
6
11
TxO
7
10
8
9
MC145406
C3
VSS
IN5818
13
D2
0.1 µF
Figure 4. ESD and Power Supply Networks
MC145406
6
MOTOROLA
+ 5V
0.1 µF
20 kΩ
DTMF
INPUT
TLA
CDSI
RDSI
20 kΩ
RTLA**
1 DSI
17 TxA
0.1 µF
6
VDD
10 µF
TIP
Xout
CD
*
SQT
3.579
MHz
8
18
10
ExI
LB
11
15
Tx1
DO1
Rx1
DI2
Tx2
3
2
8
2
12
5
3
14
2
NC 13 DO2
10
Rx2
4
EIA 232–E
DB–25
CONNECTOR
7
Tx3 7 NC
DI3
10 kΩ
10 k
MODE
GND
12
DI1
5
FB
0.1 µF 19
VAG
4
CDT
0.1 µF
CCDT
14
3
10 kΩ
CFB
1
16
VDD
VCC
MC145406
9
10 kΩ
RxA1
600:600
VDD
0.1 µF
VSS BYPASS
RxD
16
RING
0.1 µF
VDD BYPASS
TxD
RTx
600
+
Xin
MC145442/3
15 RxA2
10 kΩ
0.1 µF
CDA
NC 11 DO3
13
7
CCDA**
0.1 µF
Rx3
VSS
8
6
GND
9
0.1 µF
*Line protection circuit
**Refer to the applications information for values of CCDA and RTLA
–5V
Figure 5. 5–V 300–Baud Modem with EIA 232–E Interface
MOTOROLA
MC145406
7
MC34119
SPEAKER
DRIVER
MC145503
FILTER/
CODEC
MC145412/13/16
PULSE/TONE
DIALER
RINGING
MC145426
UDLT
1
4
7
*
2
5
8
0
3
6
9
#
LINE
INTERFACE
(TRANSFORMER
AND
PROTECTION)
HOOKSWITCH
TWISTED
PAIR
SYNC
CONNECTION
TO EXTERNAL
TERMINAL
OR PC
MC145406
RS–232
DRIVER
RECEIVER
MC145428
DATA
SET
INTERFACE
+5V
GND
–5V
MC34129
SWITCHING
POWER
SUPPLY
(ISOLATED)
LINE
FILTER
Figure 6. Line–Powered Voice/Data Telephone with Electrically Isolated EIA 232–E Interface
MC145406
8
MOTOROLA
MOTOROLA
6
VSS
VDD
8
2
4
6
3
5
7
GND
VSS
Rx1
Rx2
Rx3
Tx1
Tx2
Tx3
VCC
DO1
DO2
DO3
DI1
DI2
DI3
MC145406
1 V
DD
16
15
13
11
14
12
10
9
*For optional filtering.
**TR1 should be cut when this capacitor is used.
2
Tx
4
RTS
8
CD
5
CTS 3
Rx
7
SG
DB-25
DSR
R5
VDD
ST
ST
ST
ST
ST
NC
D2
R2 C1
13 3
NC
5
6
2
8
9
10
11
0.1 µF
12
5
RxS
BC
2
TxD
MC145428
3
TxS 1
DL
4 BRCLK RESET 19
DCO 18
11 RxD
DOE 17
DC 15
6 BR1
DIE 14
7 BR2
8 BR3
13
DCI 16
9 SB
CM
10 V
VDD 20
SS
12
Q1
Q1
D1
Q
Q2
Q2
S2
C2
VCC
NC
ST
NC
NC
NC
NC
9
14
VSS IN1 1
7
18
19
17
14
12
15
9
2
7
12
1
14
D2
D1
10 k
0.1 µF 0.1 µF
6
7
T1
NC
5
8
1000
pF*
6 13
3
4
1
2
220
NC
10
9
8
1.0 µ F**
RING
TIP
NC NC NC
3 4 5
Q1 Q2 Q3
Ca a a a 11
Q1b
NC
VCC
MC74HC393
10
Q2b
NC
Ra
9
GND
Q3b
NC
Q2b
Q4a Qb Q4b
Rx PD CCI SO2
SI2 VD LB
21
LO1
RE1
20
TDC/RDC
LO2
MC145422
TE1
MSI
220
TxSO1 SI1 L1 SE VDD Vref VSS SIE
7 6 3 10 22
2
1 13
ST
11 16
4.096 MHz
20 pF
128 kHz
8 MHz
4.096
MHz
10 M
20 pF
0.1 µF
NC ST
8 5 4
VCC
MC14069UB
IN3
2
OUT1
6 OUT3
3
OUT6 OUT5 IN6 IN5 IN2
12 10 13 11
5
OUT4 IN4
4
VDD
OUT2
8
NC NC
0.1 µF
2.048 MHz
ST — STRAP
NC — NO CONNECTION
VCC = 5 V
GND = 0 V
VDD AND VSS ARE DISCUSSED IN THE EIA-232-D SECTION
C14
VCC
NC
0.1 µF
VCC
1 4
R1 S1
14
VCC
MC74HC74
7 GND
TR1
Figure 7. 80–kbps Limited Distance Modem with EIA 232–E Interface (Master)
MC145406
9
PACKAGE DIMENSIONS
P SUFFIX
CASE 648–08
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
-A16
9
1
8
B
F
C
L
S
-T-
SEATING
PLANE
K
H
D 16 PL
0.25 (0.010)
M
J
G
T A
M
STYLE 1:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
M
STYLE 2:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
CATHODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
ANODE
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040 0.070
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0°
10°
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0°
10°
0.51
1.01
COMMON DRAIN
COMMON DRAIN
COMMON DRAIN
COMMON DRAIN
COMMON DRAIN
COMMON DRAIN
COMMON DRAIN
COMMON DRAIN
GATE
SOURCE
GATE
SOURCE
GATE
SOURCE
GATE
SOURCE
DW SUFFIX
CASE 751G–02
-A16
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
9
-B-
P 8 PL
0.25 (0.010)
1
M
B
M
8
G 14 PL
J
F
R X 45°
C
-TD 16 PL
0.25 (0.010)
MC145406
10
M
T
M
SEATING
PLANE
K
A
S
B
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
10.15 10.45
7.60
7.40
2.65
2.35
0.49
0.35
0.90
0.50
1.27 BSC
0.32
0.25
0.25
0.10
7°
0°
10.05 10.55
0.25
0.75
INCHES
MIN
MAX
0.400 0.411
0.292 0.299
0.093 0.104
0.014 0.019
0.020 0.035
0.050 BSC
0.010 0.012
0.004 0.009
0°
7°
0.395 0.415
0.010 0.029
S
MOTOROLA
SD SUFFIX
CASE 940B–02
16
8
L
B
-R1
0.250 (0.010)
M
R
M
7
A
-P-
J
M
F
NOTE 4
C
-T-
G
H
0.120 (0.005)
MOTOROLA
N
D
M
T P
S
0.076 (0.003)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION IS THE LENGTH OF TERMINAL
FOR SOLDERING TO A SUBSTRATE.
5. TERMINAL POSITIONS ARE SHOWN FOR
REFERENCE ONLY.
6. THE LEAD WIDTH DIMENSION DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION.
DIM
A
B
C
D
F
G
H
J
L
M
N
MILLIMETERS
MIN
MAX
6.10
6.30
5.20
5.38
1.75
1.99
0.25
0.38
0.65
1.00
0.65 BSC
0.73
0.90
0.10
0.20
7.65
7.90
0_
8_
0.05
0.21
INCHES
MIN
MAX
0.240
0.248
0.205
0.212
0.069
0.078
0.010
0.015
0.026
0.039
0.026 BSC
0.029
0.035
0.004
0.008
0.301
0.311
0_
8_
0.002
0.008
MC145406
11
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MC145406
12
◊
CODELINE TO BE PLACED HERE
*MC145406/D*
MC145406/D
MOTOROLA