INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4060 14-stage binary ripple counter with oscillator Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 terminals (RS, RTC and CTC), ten buffered outputs (Q3 to Q9 and Q11 to Q13) and an overriding asynchronous master reset (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may be replaced by an external clock signal at input RS. In this case keep the other oscillator pins (RTC and CTC) floating. FEATURES • All active components on chip • RC or crystal oscillator configuration • Output capability: standard (except for RTC and CTC) • ICC category: MSI The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (Q3 to Q9 and Q11 to Q13 = LOW), independent of other input conditions. GENERAL DESCRIPTION The 74HC/HCT4060 are high-speed Si-gate CMOS devices and are pin compatible with “4060” of the “4000B” series. They are specified in compliance with JEDEC standard no. 7A. In the HCT version, the MR input is TTL compatible, but the RS input has CMOS input switching levels and can be driven by a TTL output by using a pull-up resistor to VCC. The 74HC/HCT4060 are 14-stage ripple-carry counter/dividers and oscillators with three oscillator QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER tPHL/ tPLH CONDITIONS UNIT HC HCT RS to Q3 31 31 ns Qn to Qn+1 6 6 ns MR to Qn propagation delay CL = 15 pF; VCC = 5 V 17 18 ns fmax maximum clock frequency 87 88 MHz CI input capacitance 3.5 3.5 pF CPD power dissipation capacitance per package 40 40 pF tPHL notes 1, 2 and 3 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC − 1.5 V 3. For formula on dynamic power dissipation see next pages. ORDERING INFORMATION See “74HC/HCT/HCU/HCMOS Logic Package Information”. December 1990 2 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2, 3 Q11 to Q13 counter outputs 7, 5, 4, 6, 14, 13, 15 Q3 to Q9 counter outputs 8 GND ground (0 V) 9 CTC external capacitor connection 10 RTC external resistor connection 11 RS clock input/oscillator pin 12 MR master reset 16 VCC positive supply voltage Fig.1 Pin configuration. December 1990 Fig.2 Logic symbol. 3 Fig.3 IEC logic symbol. Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 DYNAMIC POWER DISSIPATION FOR 74HC PARAMETER VCC (V) TYPICAL FORMULA FOR PD (µW) (note 1) total dynamic power dissipation when using the on-chip oscillator (PD) CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 60 × VCC CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 1 750 × VCC CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 3 800 × VCC 2.0 4.5 6.0 Note 1. GND = 0 V; Tamb = 25 °C DYNAMIC POWER DISSIPATION FOR 74HCT PARAMETER VCC (V) total dynamic power dissipation when using the on-chip oscillator (PD) 4.5 TYPICAL FORMULA FOR PD (µW) (note 1) CPD × fosc × VCC2 + ∑ (CL × VCC2 × fo) + 2Ct × VCC2 × fosc + 1 750 × VCC Notes 1. GND = 0 V; Tamb = 25 °C 2. Where: fo = output frequency in MHz fosc = oscillator frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF Ct = timing capacitance in pF VCC = supply voltage in V Fig.4 Functional diagram. APPLICATIONS • Control counters • Timers • Frequency dividers • Time-delay circuits December 1990 4 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator Fig.5 Logic diagram. Fig.6 Timing diagram. December 1990 5 74HC/HCT4060 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 DC CHARACTERISTICS FOR 74HC Output capability: standard (except for RTC and CTC) ICC category: MSI Voltages are referenced to GND (ground = 0 V) Tamb (°C) SYMBOL TEST CONDITIONS 74HC PARAMETER min. 1.5 3.15 4.2 +25 −40 to +85 typ. max. min. 1.3 2.4 3.1 1.5 3.15 4.2 VIH HIGH level input voltage MR input VIL LOW level input voltage MR input VIH HIGH level input voltage RS input VIL LOW level input voltage RS input VOH HIGH level output voltage 3.98 RTC output 5.48 3.84 5.34 3.98 5.48 3.84 5.34 0.8 0.5 2.1 1.35 2.8 1.8 1.7 3.6 4.8 max. −40 to +125 min. V 2.0 4.5 6.0 V 2.0 4.5 6.0 V 2.0 4.5 6.0 V 2.0 4.5 6.0 3.7 5.2 V 4.5 RS=GND −IO = 2.6 mA −IO = 3.3 mA 6.0 and 3.7 5.2 V 4.5 RS=VCC 6.0 and 0.5 1.35 1.8 0.5 1.35 1.8 1.7 3.6 4.8 0.3 0.9 1.2 OTHER max. 1.5 3.15 4.2 1.7 3.6 4.8 UNIT V VI CC (V) 0.3 0.9 1.2 0.3 0.9 1.2 MR=GND −IO = 0.65 mA −IO = 0.85 mA MR=VCC VOH 1.9 4.4 5.9 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 V 2.0 RS=GND −IO = 20 µA −IO = 20 µA 4.5 and 6.0 MR=GND −IO = 20 µA 1.9 4.4 5.9 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 V 2.0 RS=VCC 4.5 and 6.0 MR=VCC −IO = 20 µA −IO = 20 µA −IO = 20 µA 3.84 5.34 3.7 5.2 V 4.5 RS=VIH 6.0 and −IO = 3.2 mA −IO = 4.2 mA HIGH level output voltage 3.98 CTC output 5.48 MR=VIL VOH HIGH level output voltage 1.9 except RTC output 4.4 VOH HIGH level output voltage 3.98 except RTC and CTC 5.48 outputs VOL LOW level output voltage RTC output 5.9 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 V 2.0 VIH 4.5 or 6.0 VIL −IO = 20 µA −IO = 20 µA −IO = 20 µA 3.84 5.34 3.7 5.2 V 4.5 VIH 6.0 or VIL −IO = 4.0 mA −IO = 5.2 mA 4.5 RS=VCC 6.0 and IO = 2.6 mA IO = 3.3 mA 0.26 0.26 0.33 0.33 0.4 0.4 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 MR=GND 0 0 0 December 1990 6 V 2.0 RS=VCC IO = 20 µA IO = 20 µA 4.5 and 6.0 MR=GND IO = 20 µA Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 Tamb (°C) SYMBOL 74HC PARAMETER min. VOL TEST CONDITIONS +25 −40 to +85 typ. max. min. 0.26 0.26 LOW level output voltage CTC output max. 0.33 0.33 −40 to +125 min. UNIT V VI CC (V) OTHER V IO = 3.2 mA IO = 4.2 mA max. 0.4 0.4 4.5 RS=VIL 6.0 and MR=VIH 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 V 2.0 VIH 4.5 or 6.0 VIL IO = 20 µA IO = 20 µA IO = 20 µA LOW level output voltage except RTC and CTC outputs 0.26 0.26 0.33 0.33 0.4 0.4 V 4.5 VIH 6.0 or VIL IO = 4.0 mA IO = 5.2 mA ±II input leakage current 0.1 1.0 1.0 µA 6.0 VCC or GND ICC quiescent supply current 8.0 80.0 160.0 µA 6.0 VCC or GND VOL LOW level output voltage except RTC output VOL December 1990 0 0 0 7 IO = 0 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. UNIT VCC WAVEFORMS (V) max. tPHL/ tPLH propagation delay RS to Q3 99 36 29 300 60 51 375 75 64 450 90 77 ns 2.0 4.5 6.0 Fig.12 tPHL/ tPLH propagation delay Qn to Qn+1 22 8 6 80 16 14 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.14 tPHL propagation delay MR to Qn 55 20 16 175 35 30 220 44 37 265 53 45 ns 2.0 4.5 6.0 Fig.13 tTHL/ tTLH output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 Fig.12 tW clock pulse width RS; HIGH or LOW 80 16 14 17 6 5 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.12 tW master reset pulse width MR; HIGH 80 16 14 25 9 7 100 20 17 120 24 20 ns 2.0 4.5 6.0 Fig.13 trem removal time MR to RS 100 28 20 10 17 8 125 25 21 150 30 26 ns 2.0 4.5 6.0 Fig.13 fmax maximum clock pulse frequency 6.0 30 35 4.8 24 28 4.0 20 24 2.0 MHz 4.5 6.0 Fig.12 December 1990 26 80 95 8 TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. VIH HIGH level input voltage VIL LOW level input voltage VOH HIGH level output voltage RTC output typ. −40 to +85 −40 to +125 max. 2.0 min. max. 2.0 0.8 3.98 min. VCC (V) VI OTHER max. 2.0 0.8 UNIT 0.8 V 4.5 to 5.5 note 2 V 4.5 to 5.5 note 2 3.84 3.7 V 4.5 RS=GND and MR=GND −IO = 2.6 mA 9 3.84 3.7 V 4.5 RS = VCC and MR = VCC −IO = 0.65 mA 4.4 4.5 4.4 4.4 V 4.5 RS=GND and MR=GND −IO = 20 µA 4.4 4.5 4.4 4.4 V 4.5 RS=VCC and MR=VCC −IO = 20 µA 3.84 3.7 V 4.5 RS = VIH and MR = VIL −IO = 3.2 mA 4.4 4.4 V 4.5 VIH or VIL −IO = 20 µA 3.84 3.7 V 4.5 VIH or VIL −IO = 4.0 mA 3.98 VOH HIGH level output voltage CTC output 3.98 VOH HIGH level output voltage except RTC output 4.4 VOH HIGH level output voltage except RTC and CTC outputs 3.98 VOL LOW level output voltage RTC output 4.5 0 0.33 0.4 V 4.5 RS=VCC and MR=GND IO = 2.6 mA 0.1 0.1 V 4.5 RS=VCC and MR=GND IO = 20 µA 0.26 0.33 0.4 V 4.5 RS = VIL and MR = VIH IO = 3.2 mA 0.1 0.1 0.1 V 4.5 VIH or VIL IO = 20 µA IO = 4.0 mA LOW level output voltage CTC output VOL LOW level output voltage except RTC output VOL LOW level output voltage except RTC and CTC outputs 0.26 0.33 0.4 V 4.5 VIH or VIL ±I input leakage current 0.1 1.0 1.0 µA 5.5 VCC or GND ICC quiescent supply current 5.5 VCC or GND IO = 0 ∆ICC additional quiescent supply current per input pin for unit load coefficient is 1 (note 1) 4.5 to 5.5 VCC − 2.1 V other inputs at VCC or GND; IO = 0 0 8.0 80.0 160.0 µA 100 360 450 490 µA Product specification VOL 74HC/HCT4060 0.26 0.1 Philips Semiconductors Tamb (°C) 14-stage binary ripple counter with oscillator December 1990 DC CHARACTERISTICS FOR 74HCT Output capability: standard (except for RTC and CTC) ICC category: MSI Voltages are referenced to GND (ground = 0 V) Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 Notes 1. The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given here. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. 2. Only input MR (pin 12) has TTL input switching levels for the HCT versions. INPUT UNIT LOAD COEFFICIENT MR 0.40 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 min. −40 to +85 typ. max. min. max. −40 to +125 min. UNIT V WAVEFORMS CC (V) max. tPHL/ tPLH propagation delay RS to Q3 33 66 83 99 ns 4.5 Fig.12 tPHL/ tPLH propagation delay Qn to Qn+1 8 16 20 24 ns 4.5 Fig.14 tPHL propagation delay MR to Qn 21 44 55 66 ns 4.5 Fig.13 tTHL/ tTLH output transition time 7 15 19 22 ns 4.5 Fig.12 tW clock pulse width RS; HIGH or LOW 16 6 20 24 ns 4.5 Fig.12 tW master reset pulse width MR; HIGH 16 6 20 24 ns 4.5 Fig.13 trem removal time MR to RS 26 13 33 39 ns 4.5 Fig.13 fmax maximum clock pulse frequency 30 80 24 20 MHz 4.5 Fig.12 December 1990 10 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 MBA333 14 handbook, g halfpage fs (mA/V) max. 12 typ. 10 8 min. 6 4 Fig.7 Test set-up for measuring forward transconductance gfs = dio / dvi at vo is constant (see also graph Fig.8); MR = LOW. 2 Fig.8 0 1 2 3 4 5 VCC (V) 6 Typical forward transconductance gfs as a function of the supply voltage VCC at Tamb = 25 °C. RC OSCILLATOR Fig.9 Typical formula for oscillator frequency: 1 f osc = -------------------------------2.5 × R t × C t RC oscillator frequency as a function of Rt and Ct at VCC = 2.0 to 6.0 V; Tamb = 25 °C. Ct curve at Rt = 100 kΩ; R2 = 200 kΩ. Rt curve at Ct = 1 nF; R2 = 2 × Rt. Fig.10 Example of a RC oscillator. TIMING COMPONENT LIMITATIONS The oscillator frequency is mainly determined by RtCt, provided R2 ≈ 2Rt and R2C2 << RtCt. The function of R2 is to minimize the influence of the forward voltage across the input protection diodes on the frequency. The stray capacitance C2 should be kept as small as possible. In consideration of accuracy, Ct must be larger than the inherent stray capacitance. Rt must be larger than the “ON” resistance in series with it, which typically is 280 Ω at VCC = 2.0 V, 130 Ω at VCC = 4.5 V and 100 Ω at VCC = 6.0 V. The recommended values for these components to maintain agreement with the typical oscillation formula are: Ct > 50 pF, up to any practical value, 10 kΩ < Rt < 1 MΩ. In order to avoid start-up problems, Rt ≥ 1 kΩ. December 1990 11 Philips Semiconductors Product specification 14-stage binary ripple counter with oscillator 74HC/HCT4060 TYPICAL CRYSTAL OSCILLATOR In Fig.11, R2 is the power limiting resistor. For starting and maintaining oscillation a minimum transconductance is necessary, so R2 should not be too large. A practical value for R2 is 2.2 kΩ. Fig.11 External components connection for a crystal oscillator. AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.12 Waveforms showing the clock (RS) to output (Q3) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. Fig.13 Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (RS) removal time. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.14 Waveforms showing the output (Qn) to Qn+1 propagation delays. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. December 1990 12