INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT6323A Programmable ripple counter with oscillator; 3-state Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state FEATURES • 8-pin space saving package • Programmable 3-stage ripple counter 74HC/HCT6323A capacitors minimize external component count for third overtone crystal applications. and sets the output buffer in the 3-state condition. MR can be left floating since an internal pull-up resistor will make the MR inactive. In the HCT version, the MR input and the two mode select pins S1 and S2 are TTL compatible, but the X1 input has CMOS input switching levels and may be driven by a TTL output using a pull-up resistor connected to VCC. • Two internal capacitors The oscillator may be replaced by an external clock signal at input X1. In this event the other oscillator pin (X2) must be floating. The counter advances on the negative-going transition of X1. A LOW level on MR resets the counter, stops the oscillator • Recommended operating range for use with third overtone crystals 3 to 6 V QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. • Suitable for over-tone crystal application up to 50 MHz (VCC = 5 V ± 10%) • 3-state output buffer • Oscillator stop function (MR) TYP. • Output capability: bus driver → (15 LSTTL) SYMBOL • ICC category: MSI. tPHL/tPLH propagation delay X1 to OUT (S1 = S2 = LOW) fmax APPLICATIONS • Control counters • Timers CONDITIONS UNIT HC 17 ns maximum clock frequency 90 90 MHz CI input capacitance except X1 and X2 3.5 3.5 pF CPD power dissipation capacitance per package +1; notes 1 and 2 54 54 pF +2; notes 1 and 2 42 42 pF +4; notes 1 and 2 36 36 pF +8; notes 1 and 2 33 33 pF • CIO (Compact Integrated Oscillator) • Third-overtone crystal operation. CL = 15 pF; VCC = 5 V HCT 17 • Frequency dividers • Time-delay circuits PARAMETER Notes GENERAL DESCRIPTION The HC/HCT6323A are high-speed Si-gate CMOS devices. 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = (CPD x VCC2 x fi) + (CL + VCC2 x fo) + (Ipull-up x VCC) where: They are specified in compliance with JEDEC standard no. 7A. fi = input frequency in MHz; fo = output frequency in MHz. The HC/HCT6323A are oscillators designed for quartz crystal combined with a programmable 3-state counter, a 3-state output buffer and an overriding asynchronous master reset (MR). With the two select inputs S1 and S2 the counter can be switched in the divide-by-1, 2, 4 or 8 mode. If left floating the clock is divided by 8. The oscillator is designed to operate either in the fundamental or third overtone mode depending on the crystal and external components applied. On-chip Ipull-up = pull-up currents in µA. September 1993 VCC = supply voltage in V; CL = output load capacitance in pF. 2. For HC and HCT an external clock is applied to X1 with: tr = tf ≤ 6 ns, Vi is GND to VCC, MR = HIGH Ipull-up is the summation of −II (µA) of S1 and S2 inputs at the LOW state. ORDERING INFORMATION PACKAGE EXTENDED TYPE NUMBER PINS PIN POSITION MATERIAL CODE 74HC/HCT6323AD 8 SO plastic SOT96 2 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A PINNING FUNCTION TABLE SYMBOL PIN OUT 1 S1 - S2 DESCRIPTION INPUTS counter output 3, 2 OUTPUTS S1 S2 OUT mode select inputs for divide by 1, 2, 4 or 8 0 0 fi 0 1 fi/2 GND 4 ground (0 V) 1 0 fi/4 MR 5 master reset (active LOW) 1 1 fi/8 X2 6 oscillator pin X1 7 clock input/oscillator pin VCC 8 positive supply 6 handbook, halfpage handbook, halfpage OUT S2 1 8 2 VCC 7 X1 6323A S1 3 6 X2 GND 4 5 MR 7 5 X2 X1 CP MR CD MBA343 3 S1 2 S2 OUT 1 MBA344 Fig.1 Pin configuration. Fig.2 IEC logic symbol. 6 handbook, full pagewidth X2 7 X1 5 MR 3 - STAGE BINARY COUNTER AND DECODER CP CD S1 MBA350 3 S2 2 Fig.3 Functional diagram. September 1993 3 OUT 1 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state handbook, full pagewidth 74HC/HCT6323A X2 X1 7 pF (1) VCC 7 pF CP Q CP Q CP Q FF FF FF R R R (1) V CC DECODER VCC MBA349 VCC VCC OUT MR S1 S2 Internal capacitors typical 7 pF each. Including stray capacitors on pin X1 and X2, total capacitance will be typical 12 pF per pin. Fig.4 Logic diagram. September 1993 4 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: non-standard; bus driver (except for X2) ICC category: MSI. Voltages are referenced to GND (ground = 0 V). DC CHARACTERISTICS FOR 74HC Tamb(°C) SYMBOL −40 to 85 MIN −40 to 125 UNIT V CC (V) MAX MIN MAX 25 PARAMETER TEST CONDITION MIN TYP MAX VI OTHER VIH HIGH level input voltage MR, X1 input 1.5 3.15 4.2 1.2 2.4 3.2 − − − 1.5 3.15 4.2 − − − 1.50 − 3.15 − 4.20 − V V V 2.0 4.5 6.0 VIL LOW level input voltage MR, X1 input − − − 0.8 2.1 2.8 0.5 1.35 1.80 − − − 0.5 1.35 1.8 − − − 0.5 1.35 1.8 V V V 2.0 4.5 6.0 VOH HIGH level output voltage X2 output 3.98 5.48 − − − − 3.84 5.34 − − 3.7 5.2 − − V V 4.5 6.0 X1 = GND and MR = VCC IO = −2.6 mA IO = −3.3 mA 3.98 5.48 − − − − 3.84 5.34 − − 3.7 5.2 − − V V 4.5 6.0 X1 = VCC and MR = GND IO = −2.6 mA IO = −3.3 mA 1.9 4.4 5.9 2.0 4.5 6.0 − − − 1.9 4.4 5.9 − − − 1.9 4.4 5.9 − − − V V V 2.0 4.5 6.0 X1 = GND and MR = VCC −IO = 20 µA IO = −20 µA IO = −20 µA 1.9 4.4 5.9 2.0 4.5 6.0 − − − 1.9 4.4 5.9 − − − 1.9 4.4 5.9 − − − V V V 2.0 4.5 6.0 X1 = VCC and MR = GND IO = −20 µA IO = −20 µA IO = −20 µA VOH HIGH level output voltage OUT 1.9 4.4 5.9 2.0 4.5 6.0 − − − 1.9 4.4 5.9 − − − 1.9 4.4 5.9 − − − V V V 2.0 4.5 6.0 VIH or VIL IO = −20 µA IO = −20 µA IO = −20 µA VOH HIGH level output voltage OUT 3.98 5.48 − − − − 3.84 5.34 − − 3.7 5.2 − − V V 4.5 6.0 VIH or VIL IO = −6 mA IO = −7.8 mA VOL LOW level output voltage X2 output − − − − 0.26 0.26 − − 0.33 0.33 − − 0.4 0.4 V V 4.5 6.0 X1 = VCC and MR = VCC IO = 2.6 mA IO = 3.3 mA − − − 0 0 0 0.1 0.1 0.1 − − − 0.1 0.1 0.1 − − − 0.1 0.1 0.1 V V V 2.0 4.5 6.0 X1 = VCC and MR = VCC IO = 20 µA IO = 20 µA IO = 20 µA − − − 0 0 0 0.1 0.1 0.1 − − − 0.1 0.1 0.1 − − − 0.1 0.1 0.1 V V V 2.0 4.5 6.0 VIH or VIL IO = 20 µA IO = 20 µA IO = 20 µA VOL LOW level output voltage OUT September 1993 5 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A Tamb(°C) SYMBOL TEST CONDITION MIN TYP MAX MIN −40 to 125 UNIT V CC (V) MAX MIN MAX PARAMETER −40 to 85 25 VI OTHER VOL LOW level output voltage OUT − − − − 0.26 0.26 − − 0.33 0.33 − − 0.4 0.4 V V 4.5 6.0 VIH or VIL ±ILI input leakage current X1 − − 0.1 − 1 − 1 µA 6.0 MR = VCC S1 = VCC S2 = VCC −II input pull-up current S1, S2 and MR 5 30 100 − − − − µA 6.0 GND see Fig.11 and Fig.12 ICC quiescent supply current − − 8 − 80 − 160 µA 6.0 VCC or GND IO = 0 September 1993 6 IO = 6 mA IO = 7.8 mA Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Tamb (°C) SYMBOL PARAMETER −40 to 85 25 MIN TEST CONDITION −40 to 125 TYP MAX MIN MAX MIN MAX UNIT VCC (V) VI OTHER tPHL/tPLH propagation − delay X1 to − OUT divide by 1 − 61 22 19 185 37 31 − − − 230 46 39 − − − 275 55 47 ns ns ns 2.0 4.5 6.0 Fig.7 S1 = GND S2 = GND tPHL/tPLH propagation − delay X1 to − OUT divide by 2 − 74 27 23 235 47 40 − − − 290 58 49 − − − 350 70 60 ns ns ns 2.0 4.5 6.0 Fig.7 S1 = GND S2 = VCC tPHL/tPLH propagation − delay X1 to − OUT divide by 4 − 91 33 28 285 57 48 − − − 355 71 60 − − − 425 85 72 ns ns ns 2.0 4.5 6.0 Fig.7 S1 = VCC S2 = GND tPHL/tPLH propagation − delay X1 to − OUT divide by 8 − 105 38 32 335 67 57 − − − 415 83 71 − − − 500 100 85 ns ns ns 2.0 4.5 6.0 Fig.7 S1 = VCC S2 = VCC tPLZ/tPHZ 3-state output disable time MR to OUT − − − 75 15 13 150 30 26 − − − 185 37 31 − − − 225 45 38 ns ns ns 2.0 4.5 6.0 Fig.8 tPZL 3-state output enable time MR to OUT − − − 36 13 11 150 30 26 − − − 185 37 31 − − − 225 45 38 ns ns ns 2.0 4.5 6.0 Fig.8 tPZH 3-state output enable time MR to OUT − − − 61 22 19 200 40 34 − − − 250 50 43 − − − 300 60 51 ns ns ns 2.0 4.5 6.0 Fig.8 tTHL/tTLH output transition time − − − 14 5 4 60 12 10 − − − 75 15 13 − − − 90 19 15 ns ns ns 2.0 4.5 6.0 Fig.7 tW clock pulse width X1, HIGH or LOW 50 10 9 17 6.0 5 − − − 60 12 10 − − − 75 15 13 − − − ns ns ns 2.0 4.5 6.0 Fig.7 tW master reset pulse width MR; LOW 80 16 14 22 8 7 − − − 100 20 17 − − − 120 24 20 − − − ns ns ns 2.0 4.5 6.0 Fig.9 trem removal time MR to X1 100 20 17 19 7 6.0 − − − 125 25 21 − − − 150 30 26 − − − ns ns ns 2.0 4.5 6.0 Fig.9 fmax maximum clock 10 pulse frequency 50 59 17 85 100 − − − 8 40 47 − − − 6.6 33 39 − − − MHz MHz MHz 2.0 4.5 6.0 Fig.7 Note to the 74HC AC Characteristics 1. tPZH only applicable in the divide-by-1 mode and X1 must be HIGH. September 1993 7 note 1 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver (except for X2). ICC category: MSI. Voltages are referenced to GND (ground = 0 V). Tamb (°C) SYMBOL TEST CONDITION −40 to 85 25 −40 to 125 MIN TYP MAX MIN MAX MIN UNIT V CC (V) MAX PARAMETER VI OTHER IO = −2.6 mA VIH HIGH level input voltage MR, S1 and S2 inputs 2.0 − − 2.0 − 2.0 − V 4.5 to 5.5 VIL LOW level input voltage MR, S1 and S2 inputs − − 0.8 − 0.8 − 0.8 V 4.5 to 5.5 VIH HIGH level input voltage X1 input 3.15 3.85 − − − − 3.15 3.85 − − 3.15 3.85 − − V V 4.5 5.5 VIL LOW level input voltage X1 input − − − − 1.35 1.65 − − 1.35 1.65 − − 1.35 1.65 V V 4.5 5.5 VOH HIGH level output voltage X2 output 3.98 − − 3.84 − 3.7 − V 4.5 X1 = GND and MR = VCC 3.98 − − 3.84 − 3.7 − V 4.5 IO = −2.6 mA X1 = VCC and MR = GND 4.4 4.5 − 4.4 − 4.4 − V 4.5 X1 = GND and MR = VCC 4.4 4.5 − 4.4 − 4.4 − V 4.5 IO = −20 mA X1 = VCC and MR = GND IO = −20 µA VOH HIGH level output voltage OUT 4.4 4.5 − 4.4 − 4.4 − V 4.5 VIH or VIL IO = −20 µA VOH HIGH level output voltage OUT 3.98 − − 3.84 − 3.7 − V 4.5 VIH or VIL IO = −6 mA September 1993 8 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A Tamb (°C) SYMBOL PARAMETER TEST CONDITION −40 to 85 −40 to 125 MIN TYP MAX MIN MAX MIN UNIT V CC (V) MAX LOW level output voltage X2 output − − 0.26 − 0.33 − 0.4 V − 0 0.1 − 0.1 − 0.1 VOL LOW level output voltage OUT − 0 0.1 − 0.1 − VOL LOW level output voltage OUT − − 0.26 − 0.33 ±ILI input leakage current − − 0.1 − −II input pull-up current S1, S2 and MR 5 25 100 ICC quiescent supply current − − ∆ICC additional quiescent supply current per input pin for unit load coefficient is 1 − 100 VOL 25 VI OTHER 4.5 X1 = VCC and MR = VCC IO = 2.6 mA V 4.5 X1 = VCC and MR = VCC IO = 20 µA 0.1 V 4.5 VIH or VIL IO = 20 µA − 0.4 V 4.5 VIH or VIL IO = 6 mA 1.0 − 1.0 µA 5.5 MR = VCC; S1 = VCC; S2 = VCC − − − − µA 5.5 GND see Fig.11 and Fig.12 8 − 80 − 160 µA 5.5 VCC or GND Io = 0 360 − 450 − 490 µA 5.5 VCC or GND other inputs at VCC or GND; Io = 0; (note 1) Note to the HCT DC Characteristics 1. The value of additional quiescent supply current (∆ICC) for unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD COEFFICIENT September 1993 INPUT UNIT LOAD COEFFICIENT MR, S1, S2 0.40 9 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) SYMBOL PARAMETER −40 to 85 25 TEST CONDITION −40 to 125 MIN TYP MAX MIN MAX MIN MAX UNIT VCC (V) VI OTHER tPHL/tPLH propagation delay X1 to OUT divide-by-1 − 24 40 − 50 − 60 ns 4.5 Fig.7 S1 = GND S2 = GND tPHL/tPLH propagation delay X1 to OUT divide-by-2 − 29 50 − 62 − 75 ns 4.5 Fig.7 S1 = GND S2 = VCC tPHL/tPLH propagation delay X1 to OUT divide-by-4 − 35 60 − 75 − 90 ns 4.5 Fig.7 S1 = VCC S2 = GND tPHL/tPLH propagation delay X1 to OUT divide-by-8 − 40 70 − 87 − 105 ns 4.5 Fig.7 S1 = VCC S2 = VCC tPLZ/tPHZ 3-state output disable time MR to OUT − 21 35 − 43 − 52 ns 4.5 Fig.8 tPZ 3-state output enable time MR to OUT − 16 30 − 37 − 45 ns 4.5 Fig.8 tPZH 3-state output enable time MR to OUT − 22 38 − 47 − 57 ns 4.5 Fig.8 tTHL/tTLH output transition time − 5 12 − 15 − 19 ns 4.5 Fig.7 tW clock pulse width X1, HIGH or LOW 10 6 − 12 − 15 − ns 4.5 Fig.7 tW master reset pulse width MR; LOW 16 8 − 20 − 24 − ns 4.5 Fig.9 trem removal time MR to X1 24 12 − 30 − 36 − ns 4.5 Fig.9 fmax maximum clock 50 pulse frequency 85 − 40 − 33 − MHz 4.5 Fig.7 Note to the 74HCT AC Characteristics 1. tPZH only applicable in the divide-by-1 mode and X1 must be HIGH. September 1993 10 see note 1 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A MBA331 24 handbook, halfpage gfs (mA/V) 20 R bias = 560 kΩ handbook, halfpage 16 VCC 12 0.47 µ F input output 100 µF 8 vi A io (f = 1 kHz) 4 GND MGA645 0 Fig.5 Fig.6 Test set-up for measuring forward transconductance gfs = dio/dvi at vo is constant (see also Fig.6); MR = HIGH. 0 1 2 3 4 5 6 VCC (V) Typical forward transconductance gfs as a function of the supply voltage Vcc at Tamb = 25 °C. 1/f max handbook, full pagewidth X1 INPUT V M (1) tW t PHL OUT OUTPUT t PLH V M (1) t THL t TLH MBA318 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the clock (X1) to output (OUT) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency. September 1993 11 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A tf handbook, full pagewidth tr 90 % MR INPUT V M (1) 10 % t PZL t PLZ OUTPUT LOW - to - OFF OFF - to - LOW V M (1) t PHZ t PZH 90 % OUTPUT HIGH - to - OFF OFF - to - HIGH MBA319 V M (1) outputs enabled outputs disabled outputs enabled (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the input MR to output OUT, 3-state enable and disable times. handbook, halfpage tW VM (1) MR INPUT t rem V M (1) X1 INPUT MBA323 (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the MR minimum pulse width and MR to X1 removal time. September 1993 12 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state 74HC/HCT6323A APPLICATION INFORMATION MBA347 40 handbook, halfpage −II (µA) VCC = 6 V 30 handbook, halfpage 5 6323A 20 MR 4.3 V 10 MBA348 2V 0 0 1 2 3 4 5 6 VI (V) The input pull-up current is used to create a power-on delay time at MR. Fig.11 Typical input pull-up current as a function of the input voltage (VI). Fig.10 Power-on reset. Table 1 Typical application values f (MHz) R2 (kΩ) 1 4.7 10 2.2 25 1 C1 (pF) C2 (pF) 47 to 68 MBA346 50 handbook, halfpage −II (µA) 40 Table 2 30 20 VI = 0 V 10 0 1 2 3 4 5 6 VCC (V) Fig.12 Typical input pull-up current as a function of the supply voltage (VCC). September 1993 13 47 to 68 33 33 Typical Application Values f (MHz) Rbias (kΩ) C1 (pF) 50 3.0 4.7 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state handbook, halfpage 74HC/HCT6323A handbook, halfpage MR (from logic) 7 MR (from logic) X1 7 X1 X2 R bias 22 to 37 pF 6 R bias 100 kΩ to 1 MΩ C1 X2 6 3 kΩ R2 2.2 kΩ C2 100 pF C1 1 to 10 pF (optional) MBA329 - 1 MBA328 - 1 Above 5 MHz replace R2 by a capacitor of half the value of C2. CL at which a crystal is specified (or adjusted) equals for this application C1 . C2/C1 + C2. Applicable for third overtone crystals (lower damping resistance at the third harmonic frequency) at typical 50 MHz. For lower frequencies extra load capacitors must be supplied, or increase bias resistor. Fig.13 Typical setup for a crystal oscillator operating in the fundamental mode (1 MHz to 25 MHz). Fig.14 Typical set-up for a crystal oscillator operating in the third overtone mode without the use of an inductor. September 1993 14 Philips Semiconductors Product specification Programmable ripple counter with oscillator; 3-state Typical Crystal Oscillator In Fig.13, R2 is the power limiting resistor. For starting and maintaining oscillation a minimum transconductance is necessary, so R2 should not be too large. A practical value for R2 is 2.2 kΩ. The oscillator has been designed to operate over a wide frequency spectrum, for quartz crystals operating in the fundamental mode and in the overtone mode. The circuit is a Pierce type oscillator and requires a minimum of external components. There are two on-chip capacitors, X1 and X2, of approximately 7 pF. Together with the stray and input capacitance the value becomes 12 pF for 8-pin SO packages. These values are convenient and make it possible to run the oscillator in the third overtone without external capacitors applied. If a certain frequency is chosen, the IC parameters, as forward transconductance, and the crystal parameters such as the motional resistances R1 (fundamental), R3 (third overtone) and R5 (fifth overtone), are of paramount importance. Also the values of the external components as Rs (series resistance) and the crystal load capacitances play an important role. Especially in overtone mode oscillations, Rb (bias resistance) and the load capacitance values are very important. September 1993 74HC/HCT6323A Considerations for Fundamental Oscillator: Considerations for Third-overtone Oscillator: In the fundamental oscillator mode, the Rb has only the function of biasing the inverter stage, so that it operates as an amplifier with a phase shift of approximately 180°. The value must be high, i.e. 100 kΩ up to 10 MΩ. The load capacitors C1 and C2, must have a value that is suitable for the crystal being used. The crystal is designed for a certain frequency having a specific load capacitance. C1 can be used to trim the oscillation frequency. The series resistance reduces the total loop gain. One function of it is therefore to reduce the power dissipation in the crystal. Rs also suppresses overtone oscillations and introduces a phase shift over a broad frequency range. This is of less concern provided Rs is not too high a value. In the overtone configuration, series resistance is no longer applied. This is essential otherwise the gain for third overtone can be too small for oscillation. A simple solution to suppress the fundamental oscillation, is to spoil the crystal fundamental activity. By dramatically reducing the value of the bias resistor of the inverting stage, and applying small load capacitors, it is possible to have an insufficient phase in the total loop for fundamental oscillation. However the phase for third overtone is good. It can be explained by the Rb × Cl time constant. During oscillation the crystal with the load capacitors cause a phase shift of 180°. Because Rb is parallel with the crystal (no Rs), Rb spoils the phase for fundamental. Rb × Cl must be of a value, that it is not spoiling the phase for third overtone too much. Because third overtone is a 3 times higher frequency than the fundamental, the Rb × Cl cannot 'maintain' the higher third overtone frequency, which results in a less spoiled overtone phase. Note A combination of a small load capacitor value and a small series resistance, may cause a third overtone oscillation. PACKAGE OUTLINES See “74HC/HCT/HCU/HCMOS Logic Package Outlines”. 15