19-3150; Rev 2; 10/05 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC Features The MAX5322 dual, 12-bit, serial-interface, digital-to-analog converter (DAC) provides bipolar ±5V to ±10V outputs from ±12V to ±15V analog power-supply voltages, or unipolar 5V to 10V outputs from a single 12V to 15V analog power-supply voltage. The MAX5322 features excellent linearity with both integral nonlinearity (INL) and differential nonlinearity (DNL) guaranteed to ±1 LSB (max). The device also features a fast 10µs to 0.5 LSB settling time, and a hardware-shutdown feature that reduces current consumption to 2.8µA. The output goes to midscale at power-up in bipolar mode (0V), and to zero scale at power-up in unipolar mode (0V). A clear input (CLR) asynchronously clears the DAC register and sets the outputs to 0V. The outputs can be asynchronously updated with the load DAC (LDAC) input. The device features a fast 10MHz SPI™-/QSPI™/MICROWIRE™-compatible serial interface that operates with 3V or 5V logic. Additional features include a serialdata output (DOUT) for daisy chaining and read-back functions. The MAX5322 requires external reference voltages of 2V to 5.25V and is available in a 28-pin SSOP package that operates over the extended (-40°C to +85°C) temperature range. ♦ Unipolar or Bipolar Output-Voltage Ranges Unipolar: 0 to +2 x VREF (Single or Dual Supply) Bipolar: -2 x VREF to +2 x VREF (Dual Supply) ♦ Guaranteed INL ≤ ±1 LSB (max) ♦ Guaranteed Monotonic: DNL ≤ ±1 LSB (max) ♦ 10µs Settling Time to 0.5 LSB ♦ Low 2.8µA Shutdown Current ♦ Fast 10MHz SPI-/QSPI-/MICROWIRE-Compatible Serial Interface ♦ Power-On Reset Sets DAC Output to 0V ♦ Schmitt Trigger Inputs for Direct Optocoupler Interface ♦ Serial-Data Output Allows Daisy-Chaining of Devices ♦ 28-Pin SSOP (8mm x 10mm) Ordering Information Applications Motor Control Industrial Process Controls Automatic Test Equipment (ATE) Analog I/O Boards Industrial Automation Data-Acquisition Systems MAX5322 General Description PART TEMP RANGE PIN-PACKAGE MAX5322EAI -40°C to +85°C 28 SSOP Functional Diagram 2R 2R SW2 REFA LDAC CLR 12-BIT DAC A SW1 A1 A2 INPUT REGISTERS 12 DAC REGISTERS DGND 2R SW6 12 12 REFB DIN SCLK CS UNI/BIPA UNI/BIPB SHDN DOUT VCC OUTA SW3 12 12-BIT DAC B SW4 2R SW5 SGNDA A3 16-BIT SHIFT REGISTER A4 2R DIGITAL POWER OUTB 2R SERIAL INTERFACE AND CONTROL 2R 2R MAX5322 ANALOG POWER SGNDB VSS VDD AGND SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX5322 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC ABSOLUTE MAXIMUM RATINGS VDD to AGND..........................................................-0.3V to +17V VSS to AGND ..........................................................-17V to +0.3V VDD to VSS ..........................................................................+34V VCC to DGND ...........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V SGND_ to AGND ...................................................-0.3V to +0.3V SCLK, DIN, CS, SHDN, UNI/BIP_, CLR, LDAC, DOUT to DGND ..........................-0.3V to (VCC + 0.3V) OUT_ to AGND.................................(VSS - 0.3V) to (VDD + 0.3V) REF_ to AGND..........................................................-0.3V to +6V Maximum Current into REF_ .............................................±10mA Maximum Current into Any Pin Excluding REF_...............±50mA Continuous Power Dissipation (TA = +70°C) 28-Pin SSOP (derate 9.5mW/°C above +70°C) ........761.9mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (DUAL SUPPLY) (VDD = +15V ±5%, VSS = -15V ±5%, VCC = +5V ±10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 2kΩ, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±1 LSB ±1 LSB STATIC ACCURACY Resolution N Integral Nonlinearity INL Differential Nonlinearity DNL Zero-Scale Error Zero-Scale Temperature Coefficient Gain Error Gain-Error Temperature Coefficient 12 Bits Guaranteed monotonic Bipolar, code = 800hex ±2 Unipolar, code = 000hex ±2 Bipolar 0.9 Unipolar 0.09 ppm FSR/°C Bipolar (output unloaded) ±2 Unipolar (output unloaded) ±2 Bipolar (output unloaded) 2 Unipolar (output unloaded) 2 LSB LSB ppm FSR/°C ANALOG OUTPUTS (OUTA, OUTB) Output Voltage Range (VSS + 1.5V) < VOUT < (VDD - 1.5V) Resistive Load to GND RLOAD Capacitive Load to GND CLOAD -2 x VREF +2 x VREF 2 kΩ 250 DC Output Resistance V pF 0.5 Ω 92 kΩ SGND INPUTS (SGNDA, SGNDB) Input Impedance REFERENCE INPUTS (REFA, REFB) Reference Voltage Input Range Input Resistance Reference Bandwidth 2 2.00 RREF Code = 555hex, worst-case code VREF = 200mVP-P + 5VDC 15 5.25 V 22 kΩ 200 kHz _______________________________________________________________________________________ ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC (VDD = +15V ±5%, VSS = -15V ±5%, VCC = +5V ±10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 2kΩ, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIPA, UNI/BIPB, CLR, LDAC) Input Voltage High VIH Input Voltage Low VIL Input Capacitance C Input Current (Note 1) +2.7V ≤ VCC ≤ +3.6V +4.5V ≤ VCC ≤ +5.5V 0.7 x VCC V 2.4 +2.7V ≤ VCC ≤ +3.6V 0.8 +4.5V ≤ VCC ≤ +5.5V 0.8 +2.7V ≤ VCC ≤ +3.6V 10 +4.5V ≤ VCC ≤ +5.5V 10 V pF 0 ≤ all digital inputs ≤ VCC, +2.7V ≤ VCC ≤ +3.6V ±1 0 ≤ all digital inputs ≤ VCC, +4.5V ≤ VCC ≤ +5.5V ±1 µA DIGITAL OUTPUT (DOUT) Output Voltage High VOH ISOURCE = 2mA Output Voltage Low VOL ISINK = 2mA VCC 0.5 V 0.4 V Tri-State Leakage Current 0.1 µA Tri-State Capacitance 10 pF 2.5 V/µs 10 µs DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time To ±0.5 LSB of full scale, code 000 to code FFF Digital Feedthrough CS = high, fSCLK = 10MHz, VOUT = 0V 10 nV-s DAC-to-DAC Crosstalk 2.5 nV-s Output-Noise Spectral Density at 10kHz 130 nV/√Hz POWER SUPPLIES Positive Analog-Supply Voltage VDD 10.80 15.75 V Negative Analog-Supply Voltage VSS -10.80 -15.75 V Positive Digital-Supply Voltage VCC 2.7 5.5 V Positive Analog-Supply Current IDD Output unloaded, VOUT = 0 2.8 8 mA Negative Analog-Supply Current ISS Output unloaded, VOUT = 0 -1.5 -8 mA Digital-Supply Current ICC All digital inputs = 0 or VCC 200 µA Power-Supply Rejection Ratio (Note 2) Shutdown Current PSRR Positive analog supply 0.0006 Negative analog supply 0.03 Positive analog supply 2.8 50 Negative analog supply 4 50 Digital supply 4 10 LSB/V µA _______________________________________________________________________________________ 3 MAX5322 ELECTRICAL CHARACTERISTICS (DUAL SUPPLY) (continued) MAX5322 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY) (VDD = +15V ±5%, VSS = 0V, VCC = +5V ±10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 10kΩ, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution N 12 Bits Integral Nonlinearity INL (Note 3) ±1 LSB Differential Nonlinearity DNL Guaranteed monotonic ±1 LSB ±2 Unipolar Zero-Scale Error Unipolar Zero-Scale Temperature Coefficient 0.09 Gain Error ±2 No load Gain-Error Temperature Coefficient No load LSB ppm FSR/°C LSB ppm FSR/°C 2 ANALOG OUTPUTS (OUTA, OUTB) Output Voltage Range +2 x VREF 0 Resistive Load to GND RLOAD Capacitive Load to GND CLOAD 10 kΩ 250 DC Output Resistance V pF 0.5 Ω 92 kΩ SGND INPUTS (SGNDA, SGNDB) Input Impedance REFERENCE INPUTS (REFA, REFB) Reference Voltage Input Range 2.00 Input Resistance Code = 555hex, worst-case code Reference Input Bandwidth VREF = 200mVP-P + 5VDC 15 5.25 V 22 kΩ 150 kHz DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIPA, UNI/BIPB, CLR, LDAC) Input Voltage High VIH Input Voltage Low VIL Input Capacitance CIN Input Current IIN +2.7V ≤ VCC ≤ +3.6V 0.7 x VCC +4.5V ≤ VCC ≤ +5.5V 2.4 V +2.7V ≤ VCC ≤ +3.6V 0.8 +4.5V ≤ VCC ≤ +5.5V 0.8 +2.7V ≤ VCC ≤ +3.6V 10 +4.5V ≤ VCC ≤ +5.5V 10 V pF 0 ≤ VIN ≤ VCC, +2.7V ≤ VCC ≤ +3.6V ±1 0 ≤ VIN ≤ VCC, +4.5V ≤ VCC ≤ +5.5V ±1 µA DIGITAL OUTPUT (DOUT) Output Voltage High VOH ISOURCE = 2mA Output Voltage Low VOL ISINK = 2mA Tri-State Leakage Current 4 VCC 0.5 V 0.4 0.1 _______________________________________________________________________________________ V µA ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC (VDD = +15V ±5%, VSS = 0V, VCC = +5V ±10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 10kΩ, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN Tri-State Capacitance TYP MAX UNITS 10 pF 2.5 V/µs 10 µs DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time To ±0.5 LSB of full scale Digital Feedthrough CS = high, fSCLK = 10MHz, VOUT = 0V 10 nV-s DAC-to-DAC Crosstalk 2.5 nV-s Output-Noise Spectral Density at 10kHz 130 nV/√Hz POWER SUPPLIES Positive Analog Supply Voltage VDD Negative Analog Supply Voltage VSS Positive Digital Supply Voltage VCC Positive Analog Supply Current IDD Output unloaded, VOUT = 0 Negative Analog Supply Current ISS Output unloaded, VOUT = 0 Digital Supply Current ICC All digital inputs = 0 or VCC 9 Power-Supply Rejection Ratio Shutdown Current 10.80 15.75 0 2.7 PSRR V V 5.5 V 2.5 8 mA -0.5 -8 mA 200 µA 0.001 LSB/V Analog supply 2.8 5 Digital supply 2.8 5 µA _______________________________________________________________________________________ 5 MAX5322 ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY) (continued) MAX5322 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC TIMING CHARACTERISTICS (VDD = +15V, VSS = -15V or 0V, VCC = +2.7V to +5.5V, AGND = DGND = SGND_ = 0, VREF_ = 5V, RLOAD = 2kΩ, ,CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP SCLK Frequency SCLK Clock Period tCP SCLK Pulse-Width High tCH SCLK Pulse-Width Low tCL CS Fall to SCLK Rise Setup Time tCSS SCLK Rise to CS Rise Hold Time tCSH MAX UNITS 10 MHz 100 ns For nondaisy-chain use 45 ns For nondaisy-chain use 45 For daisy-chain use ns 98 40 +2.7V ≤ VCC ≤ +3.6V 15 +4.5V ≤ VCC ≤ +5.5V 10 ns ns DIN Setup Time tDS 20 ns DIN Hold Time tDH 10 ns LDAC Pulse Width tLD 50 ns CS Rise to LDAC Low Setup Time tLDS SCLK Fall to DOUT Valid Propagation Delay tDO1 SCLK Rise to CS Fall Delay tCS0 CS Low to DOUT Valid Time tCSE CS High to DOUT Disabled Time tCSD CS Rise to SCLK Rise Hold Time tCS1 CS Pulse-Width High tCSW CLR Pulse-Width Low tCLR +2.7V ≤ VCC ≤ +3.6V 100 +4.5V ≤ VCC ≤ +5.5V 50 CLOAD = 20pF, +2.7V ≤ VCC ≤ +3.6V 100 CLOAD = 20pF, +4.5V ≤ VCC ≤ +5.5V 80 10 CLOAD = 20pF 120 50 +2.7V ≤ VCC ≤ +3.6V 200 +4.5V ≤ VCC ≤ +5.5V 100 50 _______________________________________________________________________________________ ns ns 120 Note 1: Output unloaded, digital inputs = VCC or DGND. Note 2: ∆VDD = 15.5V to 14.5V, ∆VSS = -15.5V to -14.5V, input code = 14hex to FFFhex Note 3: Accuracy is guaranteed from code 14hex to FFFhex 6 ns ns ns ns ns ns ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC 0.4 0.3 0.4 0.3 0.2 0.1 0.1 0.1 -0.1 DNL (LSB) 0.2 INL (LSB) 0.2 0 0 -0.1 0 -0.1 -0.2 -0.2 -0.2 -0.3 -0.3 -0.3 -0.4 -0.4 -0.4 -0.5 -0.5 -0.5 1024 2048 4096 3072 2.0 2.5 INPUT CODE (DECIMAL) 3.0 3.5 4.0 4.5 5.0 DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE 1024 0.3 4096 3072 BIPOLAR DNL vs. TEMPERATURE 0.5 MAX5322 toc04 0.4 2048 INPUT CODE (DECIMAL) BIPOLAR INL vs. TEMPERATURE 0.5 WORST CASE 0.4 0.5 WORST CASE 0.4 INL (LSB) 0.1 0 -0.1 -0.2 DNL (LSB) 0.3 0.2 0.2 0.1 0.3 0.2 0 -0.3 0.1 -0.1 -0.4 -0.5 0 -0.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40 -15 10 35 60 REFERENCE VOLTAGE (V) TEMPERATURE (°C) UNIPOLAR SETTLING TIME (CLOAD = 250pF, RLOAD = 10kΩ) BIPOLAR SETTLING TIME (CLOAD = 250pF, RLOAD = 2kΩ) A 5V/div CS CS 2V/div 10 35 60 85 BIPOLAR MAJOR CARRY GLITCH ENERGY, CLOAD = 250pF MAX5322 toc09 CS VOUT 100mV/div VOUT VOUT 0 0 t = 10.0µs/div t = 10.0µs/div A: CS, 5.0V/div B: OUT, 2.0V/div -15 TEMPERATURE (°C) 5V/div B 5V/div B -40 85 MAX5322 toc08 MAX5322 toc07 A 5V/div 0 5.5 REFERENCE VOLTAGE (V) MAX5322 toc05 0 MAX5322 toc03 0.3 0.5 MAX5322 toc02 0.4 INL (LSB) 0.5 MAX5322 toc01 0.5 DNL (LSB) DIFFERENTIAL NONLINEARITY vs. INPUT CODE INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE MAX5322 toc06 INTERGRAL NONLINEARITY vs. INPUT CODE t = 4.00µs/div A: CS, 5.0V/div B: OUT, 5.0V/div _______________________________________________________________________________________ 7 MAX5322 Typical Operating Characteristics (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) 2.5 MAX5322 toc11 50 CS 5V/div BIPOLAR ZERO-SCALE VOLTAGE vs. TEMPERATURE UNIPOLAR ZERO-SCALE VOLTAGE vs. TEMPERATURE MAX5322 toc10 CODE = 0X014hex 49 VOUT (mV) VOUT (mV) VOUT 100mV/div 46 CODE = 0X800hex 2.0 48 47 MAX5322 toc12 BIPOLAR MAJOR CARRY GLITCH CLOAD = 10pF 45 44 1.5 1.0 0.5 43 42 9.998 MAX5322 toc13 CODE = 0XFFFhex 9.999 35 60 85 -40 CODE = 0XFFFhex CODE = 0X000hex -9.993 -9.994 9.995 -9.995 9.995 9.993 -9.997 9.992 10 35 60 -9.998 -40 85 -15 10 35 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) UNIPOLAR SUPPLY CURRENT vs. SUPPLY VOLTAGE BIPOLAR POSITIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE BIPOLAR NEGATIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE 4 IDD (mA) 3 0 3 VDD = 15V -1 -2 2 2 -3 1 1 -4 0 0 11.8 12.8 13.8 VDD (V) 14.8 15.8 MAX5322 toc17b 4 VSS = -15V ISS (mA) VSS = 0V MAX5322 toc17a 5 MAX5322 toc16 5 10.8 85 -9.992 -9.996 -15 60 NEGATIVE BIPOLAR FULL-SCALE VOLTAGE vs. TEMPERATURE 9.994 -40 35 POSITIVE BIPOLAR FULL-SCALE VOLTAGE vs. TEMPERATURE 9.996 9.994 10 TEMPERATURE (°C) VOUT (V) 9.997 -15 TEMPERATURE (°C) 9.996 VOUT (V) VOUT (V) 10 9.997 9.998 8 -15 MAX5322 toc15 UNIPOLAR FULL-SCALE VOLTAGE vs. TEMPERATURE 10.000 0 -40 MAX5322 toc14 t = 4.00µs/div IDD (mA) MAX5322 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC -5 10.8 11.8 12.8 13.8 VDD (V) 14.8 15.8 -15.8 -14.8 -13.8 -12.8 VSS (V) _______________________________________________________________________________________ -11.8 -10.8 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC 4.0 -1.0 -1.5 3.0 3.0 -2.0 2.5 ISS (mA) 3.5 2.5 -2.5 2.0 2.0 -3.0 1.5 1.5 -3.5 1.0 1.0 -4.0 0.5 0.5 -4.5 0 0 -5.0 -15 10 35 60 85 -40 -15 10 35 60 85 -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) BIPOLAR SHUTDOWN CURRENT vs. TEMPERATURE UNIPOLAR SHUTDOWN CURRENT vs. TEMPERATURE UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT IDD 2 1 0 ISS CODE = FFFhex 10.000 9.995 3 9.990 IDD 2 1 9.985 9.980 9.975 9.970 0 -2 85 MAX5322 toc22A MAX5322 toc21 ICC 10.005 VOUT (V) 3 -1 4 SHUTDOWN CURRENT (µA) ICC 4 5 MAX5322 toc20 5 9.965 -1 -3 10 35 60 -40 85 -15 10 35 60 9.960 85 0 8 12 16 TEMPERATURE (°C) IOUT (mA) UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT -9.965 0.115 CODE = 000hex -9.970 10.005 9.995 -9.975 0.095 0.085 9.990 -9.980 VOUT (V) VOUT (V) 0.105 -9.985 -9.990 0.075 9.985 9.980 9.975 0.065 -9.995 9.970 0.055 -10.000 9.965 0.045 -10.005 0.2 0.4 0.6 IOUT (mA) 0.8 1.0 1.2 CODE = FFFhex 10.000 20 MAX5322 toc23B CODE = 014hex 0.125 0 4 TEMPERATURE (°C) MAX5322 toc23A 0.135 -15 MAX5322 toc22B -40 VOUT (V) 0 -0.5 3.5 -40 SHUTDOWN CURRENT (µA) 4.5 IDD (mA) IDD (mA) 4.0 BIPOLAR NEGATIVE SUPPLY CURRENT vs. TEMPERATURE MAX5322 toc19A VSS = 0V 4.5 5.0 MAX5322 toc18 5.0 BIPOLAR POSITIVE SUPPLY CURRENT vs. TEMPERATURE MAX5322 toc19B UNIPOLAR SUPPLY CURRENT vs. TEMPERATURE 9.960 -20 -16 -12 -8 IOUT (mA) -4 0 0 4 8 12 16 20 IOUT (mA) _______________________________________________________________________________________ 9 MAX5322 Typical Operating Characteristics (continued) (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) BIPOLAR REFERENCE INPUT RESISTANCE vs. INPUT CODE 70 60 50 40 30 90 80 70 60 50 40 20 10 10 0 0 1024 2048 3072 -5 -10 30 20 0 0 RESPONSE (dB) 80 5 MAX5322 toc25 REF INPUT RESISTANCE (kΩ) 90 100 REF INPUT RESISTANCE (kΩ) MAX5322 toc24 100 UNIPOLAR REFERENCE INPUT BANDWIDTH MAX5322 toc26 UNIPOLAR REFERENCE INPUT RESISTANCE vs. INPUT CODE -15 200mVP-P INTO REF_ -20 0 4096 1024 2048 4096 3072 INPUT CODE (DECIMAL) INPUT CODE (DECIMAL) BIPOLAR REFERENCE INPUT BANDWIDTH UNIPOLAR STARTUP RESPONSE, CLOAD = 10pF 0.01 MAX5322 toc27 0 0.1 1 10 MAX5322 toc28B 20V/div VDD VCC 5V/div VCC 5V/div VREF 5V/div VREF 2V/div VOUT 1V/div VOUT 5V/div -5 -10 -15 200mVP-P INTO REF_ -20 0.01 0.1 1 10 100 t = 10.0µs/div 1000 t = 10.0µs/div FREQUENCY (kHz) BIPOLAR STARTUP RESPONSE, CLOAD = 10pF BIPOLAR STARTUP RESPONSE, CLOAD = 230pF MAX5322 toc29A 20V/div 5V/div VDD VCC 5V/div VDD VCC 10V/div VSS 10V/div VSS 2V/div VOUT 1V/div VOUT t = 10.0µs/div 10 MAX5322 toc29B 20V/div 1000 UNIPOLAR STARTUP RESPONSE, CLOAD = 230pF VDD 20V/div 100 FREQUENCY (kHz) MAX5322 toc28A 5 RESPONSE (dB) MAX5322 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC t = 10.0µs/div ______________________________________________________________________________________ ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC UNIPOLAR RELEASE FROM HARDWARE SHUTDOWN RESPONSE BIPOLAR RELEASE FROM HARDWARE SHUTDOWN RESPONSE MAX5322 toc30 UNIPOLAR SOFTWARE-SHUTDOWN RESPONSE MAX5322 toc31 VOUT MAX5322 toc32A 5V/div CS VOUT 5V/div 5V/div VSHDN VSHDN 5V/div VOUT 2V/div 2V/div t = 100µs/div t = 100µs/div BIPOLAR SOFTWARE-SHUTDOWN RESPONSE t = 40.0µs/div DAC-TO-DAC CROSSTALK MAX5322 toc33 MAX5322 toc32B 5V/div 1mV/div CS OUTB 0V 5V/div 10V/div VOUT OUTA t = 40.0µs/div 0V t = 100µs/div ______________________________________________________________________________________ 11 MAX5322 Typical Operating Characteristics (continued) (VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25°C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) MAX5322 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC Pin Description PIN NAME 1, 2, 13–16, 27, 28 N.C. 3 UNI/BIPB 4 SHDN Active-Low Shutdown Input. Pulling SHDN low forces the DAC buffers into high impedance. Drive SHDN high for normal operation. 5 LDAC Active-Low Load DAC Input. DAC A and DAC B are updated with information in the input register on the LDAC falling edge. 6 CLR Active-Low Asynchronous Clear DAC Input. Pulling CLR low clears all DACs and input registers; resets all outputs to zero. 7 DGND 8 VCC 9 DOUT 10 SCLK 11 DIN Serial-Data Input. Data is clocked in on the rising edge of SCLK. 12 CS Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. 17 UNI/BIPA 12 18 OUTA 19 SGNDA 20 REFA 21 VDD 22 REFB 23 AGND 24 SGNDB 25 OUTB 26 VSS FUNCTION No Connection. Not internally connected. DAC B Output-Mode Selection Input. Selects unipolar or bipolar output. Logic high = unipolar, logic low = bipolar. In unipolar mode, the analog output range is 0 to 2 x VREF. In bipolar mode, the analog output range is (-2 x VREF) to (+2 x VREF). Digital Ground Digital Power Input. Connect VCC to a +2.7V to +5.5V power supply. Bypass VCC to DGND with a 10µF and 0.1µF capacitor in parallel as close to the device as possible. Serial-Data Output. Data is clocked out on SCLK’s falling edge. DOUT is high impedance when CS is high. Data shifted into DIN appears at DOUT 16.5 clock cycles later. Serial-Clock Input. SCLK clocks data in and out of the serial interface. DAC A Output-Mode Selection. Selects unipolar or bipolar output. Logic high = unipolar, logic low = bipolar. In unipolar mode, the analog output range is 0 to 2 x VREF. In bipolar mode, the analog output range is (-2 x VREF) to (+2 x VREF). DAC A Output DAC A Sense Ground. Connect to AGND. Reference Input for DAC A Positive Analog-Power Input. Connect VDD to a +10.8V to +15.75V power supply. Bypass VDD to AGND with a 10µF and 0.1µF capacitor in parallel as close to the device as possible. DAC B Reference Input Analog Ground DAC B Sense Ground. Connect to AGND. DAC B Output Negative Analog-Power Input. For single-supply operation, connect VSS to AGND. For dual-supply operation, connect VSS to a -10.8V to -15.75V power supply and bypass VSS to AGND with a 10µF and 0.1µF capacitor in parallel, as close to the device as possible. ______________________________________________________________________________________ ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC The MAX5322 dual, 12-bit DAC operates from either single or dual analog supplies. Dual ±12V to ±15V power supplies provide bipolar ±5V to ±10V outputs, or unipolar 0V to 10V outputs. Single 12V to 15V analog power supplies only provide unipolar 0 to 10V outputs. The reference inputs accept voltages from 2V to 5.25V. The DAC features INL and DNL less than ±1 LSB (max), a fast 10µs settling time, and a hardware shutdown mode that reduces current consumption to 2.8µA. The device features a 10MHz SPI-/QSPI-/MICROWIRE-compatible serial interface that operates with 3V or 5V logic, an asynchronous load input, and a serial-data output. The device offers a CLR that sets the DAC outputs to 0V. Figure 1 shows the functional diagram of the MAX5322. Serial Interface An SPI-/QSPI-/MICROWIRE-compatible serial interface allows complete control of the DAC through a 16-bit control word. The first 4 bits form the control bits that determine register loading and software shutdown functions. The last 12 bits form the DAC data. The 16bit word is entered MSB first. Table 1 shows the serial-data control-word format. Table 2 shows the interface commands. The MAX5322 can be programmed while in shutdown. The serial interface contains five registers: a 16-bit shift register, two 12-bit input registers, and two 12-bit DAC registers (Figure 1). The shift register accepts data from the serial interface. The input registers act as holding registers for data going to the DAC registers Table 1. Control-Word Format CONTROL BITS DATA BITS MSB LSB C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 2. Serial-Interface Programming Commands 16-BIT SERIAL WORD CONTROL BITS FUNCTION DATA BITS C3 C2 C1 C0 D11–D0 0 0 0 0 XXXXXXXXXXXX No operation (NOP). 1 12-bit DAC data Load both DAC registers and both input registers from the shift register. (Start both DACs with new data.) 0 0 0 0 0 1 0 12-bit DAC data Load input register A from the shift register; DAC registers are unchanged. 0 0 1 1 12-bit DAC data Load input register B from the shift register; DAC registers are unchanged. 0 1 0 0 12-bit DAC data Load DAC register A and input register A from the shift register. 0 1 0 1 12-bit DAC data Load DAC register B and input register B from the shift register. 0 1 1 0 XXXXXXXXXXXX Update DAC register A from input register A (no data sent). 0 1 1 1 XXXXXXXXXXXX Update DAC register B from input register B (no data sent). 1 0 0 0 XXXXXXXXXXXX Shut down DAC A (provided SHDN = 1). 1 0 0 1 XXXXXXXXXXXX Shut down DAC B (provided SHDN = 1). 1 0 1 0 XXXXXXXXXXXX Update both DAC registers from their respective input registers. (Start both DACs with data previously stored in the input register.) 1 0 1 1 XXXXXXXXXXXX Shut down both DACs (provided SHDN = 1). 1 1 0 0 XXXXXXXXXXXX Power up DAC A (no change to any registers). 1 1 0 1 XXXXXXXXXXXX Power up DAC B (no change to any registers). 1 1 1 0 XXXXXXXXXXXX Power up both DACs (no change to any registers). 1 1 1 1 XXXXXXXXXXXX Not used. X = Don’t care. Note: The DACs can be programmed in shutdown mode. ______________________________________________________________________________________ 13 MAX5322 Detailed Description MAX5322 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC DAC Architecture and isolate the shift register from the DAC registers. The DAC registers control the DAC ladder and thus the output voltage. Any update to a DAC register updates the respective output voltage. Data in the shift register is transferred to the input registers during the appropriate software command only. Data in the input registers is transferred to the DAC registers in two ways: using the software command, or through external logic control using the asynchronous load input (LDAC). Table 2 shows the software commands that transfer the data from the shift register to the input and/or DAC registers. The CLR, an external logic control, asynchronously forces all outputs to 0V, in both unipolar and bipolar modes. Interface timing is shown in Figures 2 and 3. The MAX5322 uses an inverted DAC ladder architecture to convert the digital input into an analog output voltage. The digital input controls weighted switches that connect the DAC-ladder nodes to either REFA (REFB) or GND (Figure 4). The sum of the weights produces the analog equivalent of the digital-input word and is then buffered at the output. External Reference and Transfer Functions Connect an external reference of 2V to 5.25V to REFA and REFB. Set the output voltage range with the reference and the input code by using the equations below. Unipolar output voltage: Wait a minimum of 100ns after CS goes high before implementing LDAC or CLR. If either of these logic inputs activates during a data transfer, the incoming data is corrupted and needs to be reloaded. For software control only, tie LDAC and CLR high. VOUT _ UNI = LSBUNI × CODE COMMAND EXECUTED CS SCLK 1 DIN C3 8 C2 C1 C0 D11 D10 D9 D8 9 D7 16 D6 D5 D4 D3 D2 D1 (1) D0 Figure 2. Serial-Interface Signals tCSW CS tCSS tCS0 tCP tCSH tCS1 SCLK tCH tDS DIN tCL tDH LSB MSB tCSE tDO1 tCSD DOUT tLDS tLD LDAC Figure 3. Serial-Interface Timing Diagram 14 ______________________________________________________________________________________ ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC LSBUNI = This configuration channels the DAC output through two output stages to generate the ±2 x VREF output swing. The first amplifier generates the ±VREF voltage range and the second amplifier gains it up by two. When configured for bipolar operation, the MAX5322 must be driven with dual ±12V to ±15V power supplies. With UNI/BIPA (UNI/BIPB) forced high, switches SW1 (SW4) and SW2 (SW5) are open and SW3 (SW6) is closed. This configuration channels the DAC output through only a single gain stage to generate a 0 to 2 x VREF output swing. 2 × VREF 212 Bipolar output voltage: VOUT _ BIP = (LSBBIP × CODE) − (2 × VREF ) where: LSBBIP = 4 × VREF 212 where VOUT_UNI is the unipolar output voltage, VOUT_BIP is the bipolar output voltage, LSBUNI is the unipolar LSB step size, LSBBIP is the bipolar LSB step size, VREF is the reference voltage, and CODE is the decimal equivalent of the binary, 12-bit, DAC input code. In either case, a 000hex input code produces the minimum output (-2 x VREF for bipolar and zero for unipolar), an 800hex input code produces the midscale output (zero for bipolar and VREF for unipolar), and a FFFhex input code produces the full-scale output (2 x VREF for bipolar and unipolar). Output Amplifiers The output-amplifier section can be configured as either unipolar or bipolar by the UNI/BIP logic input. With UNI/BIPA (UNI/BIPB) forced low, SW1 (SW4) and SW2 (SW5) in Figure 1 are closed, and SW3 (SW6) is open. Daisy-Chaining SPI-/QSPI-/MICROWIRE-compatible devices can be daisy-chained to reduce I/O lines from the host controller (Figure 7). Daisy-chain devices by connecting the DOUT of one device to the DIN of the next, and connect the SCLK of all devices to a common clock. Data is shifted out of DOUT 16.5 clock cycles after it is shifted into DIN, and is available on the rising edge of the 17th clock cycle. The SPI-/QSPI-/MICROWIRE-compatible serial interface normally works at up to 10MHz, but must be slowed to 6MHz if daisy-chaining. DOUT is high impedance when CS is high. Shutdown Shutdown is controlled by software commands or by the SHDN logic input. The SHDN logic input may be implemented at any time. The SPI-/QSPI-/MICROWIRE-compatible serial interface remains fully functional, and the device is programmable while shutdown. When shut down, the MAX5322 supply current reduces to 2.8µA 2R R 2R R MAX5322 R SW2 2R 2R 2R 2R 2R SW1 OUTA D0 1 0 D1 1 0 D10 1 0 D11 1 SW3 2R 0 REFA 2R AGND SGNDA DAC REGISTER A UNI/BIPA CONTROL LOGIC Figure 4. Basic Inverted DAC Ladder ______________________________________________________________________________________ 15 MAX5322 where: (max), DOUT is high impedance, and OUTA and OUTB are pulled to SGNDA and SGNDB, respectively, through the internal feedback resistors of the output amplifier (Figure 1). When coming out of shutdown, or during device power-up, allow 350µs for the output to stabilize. Applications Information Power Supplies A single supply of +12V to +15V is required to realize an output swing of 0 to 10V. A dual supply of ±12V to ±15V is required to realize an output swing of ±10V, and allows unipolar, 0 to +10V output if UNI/BIP_ is forced high. A +3V to +5V digital power supply and two +2.000V to +5.250V external reference voltages are also required. Always bring up the reference voltages last; the other power supplies do not require sequencing. Power-Supply Bypassing and Ground Management Bypass VDD and VSS with 1.0µF and 0.1µF capacitors to AGND, and bypass VCC with a 1.0µF and 0.1µF capacitors to DGND. Minimize trace lengths to reduce inductance. Digital and AC transient signals on AGND or DGND can create noise at the output. Connect AGND and DGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane or star connect all ground return paths back to AGND. Carefully lay out the traces between channels to reduce AC cross coupling and crosstalk. Wire-wrapped boards, sockets, and breadboards are not recommended. Table 3. Output Voltage as Input Code Examples BINARY DAC CODE ANALOG OUTPUT LSB UNIPOLAR (UNI/BIP_ = HIGH) BIPOLAR (UNI/BIP_ = LOW) +2 x VREF (4095 / 4096) +2 x VREF (2047 / 2048) 1000 0000 0001 +2 x VREF (2049 / 4096) +2 x VREF (1 / 2048) 1000 0000 0000 +2 x VREF (2048 / 4096) = VREF 0 0111 1111 1111 +2 x VREF (2047 / 4096) -2 x VREF (1 / 2048) 0000 0000 0001 +2 x VREF (1 / 4096) -2 x VREF (2047 / 2048) 0000 0000 0000 0 -2 x VREF (2048 / 2048) = -2 x VREF 1111 1111 1111 2 x VREF 4096 1 LSB = 4095 4094 4093 4092 2 x VREF 2049 2048 2047 +2047 +2046 +2045 +2044 +1 0 -1 3 2 1 -2045 0 -2048 -2046 Figure 5. Unipolar Transfer Function FFC FFD FFE FFF 801 800 7FF 000 001 002 003 FFC FFD FFE FFF 801 800 7FF 000 001 002 003 -2047 hex DIGITAL INPUT CODE (LSB) 16 4 x VREF 4096 4 x VREF 1 LSB = ANALOG OUTPUT VOLTAGE (LSB) MSB ANALOG OUTPUT VOLTAGE (LSB) MAX5322 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC hex DIGITAL INPUT CODE (LSB) Figure 6. Bipolar Transfer Function ______________________________________________________________________________________ ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322 SCLK CS CS CS CS TO OTHER SERIAL DEVICES MAX5322 MAX5322 SCLK DIN MAX5322 SCLK DOUT DIN DIN SCLK DOUT DIN DOUT Figure 7. Daisy-Chaining Devices Pin Configuration Chip Information TRANSISTOR COUNT: 5914 PROCESS: BiCMOS TOP VIEW N.C. 1 28 N.C. N.C. 2 27 N.C. UNI/BIPB 3 26 VSS SHDN 4 25 OUTB LDAC 5 CLR 6 24 SGNDB MAX5322 DGND 7 23 AGND 22 REFB VCC 8 21 VDD DOUT 9 20 REFA SCLK 10 19 SGNDA DIN 11 18 OUTA CS 12 17 UNI/BIPA N.C. 13 16 N.C. N.C. 14 15 N.C. SSOP ______________________________________________________________________________________ 17 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) 2 SSOP.EPS MAX5322 ±10V, Dual, 12-Bit, Serial, Voltage-Output DAC 1 INCHES E H MILLIMETERS DIM MIN MAX MIN MAX A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 B 0.010 0.015 0.25 0.38 C 0.20 0.09 0.004 0.008 SEE VARIATIONS D E e 0.205 0.212 0.0256 BSC 5.20 MILLIMETERS INCHES D D D D D 5.38 MIN MAX MIN MAX 0.239 0.239 0.278 0.249 0.249 0.289 6.07 6.07 7.07 6.33 6.33 7.33 0.317 0.397 0.328 0.407 8.07 10.07 8.33 10.33 N 14L 16L 20L 24L 28L 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.025 0∞ 0.037 8∞ 0.63 0∞ 0.95 8∞ N A C B e L A1 D NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. 21-0056 REV. C 1 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.