AGERE LCK4801

Preliminary Data Sheet
July 2001
LCK4801
Low-Voltage HSTL Differential Clock
General
Features
The LCK4801 is a low-voltage, 3.3 V HSTL
differential clock synthesizer. The LCK4801 supports
two differential HSTL output pairs with frequencies
from 336 MHz to 1 GHz. The clock is designed to
support single and multiple processor systems that
require HSTL differential inputs. The LCK4801
contains a fully integrated PLL (phase-locked loop)
which multiplies the HSTL_CLK or PECL_CLK input
frequency to match individual processor clock
frequencies. The PLL can be bypassed so that the
PCLK outputs are fed from the HSTL_CLK or
PECL_CLK input for test purposes. All outputs are
powered from a 2 V external supply to reduce onchip power consumption. All outputs are HSTL. The
PLL can operate in the internal feedback mode, or in
the external feedback mode for board level
debugging applications.
■
Two fully selectable clock inputs.
■
Fully integrated PLL.
■
336 MHz to 1 GHz output frequencies.
■
HSTL outputs.
■
HSTL and LVPECL reference clocks.
■
32-pin TQFP package.
Description
PCLK0_EN (PULL-UP)
PCLK1_EN (PULL-UP)
TESTM (PULL-UP)
PLLREF_EN (PULL-UP)
REF_SEL (PULL-UP)
1
HSTL_CLK (PULL-UP)
HSTL_CLK (PULL-UP)
0
0
/M
PECL_CLK (PULL-UP)
PECL_CLK (PULL-UP)
(PULL-UP)
EXTFB_IN (HSTL)
PLL
1
0
PCLK0
1
PCLK0 (HSTL)
PCLK1
0
PCLK1 (HSTL)
1
/N
(PULL-DOWN)
EXTFB_OUT
EXTFB_EN (PULL-UP)
EXTFB_OUT (HSTL)
SEL[4:0] (PULL-UP)
DECODE
RESET (PULL-UP)
PLL_BYPASS (PULL-UP)
2274.a (F)
Figure 1. LCK4801 Logic Diagram
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
PLLREF_EN
VDDHSTL
PCLK0
PCLK0
PCLK1
PCLK1
VDDHSTL
VSS
PLL_BYPASS
Description (continued)
24
25
23
22
21
20
19
18
17
16
EXTFB_OUT
VDDHSTL
SEL[3]
28
13
EXTFB_IN
SEL[2]
29
12
EXTFB_IN
SEL[1]
30
11
EXTFB_EN
SEL[0]
31
10
PECL_CLK
9
PECL_CLK
32
1
VDDD
VDDA
2
3
4
5
6
7
8
HSTL_CLK
14
HSTL_CLK
27
REF_SEL
SEL[4]
PCLK1_EN
EXTFB_OUT
PCLK0_EN
15
VSS
26
TESTM
RESET
2275 (F)
Figure 2. 32-Pin TQFP
2
Agere Systems Inc.
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Pin Information
Table 1. Pin Description
Pin Number
Pin Name
I/O 1
Type
1
VDDD
P
Power Supply
3.3 V power supply.
2
TESTM
I
LVCMOS
M divider test pins.
3
VSS
G
Ground
Digital ground.
4
PCLK0_EN
I
LVCMOS
PCLK0 enable.
5
PCLK1_EN
I
LVCMOS
PCLK1 enable.
6
REF_SEL
I
LVCMOS
Selects the PLL input reference clock.
7
HSTL_CLK
I
Differential HSTL
PLL reference clock input.
8
HSTL_CLK
I
Differential HSTL
PLL reference clock input.
9
PECL_CLK
I
Differential LVPECL PLL reference clock input.
10
PECL_CLK
I
Differential LVPECL PLL reference clock input.
11
EXTFB_EN
I
LVCMOS
12
EXTFB_IN
I
Differential HSTL
External feedback input.
13
EXTFB_IN
I
Differential HSTL
External feedback input.
14
VDDHSTL
P
Power Supply
15
EXTFB_OUT
O
Differential HSTL
External feedback output clock.
16
EXTFB_OUT
O
Differential HSTL
External feedback output clock.
17
VDDHSTL
P
Power Supply
18
PCLK1
O
Differential HSTL
Output clock 1.
19
PCLK1
O
Differential HSTL
Output clock 1.
20
PCLK0
O
Differential HSTL
Output clock 0.
21
PCLK0
O
Differential HSTL
Output clock 0.
22
VDDHSTL
P
Power Supply
23
PLLREF_EN
I
LVCMOS
PLL reference enable.
24
PLL_BYPASS
I
LVCMOS
Input signal PLL bypass.
25
VSS
P
Ground
26
RESET
I
LVCMOS
PLL bypass reset (for test use).
27
SEL[4]
I
LVCMOS
Selection of input and feedback frequency.
28
SEL[3]
I
LVCMOS
Selection of input and feedback frequency.
29
SEL[2]
I
LVCMOS
Selection of input and feedback frequency.
30
SEL[1]
I
LVCMOS
Selection of input and feedback frequency.
31
SEL[0]
I
LVCMOS
Selection of input and feedback frequency.
32
VDDA
P
Power Supply
3.3 V filtered for PLL (PLL power supply).
Description
External feedback enable.
Output buffers power supply.
Output buffers power supply.
Output buffers power supply.
Analog ground for PLL.
1. P = power, I = input, G = ground, O = output.
Agere Systems Inc.
3
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Pin Information (continued)
Table 2. Frequency Selection
Selection
4
Input
Divide
Feedback
Divide
PCLK (MHz)
for Given Input Frequency (MHz)
4
3
2
1
0
M
N
70
100
120
125
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
336
350
364
378
392
406
420
434
448
462
476
490
504
518
532
546
560
564
588
602
616
630
644
658
672
686
700
714
728
742
756
770
480
500
520
540
560
580
600
620
640
660
680
700
720
740
760
780
800
820
840
860
880
900
920
940
960
980
1000
NA
NA
NA
NA
NA
576
600
624
648
672
696
720
744
768
792
816
840
864
888
912
936
960
984
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
600
625
650
675
700
725
750
775
800
825
850
875
900
925
950
975
1000
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Agere Systems Inc.
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Pin Information (continued)
Table 3. Function Control
Control Pin
REF_SEL
0
1
HSTL_CLK.
PECL_CLK.
M divider test mode enabled.
Reference fed to bypass MUX.
PLLREF_EN
Disable the input to the PLL and reset
the M divider.
Enable the input to the PLL.
PLL_BYPASS
Outputs fed by input reference or M
divider.
Outputs fed by VCO.
EXTFB_EN
External feedback enabled.
Internal feedback enabled.
PCLK0_EN
PCLK0 = low, PCLK0 = high.
PCLK0 = high, PCLK0 = low.
PCLK1_EN
PCLK1 = low, PCLK1 = high.
PCLK1 = high, PCLK1 = low.
RESET
Resets feedback N divider.
Feedback enabled.
SEL[4:0]
See Table 2 on page 4.
See Table 2 on page 4.
TESTM
Absolute Maximum Characteristics
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are
absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in
excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for
extended periods can adversely affect device reliability.
Table 4. Absolute Maximum Ratings
Parameter
Power Supply
Input Voltage
Write Current
Storage Temperature
Agere Systems Inc.
Symbol
Min
Typical
Max
Unit
VDDD/VDDA
VDDHSTL
VIN
IIN
TS
–0.5
–0.5
–0.5
–1
–50
—
—
—
—
—
4.4
4.4
VDDD + 0.3
1
150
V
V
mA
°C
5
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Electrical Characteristics
Table 5. dc Characteristics
VDDA = VDDD = 3.3 V ± 5%, VDDHSTL = 1.7 V—2.1 V, TA = 0 °C—70 °C.
Symbol
Description
Min
Typ
Max
Unit
Condition
VIH
Input High Voltage
2.0
—
VDDD
V
LVCMOS
VIL
Input Low Voltage
0.0
—
0.8
V
LVCMOS
1
VCMR
Input High Voltage
1
—
VDDD – 0.3
V
LVPECL
VPP
Input Low Voltage1
0.5
—
1
V
LVPECL2
VIN (dc)
dc Input Signal Voltage
–0.3
—
1.45
V
HSTL3
VDIF (dc)
dc Differential Input
Voltage
0.4
—
1.75
V
HSTL4
VCM (dc)
dc Common Mode Input
Voltage
0.4
—
1.0
V
HSTL5
VOH
Output High Voltage
VX + 0.3
VX + 0.5
1.4
V
HSTL6,1
VOL
Output Low Voltage
0
VX – 0.5
VX – 0.3
V
HSTL6
IDDI
Core Supply Current
—
140
mA
—
IDDA
PLL Supply Current
—
15
20
mA
—
IDDO
Output Supply Current
—
150
—
mA
—7
ThetaJA
Junction to Ambient
Thermal Resistance
—
53
—
°C/W
—8
1. dc levels will vary 1:1 with VDDD.
2. VPP characteristics required for ac specifications. Actual tolerance of VPP is 200 mV.
3. VIN (dc) specifies maximum dc excursion of each differential input.
4. The VDIF (dc) minimum is calculated by VOH – VOL, where VOH is the true input signal and VOL is the complementary input signal.
5. VCM specifies the maximum allowable voltage range of the input signal crosspoint.
6. VX is the differential output crosspoint voltage (see Table 6 on page 7).
7. Two PCLK signals to 25 Ω, and one EXTFB signal through 50 Ω.
8. 1.3 M/s (250 fpm) airflow.
6
Agere Systems Inc.
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Electrical Characteristics (continued)
Table 6. ac Characteristics
VDDA = VDDD = 3.3 V ± 5%, VDDHSTL = 1.7 V—2.1 V, TA = 0 °C—70 °C.
Symbol
Description
Min
Typ
Max
Unit
Condition
fref
Input Frequency
—
70—125
—
MHz
—
fMAX
Maximum Output
Frequency
336
—
1000
MHZ
—1
tsk (o)
Skew Error (PCLK)
—
—
35
ps
—2
tjit (0)
Phase Jitter (I/O Jitter)
—
—
(output period)/2
—
—2
tjit (cc)
Cycle-to-Cycle Jitter
(Full Period)
—
—
5
%
—2,3
tjit (1/2 period) Cycle-to-Cycle Jitter
(Half Period)
—
—
8
%
—2,4
Differential Output
Peak-to-Peak Swing
0.6
—
—
V
For all HSTL
output pairs.
VX
Differential Output
Crosspoint Voltage
0.68
—
0.9
V
For all HSTL
output pairs.
tlock
Maximum PLL Lock Time
—
—
10
ms
—
VDIFout
1. When the phase-locked loop is active but in bypass mode, fref maximum is limited by input the buffer; optimum performance is obtained
from PECL input.
2. At differential pair crossover.
3. Full PCLK period.
4. Half PCLK period.
VDDHSTL
VOH
VDIF
VX
VCM
VOL
VSS
2276 (F)
Figure 3. HSTL Differential Input Levels
Z = 50 Ω
OUTPUT
RT = 25 Ω
VTT = VSS (GROUND)
2277 (F)
Figure 4. Output Termination and ac Test Reference
Agere Systems Inc.
7
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Applications
Power Supply Filtering
The LCK4801 is a mixed analog/digital product. Because of this, it exhibits some sensitivities that would not
necessarily be seen on a fully digital product. Analog circuitry is susceptible to random noise, the worst case being
when this noise is seen on the power supply pins. The LCK4801 provides separate power supplies for the output
buffers (VDDHSTL) and the phase-locked loop (VDDA) of the device in order to isolate the high digital output
switching noise from the internal analog PLL. In a controlled evaluation board environment, this level of isolation is
adequate. However, in a digital system, a second level of isolation is suggested.
The easiest way to accomplish this is to add a power supply filter on the VDDA pin of the LCK4801. Figure 5 on
page 9 shows the typical power supply scheme. The filter should be designed in the 10 kHz—1 MHz range, since
this is the most likely frequency range to cause spectral content noise.
Note the dc voltage drop between VDDD and VDDA on the power supply filter. Very little dc voltage drop can be
tolerated when a 3.3 V VDDD supply is used. The power supply filter in Figure 5 must be 5 Ω—10 Ω in order to
meet the drop criteria. The RC filter in Figure 5 will provide a broadband filter with approximately 100:1 attenuation
above 20 kHz.
The impedance of an individual capacitor begins to appear inductive and increases with frequency as the noise
frequency crosses the series resonant point of the capacitor. The parallel capacitor combination ensures that for
frequencies much greater than the bandwidth of the PLL there is always a low-impedance path.
8
Agere Systems Inc.
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Applications (continued)
3.3 V
RS = 5—10 Ω
VDDA
0.01 µF
22 µF
VDDD
0.01 µF
2278 (F)
Figure 5. Power Supply Filter
Although the LCK4801 has an isolated power supply and grounds, as well as fully differential PLL, there still may
be applications in which overall performance is being compromised due to system power supply noise. The power
supply filter schemes discussed are adequate to eliminate power supply noise problems in most designs.
Agere Systems Inc.
9
LCK4801
Low-Voltage HSTL Differential Clock
Preliminary Data Sheet
July 2001
Outline Diagram
Dimensions are in millimeters.
9.00 ± 0.20
7.00 ± 0.20
1.00 REF
PIN #1
IDENTIFIER ZONE
32
25
0.25
GAGE PLANE
24
1
SEATING PLANE
0.45/0.75
7.00
± 0.20
DETAIL A
9.00
± 0.20
17
8
16
9
0.09/0.200
DETAIL A
DETAIL B
0.30/0.45
1.40 ± 0.05
0.20
1.60 MAX
M
DETAIL B
SEATING PLANE
0.10
0.80 TYP
0.05/0.15
12-3076(F)
For additional information, contact your Agere Systems Account Manager or the following:
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http://www.agere.com
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[email protected]
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Tel. (65) 778 8833, FAX (65) 777 7495
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Tel. (86) 21 50471212, FAX (86) 21 50472266
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Agere Systems Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan
Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700
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Data Requests: DATALINE: Tel. (44) 7000 582 368, FAX (44) 1189 328 148
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Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.
Copyright © 2001 Agere Systems Inc.
All Rights Reserved
Printed in U.S.A.
July 2001
DS01-234HSI