Freescale Semiconductor Technical Data 3.3 V 1:6 LVCMOS PLL Clock Generator The MPC9331 is a 3.3 V compatible, 1:6 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance telecom, networking, and computing applications. With output frequencies up to 240 MHz and output skews less than 150 ps, the device meets the needs of most the demanding clock applications. The MPC9331 is specified for the temperature range of 0°C to +70°C. MPC9331 Rev. 7, 1/2005 MPC9331 LOW VOLTAGE 3.3 V LVCMOS 1:6 CLOCK GENERATOR Features • • • • • • • • • • • • • • • • • 1:6 PLL based low-voltage clock generator 3.3 V power supply Generates clock signals up to 240 MHz Maximum output skew of 150 ps Differential LVPECL reference clock input Alternative LVCMOS PLL reference clock input Internal and external PLL feedback Supports zero-delay operation in external feedback mode PLL multiplies the reference clock by 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3 or x/4 Synchronous output clock stop in logic low eliminates output runt pulses Power_down feature reduces output clock frequency Drives up to 12 clock lines 32-lead LQFP packaging 32-lead Pb-free Package Available Ambient temperature range 0°C to +70°C Internal Power-Up Reset Pin and function compatible to the MPC931 FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-03 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-03 Functional Description The MPC9331 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9331 requires either the selection of internal PLL feedback or the connection of one of the device outputs to the feedback input to close the PLL feedback path in external feedback mode. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. In external PLL feedback configuration and with the available post-PLL dividers (divide-by-2, divide-by-4, and divide-by-6), the internal VCO of the MPC9331 is running at either 2x, 4x, 6x, 8x, or 12x of the reference clock frequency. In internal feedback configuration (divide-by-8) the internal VCO is running 8x of the reference frequency. The frequency of the QA, QB, QC output banks is a division of the VCO frequency and can be configured independently for each output bank using the FSELA, FSELB, and FSELC pins, respectively. The available output to input frequency ratios are 4x, 3x, 2x, 1x, 4/3x, 3/2x, 2/3x, x/2, x/3, or x/4. The REF_SEL pin selects the differential LVPECL or the LVCMOS compatible input as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be disabled (high-impedance) by deasserting the OE/MR pin. In the PLL configuration with external feedback selected, deasserting OE/MR causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Asserting OE/MR will enable the outputs and close the phase locked loop, enabling the PLL to recover to normal operation. The MPC9331 output clock stop control allows the outputs to start and stop synchronously in logic low state, without the potential generation of runt pulses. The MPC9331 is fully 3.3 V compatible and requires no external loop filter components. The inputs (except PCLK) accept LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC9331 outputs can drive one or two traces giving the devices an effective fanout of 1:12. The device is packaged in a 7x7 mm2 32-lead LQFP package. © Freescale Semiconductor, Inc., 2005. All rights reserved. VCC 3 x 25 K Bank A PCLK PCLK 0 Ref 1 CCLK VCO PLL REF_SEL 0 ÷2 1 QA0 1 200 – 480 MHz 25k ÷2 0 ÷4 1 25k VCC CLK Stop QA1 ÷6 Bank B QB0 1 FB_IN FB_SEL ÷1 0 0 FB 0 1 CLK Stop QB1 ÷8 25k Bank C VCC QC0 25k PWR_DN 0 VCC 1 25k CLK Stop QC1 PLL_EN FSELA FSELB FSELC 3 x 25 K VCC Power_On Reset 3 x 25 K 3 CLK_STOP0 CLK_STOP1 OE/MR GND QB0 QB1 VCC FB_SEL REF_SEL PLL_EN NC Figure 1. MPC9331 Logic Diagram 24 23 22 21 20 19 18 17 GND 25 16 GND QA1 26 15 QC1 QA0 27 14 QC0 VCC 28 13 VCC FSELA 29 12 FB_IN FSELB 30 11 CLK_STOP1 FSELC 31 10 CLK_STOP0 NC 32 MPC9331 2 3 4 5 6 7 8 NC VCC_PLL PWR_DN CCLK OE/MR PCKL PCKL GND 9 1 NC It is recommended to use an external RC filter for the analog VCC_PLL power supply pin. Please see application section for details. Figure 2. MPC9331 32-Lead Package Pinout (Top View) MPC9331 2 Advanced Clock Drivers Devices Freescale Semiconductor Table 1. Pin Configuration Pin I/O Type Function CCLK Input LVCMOS PLL reference clock signal PCLK, PCLK Input LVPECL Differential PECL reference clock signal FB_IN Input LVCMOS PLL feedback signal input, connect to an output FB_SEL Input LVCMOS Feedback select REF_SEL Input LVCMOS Reference clock select PWR_DN Input LVCMOS Output frequency and power down select FSELA Input LVCMOS Frequency divider select for bank A outputs FSELB Input LVCMOS Frequency divider select for bank B outputs FSELC Input LVCMOS Frequency divider select for bank C outputs PLL_EN Input LVCMOS PLL enable/disable CLK_STOP0-1 Input LVCMOS Clock output enable/disable OE/MR Input LVCMOS Output enable/disable (high-impedance tristate) and device reset QA0-1, QB0-1, QC0-1 Output LVCMOS Clock outputs GND Supply Ground Negative power supply (GND) VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 2. Function Table Control Default 0 1 REF_SEL 0 PCLK is the PLL reference clock CCLK is the PLL reference clock FB_SEL 1 Internal PLL feedback of 8. fVCO = 8 * fref External feedback. Zero-delay operation enabled for CCLK or PCLK as reference clock PLL_EN 1 Test mode with PLL disabled. The reference clock is substituted Normal operation mode with PLL enabled. for the internal VCO output. MPC9331 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. PWR_DN 1 VCO ÷ 1 (High output frequency range) VCO ÷ 2 (Low output frequency range) FSELA 0 Output divider ÷ 2 Output divider ÷ 4 FSELB 0 Output divider ÷ 2 Output divider ÷ 4 FSELC 0 Output divider ÷ 4 Output divider ÷ 6 OE/MR 1 Outputs disabled (high-impedance state) and reset of the Outputs enabled (active) device. During reset in external feedback configuration, the PLL feedback loop is open. The VCO is tied to its lowest frequency. The MPC9331 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLK or PCLK). Reset does not affect PLL lock in internal feedback configuration. CLK_STOP[0:1] 11 See Table 3 PWR_DN, FSELA, FSELB and FSELC control the operating PLL frequency range and input/output frequency ratios. See Table 8 through Table 10 for supported frequency ranges and output to input frequency ratios. MPC9331 Advanced Clock Drivers Devices Freescale Semiconductor 3 Table 3. Clock Output Synchronous Disable (CLK_STOP) Function Table(1) CLK_STOP0 CLK_STOP1 QA[0:1] QB[0:1] QC[0:1] 0 0 Active Stopped in logic L state Stopped in logic L state 0 1 Active Stopped in logic L state Active 1 0 Stopped in logic L state Stopped in logic L state Active 1 1 Active Active Active 1. Output operation for OE/MR=1 (outputs enabled). OE/MR=0 will disable (high-impedance state) all outputs independent on CLK_STOP[0:1]. Table 4. General Specifications Symbol Characteristics Min Typ Max Unit VCC ÷ 2 VTT Output Termination Voltage MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V 200 Condition V LU Latch-Up Immunity CPD Power Dissipation Capacitance 10 mA pF Per output CIN Input Capacitance 4.0 pF Inputs Table 5. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC + 0.3 V DC Output Voltage –0.3 VCC + 0.3 V DC Input Current ±20 mA DC Output Current ±50 mA 125 °C VOUT IIN IOUT TS Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 6. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to 70°C) Symbol Characteristics Min VIH Input high voltage VIL Input low voltage VPP Peak-to-peak input voltage PCLK, PCLK 250 Common Mode Range PCLK, PCLK 1.0 VCMR(1) VOH Output High Voltage VOL Output Low Voltage ZOUT Output impedance IIN ICC_PLL ICCQ Typ 2.0 Unit V LVCMOS 0.8 V LVCMOS mV LVPECL V LVPECL V IOH = –24 mA(2) 0.55 0.30 V V IOL = 24 mA IOL = 12 mA ±200 µA VIN = VCC or GND 12 mA VCC_PLL Pin 26 mA All VCC Pins VCC – 0.6 2.4 Maximum PLL Supply Current 8.0 (4) Condition Ω 14 – 17 Input Current(3) Maximum Quiescent Supply Current Max VCC + 0.3 1. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. 2. The MPC9331 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines. 3. Inputs have pull-down or pull-up resistors affecting the input current. 4. OE/MR=0 (outputs in high-impedance state). MPC9331 4 Advanced Clock Drivers Devices Freescale Semiconductor Table 7. AC Characteristics (VCC = 3.3V ± 5%, TA = 0°C to 70°C)(1) Symbol fREF Characteristics Input reference frequency PLL mode, external feedback Min VCO lock frequency range(3) fMAX Output Frequency VPP Peak-to-peak input voltage VCMR (4) Common Mode Range Input Reference Pulse Width tR, tF CCLK Input Rise/Fall Time(6) t(∅) tsk(O) DC MHz MHz MHz MHz MHz MHz MHz 200 480 MHz 100.0 50.0 33.3 25.0 16.67 240.0 120.0 80.0 60.0 40.0 MHz MHz MHz MHz MHz PLL locked PCLK, PCLK 400 1000 mV LVPECL PCLK, PCLK 1.2 VCC – 0.9 V LVPECL 2.0 CCLK to FB_IN PCLK to FB_IN(7) CCLK or PCLK to FB_IN(8) –250 –180 –3.0 (9) (T÷2)–500 –130 –30 T÷2 0.1 1.0 ns 0.8 to 2.0 V –50 +120 +3.0 ps ps ° FB_SEL = 1 and PLL locked 150 ps (T÷2)+500 ps 1.0 ns tR, tF Output Rise/Fall Time tPLZ, HZ Output Disable Time 8.0 ns tPZL, LZ Output Enable Time 10 ns (10) tJIT(CC) Cycle-to-cycle jitter 200 ps tJIT(PER) Period Jitter 125 ps 25 ps tJIT(∅) BW tLOCK 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. RMS (1 σ) I/O Phase Jitter (11) PLL closed loop bandwidth PLL mode, external feedback Maximum PLL Lock Time ÷ 4 feedback ÷ 6 feedback ÷ 8 feedback ÷12 feedback PLL locked ns Output-to-output Skew Output duty cycle 240.0 120.0 80.0 60.0 40.0 60.0 240 Condition ÷2 output ÷4 output ÷6 output ÷8 output ÷12 output (7) Propagation Delay (static phase offset) Unit 100.0 50.0 33.3 25.0 16.67 25.0 (5) tPW,MIN Max ÷2 feedback ÷4 feedback ÷6 feedback ÷8 feedback ÷12 feedback (÷8 feedback) PLL mode, internal feedback Input reference frequency in PLL bypass mode(2) fVCO Typ 2.0–8.0 1.2–4.0 1.0–3.0 0.7–2.0 0.55 to 2.4 V MHz MHz MHz MHz 10 ms AC characteristics apply for parallel output termination of 50 Ω to VTT. In bypass mode, the MPC9331 divides the input reference clock. The input frequency fREF must match the VCO frequency range divided by the feedback divider ratio FB: fREF = fVCO ÷ FB. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅). Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% – DCREF,MIN. The MPC9331 will operate with input rise/fall times up to 3.0 ns, but the AC characteristics, specifically t(∅), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. Data valid for fREF = 50 MHz and a PLL feedback of ÷8 (e.g. QAx connected to FB_IN and FSELA=1, PWR_DN=1). Data valid for 16.67 MHz < fREF < 100 MHz and any feedback divider. tsk(O) [s] = tsk(O) [°] ÷ (fREF ⋅ 360°). Output duty cycle is DC = (0.5 ± 500 ps ⋅ fOUT) ⋅ 100%. (e.g. the DC range at fOUT = 100 MHz is 45% < DC < 55%). All outputs in ÷4 divider configuration. –3 dB point of PLL transfer characteristics. MPC9331 Advanced Clock Drivers Devices Freescale Semiconductor 5 APPLICATIONS INFORMATION Output Power Down (PWR_DN) Timing Diagram VCO÷2 VCO÷4 PWR_DWN QAx (÷2) QBx (÷4) QCx (÷6) Output Clock Stop (CLK_STOP) Timing Diagram QAx (÷2) QBx (÷4) QCx (÷6) CLK_STOP0 CLK_STOP1 QAx (÷2) QBx (÷4) QCx (÷6) Programming the MPC9331 The MPC9331 supports output clock frequencies from 16.67 to 240 MHz. Different feedback and output divider configurations can be used to achieve the desired input to output frequency relationship. The feedback frequency and divider should be used to situate the VCO in the frequency lock range between 200 and 480 MHz for stable and optimal operation. The FSELA, FSELB, FSELC and PWR_DN pins select the desired output clock frequencies. Possible frequency ratios of the reference clock input to the outputs are 4:1, 3:1, 2:1, 1:1, 1:2, 2:3 and 3:2. Table 8 illustrates the various output configurations and frequency ratios supported by the MPC9331. See also Table 9 and Table 10 for further reference. MPC9331 6 Advanced Clock Drivers Devices Freescale Semiconductor Table 8. MPC9331 Example Configurations (Internal Feedback: FB_SEL = 0) fref(1) [MHz] PWR_DN FSELA FSELB FSELC 25.0 – 60.0 0 0 0 0 fref ⋅ 4 (100-240 MHz) fref ⋅ 4 (100-240 MHz) fref ⋅ 2 (50-120 MHz) 0 0 0 1 fref ⋅ 4 (100-240 MHz) fref ⋅ 4 (100-240 MHz) fref ⋅4÷3 (33.3-80 MHz) 0 0 1 0 fref ⋅ 4 (100-240 MHz) fref ⋅ 2 (50-120 MHz) fref ⋅ 2 (50-120 MHz) 0 0 1 1 fref ⋅ 4 (100-240 MHz) fref ⋅ 2 (50-120 MHz) fref ⋅4÷3 (33.3-80 MHz) 0 1 0 0 fref ⋅ 2 (50-120 MHz) fref ⋅ 4 (100-240 MHz) fref ⋅ 2 (50-120 MHz) 0 1 0 1 fref ⋅ 2 (50-120 MHz) fref ⋅ 4 (100-240 MHz) fref ⋅4÷3 (33.3-80 MHz) 0 1 1 0 fref ⋅ 2 (50-120 MHz) fref ⋅ 2 (50-120 MHz) fref ⋅ 2 (50-120 MHz) 0 1 1 1 fref ⋅ 2 (50-120 MHz) fref ⋅ 2 (50-120 MHz) fref ⋅4÷3 (33.3-80 MHz) 1 0 0 0 fref ⋅ 2 (50-120 MHz) fref ⋅ 2 (50-120 MHz) fref 1 0 0 1 fref ⋅ 2 (50-120 MHz) fref ⋅ 2 (50-120 MHz) fref ⋅2÷3 1 0 1 0 fref ⋅ 2 (50-120 MHz) fref (25.0-60 MHz) fref 1 0 1 1 fref ⋅ 2 (50-120 MHz) fref (25.0-60 MHz) fref ⋅2÷3 1 1 0 0 fref (25.0-60 MHz) fref ⋅ 2 (50-120 MHz) fref 1 1 0 1 fref (25.0-60 MHz) fref ⋅ 2 (50-120 MHz) fref ⋅2÷3 1 1 1 0 fref (25.0-60 MHz) fref (25.0-60 MHz) fref 1 1 1 1 fref (25.0-60 MHz) fref (25.0-60 MHz) fref ⋅2÷3 QA[0:1]:fref ratio QB[0:1]:fref ratio QC[0:1]:fref ratio (25.0-60 MHz) (16.67-40 MHz) (25.0-60 MHz) (16.67-40 MHz) (25.0-60 MHz) (16.67-40 MHz) (25.0-60 MHz) (16.67-40 MHz) 1. fref is the input clock reference frequency (CCLK or PCLK). Table 9. MPC9331 Example Configurations (External Feedback and PWR_DN = 0) PLL Feedback VCO ÷ 2(2) VCO ÷ 4(3) VCO ÷ 6(4) 1. 2. 3. 4. fref(1) [MHz] 100 – 240 50 –120 33.3 – 80 FSELA FSELB FSELC QA[0:1]:fref ratio QB[0:1]:fref ratio QC[0:1]:fref ratio 0 0 0 fref (100-240 MHz) fref (100-240 MHz) fref ÷ 2 (50-120 MHz) 0 0 1 fref (100-240 MHz) fref (100-240 MHz) fref ÷ 3 (33.3-80 MHz) 0 1 0 fref (100-240 MHz) fref ÷ 2 (50-120 MHz) fref ÷ 2 (50-120 MHz) 0 1 1 fref (100-240 MHz) fref ÷ 2 (50-120 MHz) fref ÷ 3 (33.3-80 MHz) 1 0 0 fref (50-120 MHz) fref ⋅2 (100-240 MHz) fref (50-120 MHz) 1 0 1 fref (50-120 MHz) fref ⋅2 (100-240 MHz) fref ⋅2÷3 (33.3-80 MHz) 1 1 0 fref (50-120 MHz) fref (100-240 MHz) fref (50-120 MHz) 1 1 1 fref (50-120 MHz) fref (100-240 MHz) fref ⋅2 ÷ 3 (33.3-80 MHz) 0 0 1 fref ⋅3 (100-240 MHz) fref ⋅3 (100-240 MHz) fref (33.3-80 MHz) 0 1 1 fref ⋅3 (100-240 MHz) fref ⋅3 ÷ 2 (50-120 MHz) fref (33.3-80 MHz) 1 0 1 fref ⋅3 ÷ 2 (50-120 MHz) fref ⋅3 (100-240 MHz) fref (33.3-80 MHz) 1 1 1 fref ⋅3 ÷ 2 (50-120 MHz) fref ⋅3 ÷ 2 (50-120 MHz) fref (33.3-80 MHz) fref is the input clock reference frequency (CCLK or PCLK). QAx connected to FB_IN and FSELA=0, PWR_DN=0. QAx connected to FB_IN and FSELA=1, PWR_DN=0. QCx connected to FB_IN and FSELC=1, PWR_DN=0. Table 10. MPC9331 Example Configurations (External Feedback and PWR_DN = 1) PLL Feedback fref(1) [MHz] FSELA FSELB FSELC VCO ÷ 8(2) 25.0 – 60.0 1 0 0 fref 25-60 MHz) fref ⋅2 (50-120 MHz) fref (2.25-60 MHz) 1 0 1 fref (25-60 MHz) fref ⋅2 (50-120 MHz) fref ⋅2÷3 (16.6-40 MHz) 1 1 0 fref (25-60 MHz) fref (25-60 MHz) fref 1 1 1 fref (25-60 MHz) fref (25-60 MHz) fref ⋅2÷3 0 0 1 fref ⋅3 (50-120 MHz) fref ⋅3 (50-120 MHz) fref (16.67-40 MHz) 0 1 1 fref ⋅3 (50-120 MHz) fref ⋅3 ÷ 2 (25-60 MHz) fref (16.67-40 MHz) 1 0 1 fref ⋅3 ÷ 2 (25-60 MHz) fref ⋅3 (50-120 MHz) fref (16.67-40 MHz) 1 1 1 fref ⋅3 ÷ 2 (25-60 MHz) fref ⋅3 ÷ 2 (25-60 MHz) fref (16.67-40 MHz) VCO ÷ 12(3) 16.67 – 40 QA[0:1]:fref ratio QB[0:1]:fref ratio QC[0:1]:fref ratio (25-60 MHz) (16.6-40 MHz) 1. fref is the input clock reference frequency (CCLK or PCLK). 2. QAx connected to FB_IN and FSELA=1, PWR_DN=1. 3. QCx connected to FB_IN and FSELC=1, PWR_DN=1. MPC9331 Advanced Clock Drivers Devices Freescale Semiconductor 7 APPLICATIONS INFORMATION Power Supply Filtering The MPC9331 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance, I/O jitter. The MPC9331 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies, a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9331. Figure 3 illustrates a typical power supply filter scheme. The MPC9331 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet, the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 8 mA (12 mA maximum), assuming that a minimum of 3.0 V must be maintained on the VCC_PLL pin. RF = 10 – 15Ω CF = 22 µF RF VCC Driving Transmission Lines The MPC9331 clock driver was designed to drive highspeed signals in a terminated transmission line environment. To provide the optimum flexibility to the user, the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω, the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines, the reader is referred to Freescale application note AN1091. In most high performance clock networks, point-to-point distribution of signals is the method of choice. In a point-to-point scheme, either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 Ω resistance to VCC÷2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9331 clock driver. For the series terminated case, however, there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 4 illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9331 clock driver is effectively doubled due to its capability to drive multiple lines. MPC9331 OUTPUT BUFFER VCC_PLL CF 10 nF MPC9331 14Ω IN RS = 36Ω ZO = 50Ω RS = 36Ω ZO = 50Ω RS = 36Ω ZO = 50Ω OutA VCC MPC9331 OUTPUT BUFFER 33...100 nF Figure 3. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 3, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9331 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. IN OutB0 14Ω OutB1 Figure 4. Single versus Dual Transmission Lines The waveform plots in Figure 5 show the simulation results of an output driving a single line versus two lines. In both cases, the drive capability of the MPC9331 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations, a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9331. The output waveform in Figure 5 shows a step in the waveform; this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: MPC9331 8 Advanced Clock Drivers Devices Freescale Semiconductor VL = Z0 = RS = R0 = VL = = VS (Z0 ÷ (RS+R0 + Z0)) 50 Ω || 50 Ω 36 Ω || 36 Ω 14 Ω 3.0 (25 ÷ (18+14+25) 1.31 V At the load end, the voltage will double due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). 1. Final skew data pending specification. Since this step is well above the threshold region it will not cause any false clock triggering; however, designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines, the situation in should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance, the line impedance is perfectly matched. MPC9331 Output Buffer RS = 22Ω ZO = 50Ω RS = 22Ω ZO = 50Ω 14Ω 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 14Ω + 22Ω || 22Ω = 50Ω || 50Ω 25Ω = 25Ω Voltage (V) 2.0 In Figure 6. Optimized Dual Line Termination 1.5 1.0 0.5 0 2 4 6 8 Time (ns) 10 12 14 Figure 5. Single versus Dual Line Termination Waveforms MPC9931 DUT Pulse Generator Z = 50Ω ZO = 50Ω ZO = 50Ω RT = 50Ω RT = 50Ω VTT VTT Figure 7. CCLK MPC9331 AC Test Reference for Vcc = 3.3 V MPC9331 Advanced Clock Drivers Devices Freescale Semiconductor 9 VCC VCC ÷ 2 GND VCC VCC VCC ÷ 2 CCLK GND VCC ÷ 2 GND tSK(O) VCC VCC ÷ 2 FB_IN GND The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 8. Output-to-Output Skew tSK(O) t(∅) Figure 9. Propagation Delay (t(∅), Static Phase offset) Test Reference VCC VCC ÷ 2 CCLK GND tP FB_IN T0 DC = tP/T0 x 100% TJIT(ý) = |T0–T1mean| The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 10. Output Duty Cycle (DC) Figure 11. I/O Jitter TN TN+1 TJIT(CC) = |TN–TN+1| TJIT(PER) = |TN–1/f0| T0 The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 12. Cycle-to-Cycle Jitter Figure 13. Period Jitter VCC=3.3 V 2.4 0.55 tF tR Figure 14. Output Transition Time Test Reference MPC9331 10 Advanced Clock Drivers Devices Freescale Semiconductor PACKAGE DIMENSIONS 4X 0.20 H 6 A-B D D1 PIN 1 INDEX 3 e/2 D1/2 32 A, B, D 25 1 E1/2 A F B 6 E1 E 4 F DETAIL G 8 17 9 7 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED AT DATUM PLANE H. 4. DIMENSIONS D AND E TO BE DETERMINED AT SEATING PLANE C. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08-mm. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION: 0.07-mm. 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1-mm AND 0.25-mm FROM THE LEAD TIP. 4 D 4X A-B D H SEATING PLANE DETAIL G D D/2 0.20 C E/2 28X e 32X C 0.1 C DETAIL AD PLATING BASE METAL b1 c c1 b 8X (θ1˚) 0.20 R R2 A2 8 C A-B D SECTION F-F R R1 A M 5 0.25 GAUGE PLANE A1 (S) L (L1) θ˚ DETAIL AD DIM A A1 A2 b b1 c c1 D D1 e E E1 L L1 q q1 R1 R2 S MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0.30 0.40 0.09 0.20 0.09 0.16 9.00 BSC 7.00 BSC 0.80 BSC 9.00 BSC 7.00 BSC 0.50 0.70 1.00 REF 0˚ 7˚ 12 REF 0.08 0.20 0.08 --0.20 REF C S CASE 873A-03 ISSUE B 32-LEAD LQFP PACKAGE MPC9331 Advanced Clock Drivers Devices Freescale Semiconductor 11 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 [email protected] Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) [email protected] Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 [email protected] For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. 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