19-2442; Rev 1; 10/02 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs The MAX1036–MAX1039 low-power, 8-bit, multichannel, analog-to-digital converters (ADCs) feature internal track/hold (T/H), voltage reference, clock, and an I2C-compatible 2-wire serial interface. These devices operate from a single supply and require only 350µA at the maximum sampling rate of 188ksps. AutoShutdown™ powers down the devices between conversions reducing supply current to less than 1µA at low throughput rates. The MAX1036/MAX1037 have four analog input channels each, while the MAX1038/MAX1039 have twelve analog input channels. The analog inputs are software configurable for unipolar or bipolar and singleended or pseudo-differential operation. The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to V DD . The MAX1037/ MAX1039 feature a 2.048V internal reference and the MAX1036/MAX1038 feature a 4.096V internal reference. The MAX1036/MAX1037 are available in 8-pin SOT23 packages. The MAX1038/MAX1039 are available in 16pin QSOP packages. The MAX1036–MAX1039 are guaranteed over the extended industrial temperature range (-40°C to +85°C). Refer to MAX1136–MAX1139 for 10-bit devices and to the MAX1236–MAX1239 for 12-bit devices. Applications Hand-Held Portable Applications Medical Instruments Battery-Powered Test Equipment Solar-Powered Remote Systems Received-Signal-Strength Indicators System Supervision Features ♦ High-Speed I2C-Compatible Serial Interface 400kHz Fast Mode 1.7MHz High-Speed Mode ♦ Single Supply 2.7V to 3.6V (MAX1037/MAX1039) 4.5V to 5.5V (MAX1036/MAX1038) ♦ Internal Reference 2.048V (MAX1037/MAX1039) 4.096V (MAX1036/MAX1038) ♦ External Reference: 1V to VDD ♦ Internal Clock ♦ 4-Channel Single-Ended or 2-Channel PseudoDifferential (MAX1036/MAX1037) ♦ 12-Channel Single-Ended or 6-Channel PseudoDifferential (MAX1038/MAX1039) ♦ Internal FIFO with Channel-Scan Mode ♦ Low Power 350µA at 188ksps 110µA at 75ksps 8µA at 10ksps 1µA in Power-Down Mode ♦ Software Configurable Unipolar/Bipolar ♦ Small Packages 8-Pin SOT23 (MAX1036/MAX1037) 16-Pin QSOP (MAX1038/MAX1039) Pin Configurations and Typical Operating Circuit appear at end of data sheet. Ordering Information PART TUE (LSB) INPUT CHANNELS INTERNAL REFERENCE (V) 8 SOT23-8 ±2 4 4.096 AAJE 8 SOT23-8 ±2 4 2.048 AAJG -40°C to +85°C 16 QSOP ±1 12 4.096 — -40°C to +85°C 16 QSOP ±1 12 2.048 — TEMP RANGE PIN-PACKAGE MAX1036EKA-T -40°C to +85°C MAX1037EKA-T -40°C to +85°C MAX1038AEEE MAX1039AEEE TOP MARK AutoShutdown is a trademark of Maxim Integrated Products, Inc. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1036–MAX1039 General Description MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V AIN0–AIN11, REF to GND ......................-0.3V to the lower of (VDD + 0.3V) and +6V SDA, SCL to GND.....................................................-0.3V to +6V Maximum Current Into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 8-Pin SOT23 (derate 7.1mW/°C above +70°C).............567mW 16-Pin QSOP (derate 8.3mW/°C above +70°C).........666.7mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V DD = 2.7V to 3.6V (MAX1037/MAX1039), V DD = 4.5V to 5.5V (MAX1036/MAX1038). External reference, V REF = 2.048V (MAX1037/MAX1039), VREF = 4.096V (MAX1036/MAX1038). External clock, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution 8 Bits Relative Accuracy INL (Note 2) ±1 LSB Differential Nonlinearity DNL No missing codes over temperature ±1 LSB ±1.5 LSB Offset Error Offset Error Temperature Coefficient 3 Gain Error ±1 (Note 3) ±1 Gain Temperature Coefficient Total Unadjusted Error ppm/°C TUE LSB ppm/°C MAX1036/MAX1037 ±0.5 ±2 MAX1038A/MAX1039A ±0.5 ±1 LSB Channel-to-Channel Offset Matching ±0.1 LSB Channel-to-Channel Gain Matching ±0.5 LSB 75 dB Input Common-Mode Rejection Ratio CMRR Pseudo-differential input mode DYNAMIC PERFORMANCE (fIN(sine wave) = 25kHz, VIN = VREF(P-P), fSAMPLE = 188ksps, RIN = 100Ω) Signal-to-Noise Plus Distortion SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Up to the 5th harmonic 49 dB -69 dB 69 dB Channel-to-Channel Crosstalk (Note 4) 75 dB Full-Power Bandwidth -3dB point 2.0 MHz Full-Linear Bandwidth SINAD > 49dB 200 kHz CONVERSION RATE Conversion Time (Note 5) 2 tCONV Internal clock External clock 6.1 4.7 _______________________________________________________________________________________ µs 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs (V DD = 2.7V to 3.6V (MAX1037/MAX1039), V DD = 4.5V to 5.5V (MAX1036/MAX1038). External reference, V REF = 2.048V (MAX1037/MAX1039), VREF = 4.096V (MAX1036/MAX1038). External clock, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER Throughput Rate SYMBOL fSAMPLE CONDITIONS MIN TYP Internal clock, SCAN[1:0] = 01 (MAX1036/MAX1037) 76 Internal clock, SCAN[1:0] = 00 CS[3:0] = 1011 (MAX1038/MAX1039) 77 External clock 588 Internal Clock Frequency ksps ns 2.25 tAD UNITS 188 Track/Hold Acquisition Time Aperture Delay MAX External clock, fast mode 45 External clock, high-speed mode 30 MHz ns ANALOG INPUT (AIN0–AIN11) Unipolar Input Voltage Range, Single Ended and Differential (Note 6) VREF ±VREF / 2 On/off-leakage current, VAIN_= 0 or VDD, no clock, fSCL = 0 Input Multiplexer Leakage Current Input Capacitance 0 Bipolar ±0.01 CIN ±1 18 V µA pF INTERNAL REFERENCE (Note 7) Reference Voltage VREF Reference Temperature Coefficient TA = +25°C MAX1037/MAX1039 1.925 2.048 2.171 MAX1036/MAX1038 3.850 4.096 4.342 TCREF 120 Reference Short-Circuit Current ppm/°C 10 Reference Source Impedance (Note 8) V mA Ω 675 EXTERNAL REFERENCE Reference Input Voltage Range VREF (Note 9) REF Input Current IREF fSAMPLE = 188ksps 1.0 14 VDD V 30 µA DIGITAL INPUTS/OUTPUTS (SCL, SDA) Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 0.7 x VDD VHYST Input Current IIN Input Capacitance CIN Output Low Voltage VOL V 0.3 x VDD 0.1 x VDD V ±10 VIN = 0 to VDD 15 ISINK = 3mA V µA pF 0.4 V _______________________________________________________________________________________ 3 MAX1036–MAX1039 ELECTRICAL CHARACTERISTICS (continued) MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (V DD = 2.7V to 3.6V (MAX1037/MAX1039), V DD = 4.5V to 5.5V (MAX1036/MAX1038). External reference, V REF = 2.048V (MAX1037/MAX1039), VREF = 4.096V (MAX1036/MAX1038). External clock, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER REQUIREMENTS Supply Voltage (Note 10) Supply Current VDD IDD MAX1037/MAX1039 2.7 3.6 MAX1036/MAX1038 4.5 5.5 fSAMPLE = 188ksps Internal REF, external clock 350 External REF, external clock 250 fSAMPLE = 75ksps External REF, external clock 110 External REF, internal clock 150 fSAMPLE = 10ksps External REF, external clock 8 External REF, internal clock 10 fSAMPLE = 1ksps External REF, external clock 2 External REF, internal clock 2.5 Power-down Power-Supply Rejection Ratio PSRR (Note 11) V 650 µA 1 10 ±0.25 ±1 LSB/V 400 kHz TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1A and 2) Serial Clock Frequency fSCL Bus Free Time Between a STOP and a START Condition tBUF 1.3 µs Hold Time for Start Condition tHD, STA 0.6 µs Low Period of the SCL Clock tLOW 1.3 µs High Period of the SCL Clock tHIGH 0.6 µs Setup Time for a Repeated START Condition (Sr) tSU, STA 0.6 µs Data Hold Time tHD, DAT Data Setup Time tSU, DAT (Note 12) 0 150 100 ns ns Rise Time of Both SDA and SCL Signals, Receiving tR (Note 13) 20 + 0.1CB 300 ns Fall Time of SDA Transmitting tF (Note 13) 20 + 0.1CB 300 ns Setup Time for STOP Condition tSU, STO 0.6 µs Capacitive Load for Each Bus Line CB 400 pF Pulse Width of Spike Suppressed tSP 50 ns 1.7 MHz TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1B and 2) Serial Clock Frequency Hold Time (Repeated) Start Condition fSCLH (Note 14) tHD, STA 160 ns Low Period of the SCL Clock tLOW 320 ns High Period of the SCL Clock tHIGH 120 ns 4 _______________________________________________________________________________________ 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs (V DD = 2.7V to 3.6V (MAX1037/MAX1039), V DD = 4.5V to 5.5V (MAX1036/MAX1038). External reference, V REF = 2.048V (MAX1037/MAX1039), VREF = 4.096V (MAX1036/MAX1038). External clock, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) PARAMETER SYMBOL Setup Time for a Repeated START Condition (Sr) tSU, STA Data Hold Time tHD, DAT Data Setup Time tSU, DAT CONDITIONS MIN TYP MAX 160 (Note 12) 0 UNITS ns 150 10 ns ns Rise Time of SCL Signal (Current Source Enabled) tRCL (Note 13) 20 80 ns Rise Time of SCL Signal After Acknowledge Bit tRCL1 (Note 13) 20 160 ns Fall Time of SCL Signal tFCL (Note 13) 20 80 ns Rise Time of SDA Signal tRDA (Note 13) 20 160 ns Fall Time of SDA Signal tFDA (Note 13) 20 160 Setup Time for STOP Condition tSU, STO Capacitive Load for Each Bus Line CB Pulse Width of Spike Suppressed tSP 160 0 ns ns 400 pF 10 ns Note 1: The MAX1036/MAX1038 are tested at VDD = 5V and the MAX1037/MAX1039 are tested at VDD = 3V. All devices are configured for unipolar, single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. Note 3: Offset nulled. Note 4: Ground ON channel; sine wave applied to all OFF channels. Note 5: Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode. Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD. Note 7: When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor. Note 8: The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675Ω. Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mVP-P. Note 10: Electrical characteristics are guaranteed from VDD(min) to VDD(max). For operation beyond this range, see the Typical Operating Characteristics. Note 11: Power-supply rejection ratio is measured as: N [VFS (3.3V) − VFS (2.7V)] × V2REF 3.3V − 2.7V , for the MAX1037/MAX1039 where N is the number of bits (8) and VREF = 2.048V. Power-supply rejection ratio is measured as: N [VFS (5.5V) − VFS (4.5V)] × V2REF 5.5V − 4.5V , for the MAX1036/MAX1038 where N is the number of bits (8) and VREF = 2.048V. Note 12: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of SCL’s falling edge (Figure 1). Note 13: CB = total capacitance of one bus line in pF. tR and tF measured between 0.3VDD and 0.7VDD. Minimum specification is tested at +25°C with CB = 400pF. Note 14: fSCLH must meet the minimum clock low time plus the rise/fall times. _______________________________________________________________________________________ 5 MAX1036–MAX1039 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (VDD = 3.3V (MAX1037/MAX1039), VDD = 5V (MAX1036/MAX1038), fSCL = 1.7MHz, external clock (33% duty cycle), fSAMPLE = 188ksps, single ended, unipolar, TA = +25°C, unless otherwise noted.) SUPPLY CURRENT vs. TEMPERATURE 400 A SDA = SCL = VDD 4 INTERNAL 4.096VREF 350 IDD (µA) B 300 300 INTERNAL 2.048VREF C 250 IDD (µA) 350 IDD (µA) 5 MAX1036 toc02 A) INTERNAL 4.096VREF B) INTERNAL 2.048VREF C) EXTERNAL 4.096VREF D) EXTERNAL 2.048VREF 400 450 MAX1036 toc01 450 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX1036 toc03 SUPPLY CURRENT vs. VOLTAGE 3 2 EXTERNAL 4.096VREF 250 D 200 200 150 3.0 3.5 4.0 4.5 5.0 0 -40 -15 10 35 60 85 2.5 3.5 4.0 4.5 5.0 5.5 VDD (V) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (INTERNAL CLOCK) AVERAGE SUPPLY CURRENT VS. CONVERSION RATE (EXTERNAL CLOCK) 350 300 VDD = 5V A 500 A) INTERNAL REF ALWAYS ON B) INTERNAL REF AUTOSHUTDOWN C) EXTERNAL REF A 450 400 250 B AVERAGE IDD (µA) AVERAGE IDD (µA) 3 A) INTERNAL REF ALWAYS ON B) INTERNAL REF AUTOSHUTDOWN C) EXTERNAL REF MAX1036 toc05 SDA = SCL = VDD 200 C 150 100 MAX1036 toc06 TEMPERATURE (°C) 2 350 300 B 250 200 C 150 100 1 50 INTERNAL CLOCK MODE fSCL = 1.7MHz VDD = 3.3V -15 10 35 60 0 0 85 10 20 30 40 50 60 TEMPERATURE (°C) CONVERSION RATE (ksps) NORMALIZED 4.096V REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL 4.096V REFERENCE VOLTAGE vs. TEMPERATURE 1.015 1.0000 0.9975 1.0050 1.005 1.000 0.995 1.0025 1.0000 0.9975 0.9950 0.990 0.9950 0.9925 0.985 0.9925 0.9900 0.980 4.00 4.25 4.50 4.75 VDD (V) 5.00 5.25 5.50 200 1.0075 VREF NORMALIZED 1.0025 150 1.0100 1.010 VREF NORMALIZED 1.0050 100 INTERNAL 2.048V REFERENCE VOLTAGE vs. SUPPLY VOLTAGE MAX1036 toc08 1.0075 50 CONVERSION RATE (ksps) 1.020 MAX1036 toc7 1.0100 0 MAX1036 toc09 -40 EXTERNAL CLOCK MODE fSCL = 1.7MHz 50 0 0 6 3.0 VDD (V) 4 IDD (µA) 5.5 MAX1036 toc04 5 1 EXTERNAL 2.048VREF 150 2.5 VREF NORMALIZED MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs 0.9900 -40 -15 10 35 TEMPERATURE (°C) 60 85 2.5 3.0 3.5 4.0 VDD (V) _______________________________________________________________________________________ 4.5 5.0 5.5 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE 0.4 0.3 DNL (LSB) 1.005 1.000 0.995 0.3 0.2 0.2 0.1 0.1 0 -0.1 0 -0.1 -0.2 -0.2 -0.3 -0.3 0.985 -0.4 -0.4 0.980 -0.5 0.990 35 60 85 -0.5 0 50 TEMPERATURE (°C) 100 150 200 250 300 0 50 DIGITAL OUTPUT CODE 1.0 MAX1036 toc13 fSAMPLE = 188ksps fIN = 25kHz -40 -60 -80 VREF = 2.048V 0.9 0.8 OFFSET ERROR (LSB) -20 150 200 250 300 OFFSET ERROR vs. SUPPLY VOLTAGE FFT PLOT 0 100 DIGITAL OUTPUT CODE MAX1036 toc14 10 0.7 0.6 0.5 0.4 0.3 0.2 -100 0.1 -120 0 40k 60k 80k 2.5 100k 3.0 3.5 FREQUENCY (Hz) 4.5 5.0 5.5 GAIN ERROR vs. SUPPLY VOLTAGE OFFSET ERROR vs. TEMPERATURE 1.0 0.9 4.0 VDD (V) 0 VDD = 3.3V VREF = 2.048V 0.8 0.6 0.5 0.4 0.3 -0.02 -0.03 -0.04 -0.05 -0.06 -0.07 0.2 -0.08 0.1 -0.09 0 VREF = 2.048V -0.01 GAIN ERROR (LSB) 0.7 MAX1036 toc16 20k 0 MAX1036 toc15 -15 AMPLITUDE (dBc) -40 OFFSET ERROR (LSB) VREF NORMALIZED 1.010 0.4 INL (LSB) 1.015 0.5 MAX1036 toc11 0.5 MAX1036 toc10 1.020 INTEGRAL NONLINEARITY vs. DIGITAL CODE MAX1036 toc12 INTERNAL 2.048V REFERENCE VOLTAGE vs. TEMPERATURE -0.1 -40 -15 10 35 TEMPERATURE (°C) 60 85 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) _______________________________________________________________________________________ 7 MAX1036–MAX1039 Typical Operating Characteristics (continued) (VDD = 3.3V (MAX1037/MAX1039), VDD = 5V (MAX1036/MAX1038), fSCL = 1.7MHz, external clock (33% duty cycle), fSAMPLE = 188ksps, single ended, unipolar, TA = +25°C, unless otherwise noted.) 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs MAX1036–MAX1039 Pin Description PIN MAX1036/ MAX1037 MAX1038/ MAX1039 NAME FUNCTION 1, 2, 3 8, 7, 6 AIN0–AIN2 — 5, 4, 3, 2, 1 AIN3–AIN7 — 16, 15, 14 AIN8–AIN10 4 — AIN3/REF Analog Input 3/Reference Input or Output. Selected in the setup register. — 13 AIN11/REF Analog Input 11/Reference Input or Output. Selected in the setup register. Analog Inputs 5 9 SCL Clock Input 6 10 SDA Data Input/Output 7 11 GND Ground 8 12 VDD Positive Supply. Bypass to GND with a 0.1µF capacitor. Detailed Description The MAX1036–MAX1039 ADCs use successiveapproximation conversion techniques and input T/H circuitry to capture and convert an analog signal to a serial 8-bit digital output. The MAX1036/MAX1037 are 4-channel ADCs, and the MAX1038/MAX1039 are 12channel ADCs. These devices feature a high-speed 2wire serial interface supporting data rates up to 1.7MHz. Figure 3 shows the simplified functional diagram for the MAX1038/MAX1039. Power Supply The MAX1036–MAX1039 operate from a single supply and consume 350µA at sampling rates up to 188ksps. The MAX1037/MAX1039 feature a 2.048V internal reference and the MAX1036/MAX1038 feature a 4.096V internal reference. All devices can be configured for use with an external reference from 1V to VDD. Analog Input and Track/Hold The MAX1036–MAX1039 analog input architecture contains an analog input multiplexer (MUX), a T/H capacitor, T/H switches, a comparator, and a switched capacitor digital-to-analog converter (DAC) (Figure 4). In single-ended mode, the analog input multiplexer connects CT/H to the analog input selected by CS[3:0] (see the Configuration/Setup Bytes (Write Cycle) section). The charge on CT/H is referenced to GND when converted. In pseudo-differential mode, the analog input multiplexer connects C T/H to the ‘+’ analog input selected by CS[3:0]. The charge on CT/H is referenced to the ‘-’ analog input when converted. 8 The MAX1036–MAX1039 input configuration is pseudodifferential in that only the signal at the ‘+’ analog input is sampled with the T/H circuitry. The ‘-’ analog input signal must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to GND during a conversion. To accomplish this, connect a 0.1µF capacitor from ‘-’ analog input to GND. See the Single-Ended/PseudoDifferential Input section. During the acquisition interval, the T/H switches are in the track position and CT/H charges to the analog input signal. At the end of the acquisition interval, the T/H switches move to the hold position retaining the charge on CT/H as a sample of the input signal. During the conversion interval, the switched capacitive DAC adjusts to restore the comparator input voltage to zero within the limits of 8-bit resolution. This action requires eight conversion clock cycles and is equivalent to transferring a charge of 18pF ✕ (VIN+ - VIN-) from CT/H to the binary weighted capacitive DAC forming a digital representation of the analog input signal. Sufficiently low source impedance is required to ensure an accurate sample. A source impedance below 1.5kΩ does not significantly degrade sampling accuracy. To minimize sampling errors with higher source impedances, connect a 100pF capacitor from the analog input to GND. This input capacitor forms an RC filter with the source impedance limiting the analog input bandwidth. For larger source impedances, use a buffer amplifier to maintain analog input signal integrity. When operating in internal clock mode, the T/H circuitry enters its tracking mode on the ninth falling clock edge _______________________________________________________________________________________ 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs MAX1036–MAX1039 A. F/S-MODE I2C SERIAL INTERFACE TIMING tR tF t SDA tSU.DAT tHD.DAT tHD.STA tLOW tBUF tSU.STA tSU.STO SCL tHD.STA tHIGH tR tF S A Sr P S B. HS-MODE I2C SERIAL INTERFACE TIMING tRDA tFDA SDA tSU.DAT tHD.DAT tBUF tHD.STA tLOW tSU.STO tSU.STA SCL tHD.STA tHIGH tRCL tFCL tRCL1 S Sr A S HS-MODE F/S-MODE Figure 1. I2C Serial Interface Timing of the address byte (see the Slave Address section). The T/H circuitry enters hold mode two internal clock cycles later. A conversion or series of conversions are then internally clocked (eight clock cycles per conversion) and the MAX1036–MAX1039 hold SCL low. When operating in external clock mode, the T/H circuitry enters track mode on the seventh falling edge of a valid slave address byte. Hold mode is then entered on the falling edge of the eighth clock cycle. The conversion is performed during the next eight clock cycles. The time required for the T/H circuitry to acquire an input signal is a function of input capacitance. If the analog input source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the minimum time needed for the signal to be acquired. It is calculated by: tACQ ≥ 6.25 ✕ (RSOURCE + RIN) ✕ CIN where RSOURCE is the analog input source impedance, RIN = 2.5kΩ, and CIN = 18pF. tACQ is 1/fSCL for external VDD IOL = 3mA VOUT SDA 400pF IOH = 0mA Figure 2. Load Circuit clock mode. For internal clock mode, the acquisition time is two internal clock cycles. To select RSOURCE, allow 625ns for tACQ in internal clock mode to account for clock frequency variations. _______________________________________________________________________________________ 9 MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs SDA SCL INPUT SHIFT REGISTER VDD SETUP REGISTER GND CONTROL LOGIC INTERNAL OSCILLATOR CONFIGURATION REGISTER AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11/REF T/H ANALOG INPUT MUX OUTPUT SHIFT REGISTER AND 12-BYTE RAM 8-BIT ADC REF REFERENCE 4.096V (MAX1038) 2.048V (MAX1039) MAX1038 MAX1039 Figure 3. MAX1038/MAX1039 Simplified Functional Diagram ANALOG INPUT MUX REF CT/H AIN2 AIN3/REF GND HOLD HOLD SINGLE ENDED CAPACITIVE DAC TRACK TRACK AIN1 DIFFERENTIAL AIN0 MAX1036 MAX1037 Figure 4. Equivalent Input Circuit Analog Input Bandwidth Analog Input Range and Protection The MAX1036–MAX1039 feature input tracking circuitry with a 2MHz small signal-bandwidth. The 2MHz input bandwidth makes it possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. To avoid high frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Internal protection diodes clamp the analog input to VDD and GND. These diodes allow the analog inputs to swing from (GND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions, the inputs must not go more than 50mV below GND or above VDD. If the analog input exceeds VDD by more than 50mV, the input current should be limited to 2mA. 10 ______________________________________________________________________________________ 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs MAX1036–MAX1039 Table 1. Setup Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) REG SEL2 SEL1 SEL0 CLK BIP/UNI RST X BIT NAME 7 REG 6 SEL2 5 SEL1 4 SEL0 3 CLK 2 BIP/UNI 1 RST 0 X DESCRIPTION Register bit. 1 = Setup Byte, 0 = Configuration Byte (Table 2). Three bits select the reference voltage and the state of AIN_/REF (Table 6). Default to 000 at power-up. 1 = External clock, 0 = Internal clock. Defaulted to zero at power-up. 1 = Bipolar, 0 = Unipolar. Defaulted to zero at power-up (see the Unipolar/Bipolar section). 1 = No action, 0 = Resets the configuration register to default. Setup register remains unchanged. Don’t care, can be set to 1 or 0. Single-Ended/Pseudo-Differential Input Digital Interface The SGL/DIF bit of the configuration byte configures the MAX1036–MAX1039 analog input circuitry for singleended or pseudo-differential inputs (Table 2). In singleended mode (SGL/DIF = 1), the digital conversion results are the difference between the analog input selected by CS[3:0] and GND (Table 3). In pseudo-differential mode (SGL/DIF = 0), the digital conversion results are the difference between the ‘+’ and the ‘-’ analog inputs selected by CS[3:0] (Table 4). The ‘-’ analog input signal must remain stable within ±0.5LSB (±0.1LSB for best results) with respect to GND during a conversion. The MAX1036–MAX1039 feature a 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX1036–MAX1039 and the master at rates up to 1.7MHz. The MAX1036–MAX1039 are slaves that transmit and receive data. The master (typically a microcontroller) initiates data transfer on the bus and generates SCL to permit that transfer. Unipolar/Bipolar When operating in pseudo-differential mode, the BIP/ UNI bit of the setup byte (Table 1) selects unipolar or bipolar operation. Unipolar mode sets the differential analog input range from zero to VREF. A negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to ±VREF/2, with respect to the negative input. The digital output code is binary in unipolar mode and two’s complement binary in bipolar mode (see the Transfer Functions section). In single-ended mode, the MAX1036–MAX1039 always operate in unipolar mode regardless of the BIP/UNI setting, and the analog inputs are internally referenced to GND with a full-scale input range from zero to VREF. SDA and SCL must be pulled high. This is typically done with pullup resistors (500Ω or greater) (see Typical Operating Circuit). Series resistors (RS) are optional. They protect the input architecture of the MAX1036–MAX1039 from high-voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. Nine clock cycles are required to transfer the data in or out of the MAX1036–MAX1039. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). Both SDA and SCL idle high when the bus is not busy. START and STOP Conditions The master initiates a transmission with a START condition (S), a high-to-low transition on SDA with SCL high. The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA, while ______________________________________________________________________________________ 11 MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs SCL is high (Figure 5). A repeated START condition (Sr) can be used in place of a STOP condition to leave the bus active and in its current timing mode (see the HSMode section). Acknowledge Bits Successful data transfers are acknowledged with an acknowledge bit (A) or a not-acknowledge bit (A). Both the master and the MAX1036–MAX1039 (slave) generate acknowledge bits. To generate an “acknowledge,” the receiving device must pull SDA low before the rising edge of the acknowledge related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 6). To generate a “not acknowledge,” the receiver allows SDA to be pulled high before the rising edge of the acknowledge related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by a slave address. When idle, the MAX1036–MAX1039 continuously wait for a START condition followed by their slave address. When the MAX1036–MAX1039 recognize their slave address, they are ready to accept or send data. The slave address has been factory programmed and is always 1100100 for the MAX1036/ MAX1037, and 1100101 for MAX1038/ MAX1039 (Figure 7). The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MAX1036–MAX1039 (R/W = zero selects a write condition. R/W = 1 selects a read condition). After receiving the address, the MAX1036– MAX1039 (slave) issue an acknowledge by pulling SDA low for one clock cycle. Bus Timing At power-up, the MAX1036–MAX1039 bus timing defaults to fast mode (F/S-mode) allowing conversion rates up to 44ksps. The MAX1036–MAX1039 must operate in high-speed mode (HS-mode) to achieve conversion rates up to 188ksps. Figure 1 shows the bus timing for the MAX1036–MAX1039’s 2-wire interface. HS-Mode At power-up, the MAX1036–MAX1039 bus timing is set for F/S-mode. The master selects HS-mode by addressing all devices on the bus with the HS-mode master 12 S P Sr SDA SCL Figure 5. START and STOP Conditions S NOT ACKNOWLEDGE SDA ACKNOWLEDGE SCL 1 2 8 9 Figure 6. Acknowledge Bits code 0000 1XXX (X = Don’t care). After successfully receiving the HS-mode master code, the MAX1036– MAX1039 issues a not acknowledge, allowing SDA to be pulled high for one clock cycle (Figure 8). After the not acknowledge, the MAX1036–MAX1039 are in HS-mode. The master must then send a repeated START followed by a slave address to initiate HS-mode communication. If the master generates a STOP condition, the MAX1036–MAX1039 return to F/S-mode. Configuration/Setup Bytes (Write Cycle) Write cycles begin with the master issuing a START condition followed by 7 address bits (Figure 7) and 1 write bit (R/W = zero). If the address byte is successfully received, the MAX1036–MAX1039 (slave) issue an acknowledge. The master then writes to the slave. The slave recognizes the received byte as the setup byte (Table 1) if the most significant bit (MSB) is 1. If the MSB is zero, the slave recognizes that byte as the configuration byte (Table 2). The master can write either 1 or 2 bytes to the slave in any order (setup byte then configuration byte; configuration byte then setup byte; setup byte only; configuration byte only; Figure 9). If the slave receives bytes successfully, it issues an acknowledge. The master ends the write cycle by issuing a STOP condition or a repeated START condition. When operating in HS-mode, a STOP condition returns the bus to F/S-mode (see the HS-Mode section). Data Byte (Read Cycle) A read cycle must be initiated to obtain conversion results. Read cycles begin with the bus master issuing ______________________________________________________________________________________ 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs SLAVE ADDRESS MAX1036/MAX1037 1100100 MAX1038/MAX1039 1100101 MAX1036–MAX1039 DEVICE SLAVE ADDRESS S 1 1 0 0 1 0 0 R/W A SDA 1 SCL 2 3 4 5 6 7 8 9 Figure 7. MAX1036/MAX1037 Slave Address Byte HS-MODE MASTER CODE S 0 0 0 0 1 X X X A Sr SDA SCL F/S-MODE HS-MODE Figure 8. F/S-Mode to HS-Mode Transfer a START condition followed by 7 address bits and a read bit (R/W = 1). If the address byte is successfully received, the MAX1036–MAX1039 (slave) issue an acknowledge. The master then reads from the slave. After the master has received the results, it can issue an acknowledge if it wants to continue reading or a not acknowledge if it no longer wishes to read. If the MAX1036–MAX1039 receive a not acknowledge, they release SDA allowing the master to generate a STOP or repeated START. See the Clock Mode and Scan Mode sections for detailed information on how data is obtained and converted. Clock Mode The clock mode determines the conversion clock, the acquisition time, and the conversion time. The clock mode also affects the scan mode. The state of the setup byte’s CLK bit determines the clock mode (Table 1). At power-up, the MAX1036–MAX1039 default to internal clock mode (CLK = zero). Internal Clock When configured for internal clock mode (CLK = zero), the MAX1036–MAX1039 use their internal oscillator as the conversion clock. In internal clock mode, the MAX1036–MAX1039 begin tracking analog input on the ninth falling clock edge of a valid slave address byte. Two internal clock cycles later, the analog signal is acquired and the conversion begins. While tracking and converting the analog input signal, the MAX1036–MAX1039 hold SCL low (clock stretching). After the conversion completes, the results are stored ______________________________________________________________________________________ 13 MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs MASTER TO SLAVE SLAVE TO MASTER A. 1-BYTE WRITE CYCLE 1 S 7 1 1 SLAVE ADDRESS 8 1 1 NUMBER OF BITS SETUP OR W A A P OR Sr CONFIGURATION BYTE MSB DETERMINES WHETHER SETUP OR CONFIGURATION BYTE B. 2-BYTE WRITE CYCLE 1 S 7 1 1 SLAVE ADDRESS 8 SETUP OR W A CONFIGURATION BYTE 1 A 8 1 1 NUMBER OF BITS SETUP OR A P OR Sr CONFIGURATION BYTE MSB DETERMINES WHETHER SETUP OR CONFIGURATION BYTE Figure 9. Write Cycle in random access memory (RAM). If the scan mode is set for multiple conversions, they all happen in succession with each additional result being stored in RAM. The MAX1036/MAX1037 contain 8 bytes of RAM, and the MAX1038/MAX1039 contain 12 bytes of RAM. Once all conversions are complete, the MAX1036–MAX1039 release SCL, allowing it to be pulled high. The master can now clock the results out of the output shift register at a clock rate of up to 1.7MHz. SCL is stretched for a maximum acquisition and conversion time of 7.6µs per channel (Figure 10). The device RAM contains all of the conversion results when the MAX1036–MAX1039 release SCL. The converted results are read back in a first-in-first-out (FIFO) sequence. If AIN_/REF is set to be a reference input or output (SEL1 = 1, Table 6), AIN_/REF is excluded from a multichannel scan. RAM contents can be read continuously. If reading continues past the last result stored in RAM, the pointer wraps around and points to the first result. Note that only the current conversion results are read from memory. The device must be addressed with a read command to obtain new conversion results. The internal clock mode’s clock stretching quiets the SCL bus signal, reducing the system noise during conversion. Using the internal clock also frees the master (typically a microcontroller) from the burden of running the conversion clock. 14 External Clock When configured for external clock mode (CLK = 1), the MAX1036–MAX1039 use SCL as the conversion clock. In external clock mode, the MAX1036–MAX1039 begin tracking the analog input on the seventh falling clock edge of a valid slave address byte. One SCL clock cycle later, the analog signal is acquired and the conversion begins. Unlike internal clock mode, converted data is available immediately after the slave-address acknowledge bit. The device continuously converts input channels dictated by the scan mode until given a not acknowledge. There is no need to readdress the device with a read command to obtain new conversion results (Figure 11). The conversion must complete in 9ms or droop on the T/H capacitor degrades conversion results. Use internal clock mode if the SCL clock period exceeds 1ms. The MAX1036–MAX1039 must operate in external clock mode for conversion rates up to 188ksps. Scan Mode SCAN0 and SCAN1 of the configuration byte set the scan mode configuration. Table 5 shows the scanning configurations. If AIN_/REF is set to be a reference input or output (SEL1 = 1, Table 6), AIN_/REF is excluded from a multichannel scan. ______________________________________________________________________________________ 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGL/DIF BIT NAME 7 REG 6 SCAN1 5 SCAN0 4 CS3 3 CS2 2 CS1 1 CS0 0 SGL/DIF DESCRIPTION Register bit. 1 = Setup Byte (Table 1), 0 = Configuration Byte. Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up. Channel select bits. Four bits select which analog input channels are to be used for conversion (Tables 3, 4). Default to 0000 at power-up. For MAX1036/MAX1037, CS3 and CS2 are internally set to 0. 1 = single-ended, 0 = pseudo-differential (Tables 3, 4). Default to 1 at power-up (see the SingleEnded/Pseudo-Differential Input section). Applications Information Power-On Reset The configuration and setup registers (Tables 1 and 2) default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the reference and AIN_/REF configured as an analog input. The RAM contents are unknown after power-up. Automatic Shutdown SEL[2:0] of the setup byte (Tables 1 and 6) controls the state of the reference and AIN_/REF. If automatic shutdown is selected (SEL[2:0] = 100), shutdown occurs between conversions when the MAX1036–MAX1039 are idle. When operating in external clock mode, a STOP condition must be issued to place the devices in idle mode and benefit from automatic shutdown. A STOP condition is not necessary in internal clock mode to benefit from automatic shutdown because power-down occurs once all contents are written to memory (Figure 10). All analog circuitry is inactive in shutdown and supply current is less than 1µA. The digital conversion results are maintained in RAM during shutdown and are available for access through the serial interface at any time prior to a STOP or repeated START condition. When idle, the MAX1036–MAX1039 wait for a START condition followed by their slave address (see the Slave Address section). Upon reading a valid address byte, the MAX1036–MAX1039 power up. The analog circuits do not require any wakeup time from shutdown, whether using external or internal reference. Automatic shutdown results in dramatic power savings, particularly at slow conversion rates. For example, at a conversion rate of 10ksps, the average supply current for the MAX1036 is 8µA and drops to 2µA at 1ksps. At 0.1ksps the average supply current is just 1µA (see Average Supply Current vs. Conversion Rate in the Typical Operating Characteristics section). Reference Voltage SEL[2:0] of the setup byte (Table 1) controls the reference and the AIN_/REF configuration (Table 6). When AIN_/REF is configured to be a reference input or reference output (SEL1 = 1), conversions on AIN_/REF appear as if AIN_/REF is connected to GND (see Note 2 of Tables 3 and 4). Internal Reference The internal reference is 4.096V for the MAX1036/ MAX1038 and 2.048V for the MAX1037/MAX1039. SEL1 of the setup byte controls whether AIN_/REF is used for an analog input or a reference (Table 6). When AIN_/REF is configured to be an internal reference output (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01µF capacitor. Due to the decoupling capacitor and the 675Ω reference source impedance, allow 80µs for the reference to stabilize during initial power-up. Once powered up, the reference always remains on until reconfigured. The reference should not be used to supply current for external circuitry. ______________________________________________________________________________________ 15 MAX1036–MAX1039 Table 2. Configuration Byte Format MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs MASTER TO SLAVE SLAVE TO MASTER A. SINGLE CONVERSION WITH INTERNAL CLOCK 1 7 8 1 1 S SLAVE ADDRESS R A RESULT CLOCK STRETCH tACQ 1 1 NUMBER OF BITS A P or Sr tCONV B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK 7 1 1 1 8 S SLAVE ADDRESS R A CLOCK STRETCH CLOCK STRETCH tACQ1 tACQ2 tCONV2 tCONV1 1 8 1 8 RESULT 1 A RESULT 2 A 1 1 NUMBER OF BITS RESULT N A P OR Sr tACQN tCONVN NOTE: tACQ + tCONV ≤ 7.6µs PER CHANNEL. Figure 10. Internal Clock Mode Read Cycles MASTER TO SLAVE SLAVE TO MASTER A. SINGLE CONVERSION WITH EXTERNAL CLOCK 1 7 1 1 8 1 1 S SLAVE ADDRESS R A RESULT A P OR Sr tACQ NUMBER OF BITS tCONV B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK 1 S 7 1 1 SLAVE ADDRESS R A 8 1 RESULT 1 A tACQ1 tCONV1 8 1 RESULT 2 A tACQ2 tCONV2 8 RESULT N 1 1 NUMBER OF BITS A P OR Sr tACQN tCONVN Figure 11. External Clock Mode Read Cycles 16 ______________________________________________________________________________________ 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs CS31 CS21 CS1 CS0 AIN0 0 0 0 0 + 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 RESERVED 1 1 0 1 RESERVED 1 1 1 0 RESERVED 1 1 1 1 RESERVED AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN112 GND - + + + + + + + + + + + - Note 1: For MAX1036/MAX1037, CS3 and CS2 are internally set to zero. Note 2: When SEL1 = 1, a single-ended read of AIN3/REF (MAX1036/MAX1037) or AIN11/REF (MAX1038/MAX1039) returns GND. ______________________________________________________________________________________ 17 MAX1036–MAX1039 Table 3. Channel Selection in Single-Ended Mode (SGL / DIF = 1) MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs Table 4. Channel Selection in Pseudo-Differential Mode (SGL / DIF = 0) CS31 CS21 CS1 CS0 AIN0 AIN1 0 0 0 0 + - 0 0 0 1 - + 0 0 1 0 + - 0 0 1 1 - + 0 1 0 0 + - 0 1 0 1 - + 0 1 1 0 1 1 0 1 AIN2 AIN32 AIN4 AIN5 AIN8 AIN9 AIN10 AIN112 AIN6 AIN7 0 + - 1 1 - + 0 0 + - 0 0 1 - + 1 0 1 0 + - 1 0 1 1 - + 1 1 0 0 RESERVED 1 1 0 1 RESERVED 1 1 1 0 RESERVED 1 1 1 1 RESERVED Note 1: For MAX1036/MAX1037, CS3 and CS2 are internally set to zero. Note 2: When SEL1 =1, a pseudo-differential read between AIN2 and AIN3/REF (MAX1036/MAX1037) or AIN10 and AIN11/REF (MAX1038/MAX1039) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011 returns the negative difference between AIN10 and GND. Note 3: When scanning multiple channels (SCAN0 = 0), CS0 = 0 causes the even-numbered channel-select bits to be scanned, while CS0 = 1 causes the odd-numbered channel-select bits to be scanned. For example, if the MAX1038/MAX1039 SCAN[1:0] = 00 and CS[3:0] = 1010, a differential read returns AIN0–AIN1, AIN2–AIN3, AIN4–AIN5, AIN6–AIN7, AIN8–AIN9, and AIN10–AIN11. If the MAX1038/MAX1039 SCAN[1:0] = 00 and CS[3:0] = 1011, a differential read returns AIN1–AIN0, AIN3–AIN2, AIN5–AIN4, AIN7–AIN6, AIN9–8, and AIN11–AIN10. 18 ______________________________________________________________________________________ 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs SCAN1 SCAN0 SCANNING CONFIGURATION 0 0 Scans up from AIN0 to the input selected by CS3–CS0 (default setting). 0 1 Converts the input selected by CS3–CS0 eight times.* Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0–AIN2, the scanning stops at AIN2 (MAX1036/MAX1037). 1 0 Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6 scanning stops at AIN6 (MAX1038/MAX1039). 1 1 Converts the channel selected by CS3–CS0.* *When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11 and converting continues until a not acknowledge occurs. Table 6. Reference Voltage and AIN_/REF Format REFERENCE VOLTAGE AIN_/REF INTERNAL REFERENCE STATE SEL2 SEL1 SEL0 0 0 X VDD Analog input Always Off 0 1 X External reference Reference input Always Off 1 0 0 Internal reference Analog input Auto Shutdown 1 0 1 Internal reference Analog input Always On 1 1 X Internal reference Reference output Always On X = Don’t care. External Reference The external reference can range from 1.0V to VDD. For maximum conversion accuracy, the reference must be able to deliver up to 30µA and have an output impedance of 1kΩ or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close to AIN_/REF as possible with a 0.1µF capacitor. Transfer Functions Output data coding for the MAX1036–MAX1039 is binary in unipolar mode and two’s complement binary in bipolar mode with 1LSB = (VREF/2N) where N is the number of bits (8). Code transitions occur halfway between successive-integer LSB values. Figures 12 and 13 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. Layout, Grounding, and Bypassing For best performance, use PC boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only one star point (Figure 14) con- necting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground’s power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC’s fast comparator. Bypass V DD to the star ground with a 0.1µF capacitor located as close as possible to the MAX1036–MAX1039 power-supply pin. Minimize capacitor lead length for best supply-noise rejection, and add an attenuation resistor (5Ω) if the power supply is extremely noisy. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The INL is measured using the endpoint method. ______________________________________________________________________________________ 19 MAX1036–MAX1039 Table 5. Scanning Configuration MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs OUTPUT CODE 1LSB = OUTPUT CODE (TWO'S COMPLEMENT) VREF 256 1LSB = VREF 256 REF 0...111 0...110 0...101 0...100 REF 1...111 1...110 1...101 1...100 0...001 0...000 1...111 1...011 1...010 1...001 1...000 0...011 0...010 0...001 0...000 0 1 2 3 252 253 254 255 256 -128 -127 -126 -125 -1 0 +1 +124 +125 +126 +127 +128 '-' INPUT INPUT VOLTAGE (LSB) INPUT VOLTAGE (LSB) Figure 12. Unipolar Transfer Function Figure 13. Bipolar Transfer Function Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. SUPPLIES 3V/5V VLOGIC = 3V/5V GND Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. R* = 5Ω Aperture Delay 0.1µF VDD GND MAX1036 MAX1037 MAX1038 MAX1039 3V/5V DGND DIGITAL CIRCUITRY *OPTIONAL Figure 14. Power-Supply and Grounding Connections 20 Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 ✕ N + 1.76)dB ______________________________________________________________________________________ 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to RMS equivalent of all other ADC output signals. SINAD (dB) = 20 ✕ log (SignalRMS / NoiseRMS) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the ADC’s full-scale range, calculate the ENOB as follows: ENOB = (SINAD - 1.76) / 6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal’s first five harmonics to the fundamental itself. This is expressed as: 2 2 2 2 THD = 20 × log V2 + V3 + V4 + V5 / V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component. Chip Information MAX1036/MAX1037 TRANSISTOR COUNT: 6283 MAX1038/MAX1039 TRANSISTOR COUNT: 7257 PROCESS: BiCMOS Pin Configurations Typical Operating Circuit 5V TOP VIEW AIN0 1 8 VDD AIN1 2 7 GND 6 SDA 5 SCL AIN2 3 MAX1036 MAX1037 AIN3/REF 4 VDD ANALOG INPUTS AIN0 AIN1 AIN2 AIN3/REF *RS MAX1036 MAX1037 MAX1038 MAX1039 SDA SCL *RS GND 5V SOT23 RP 5V AIN7 1 16 AIN8 AIN6 2 15 AIN9 AIN5 3 14 AIN10 AIN4 4 AIN3 5 MAX1038 MAX1039 RP µC SDA SCL 13 AIN11/REF 12 VDD AIN2 6 11 GND AIN1 7 10 SDA AIN0 8 9 *OPTIONAL SCL QSOP ______________________________________________________________________________________ 21 MAX1036–MAX1039 In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Package Information SOT23, 8L.EPS (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) QSOP.EPS MAX1036–MAX1039 2.7V to 5.5V, Low-Power, 4-/12-Channel 2-Wire Serial 8-Bit ADCs Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.