19-4560; Rev 1; 7/09 KIT ATION EVALU E L B AVAILA 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs The MAX11606–MAX11611 low-power, 10-bit, multichannel analog-to-digital converters (ADCs) feature internal track/hold (T/H), voltage reference, clock, and an I2C-compatible 2-wire serial interface. These devices operate from a single supply of 2.7V to 3.6V (MAX11607/ MAX11609/MAX11611) or 4.5V to 5.5V (MAX11606/ MAX11608/MAX11610) and require only 670µA at the maximum sampling rate of 94.4ksps. Supply current falls below 230µA for sampling rates under 46ksps. AutoShutdown™ powers down the devices between conversions, reducing supply current to less than 1µA at low throughput rates. The MAX11606/MAX11607 have 4 analog input channels each, the MAX11608/MAX11609 have 8 analog input channels each, while the MAX11610/MAX11611 have 12 analog input channels each. The fully differential analog inputs are software configurable for unipolar or bipolar, and single ended or differential operation. The full-scale analog input range is determined by the internal reference or by an externally applied reference voltage ranging from 1V to V DD . The MAX11607/ MAX11609/MAX11611 feature a 2.048V internal reference and the MAX11606/MAX11608/MAX11610 feature a 4.096V internal reference. The MAX11606/MAX11607 are available in an 8-pin µMAX® package. The MAX11608–MAX11611 are available in a 16-pin QSOP package. The MAX11606– MAX11611 are guaranteed over the extended temperature range (-40°C to +85°C). For pin-compatible 12-bit parts, refer to the MAX11612–MAX11617 data sheet. For pin-compatible 8-bit parts, refer to the MAX11600– MAX11605 data sheet. Features o High-Speed I2C-Compatible Serial Interface o o o o o o o o o o o 400kHz Fast Mode 1.7MHz High-Speed Mode Single-Supply 2.7V to 3.6V (MAX11607/MAX11609/MAX11611) 4.5V to 5.5V (MAX11606/MAX11608/MAX11610) Internal Reference 2.048V (MAX11607/MAX11609/MAX11611) 4.096V (MAX11606/MAX11608/MAX11610) External Reference: 1V to VDD Internal Clock 4-Channel Single-Ended or 2-Channel Fully Differential (MAX11606/MAX11607) 8-Channel Single-Ended or 4-Channel Fully Differential (MAX11608/MAX11609) 12-Channel Single-Ended or 6-Channel Fully Differential (MAX11610/MAX11611) Internal FIFO with Channel-Scan Mode Low Power 670µA at 94.4ksps 230µA at 40ksps 60µA at 10ksps 6µA at 1ksps 0.5µA in Power-Down Mode Software-Configurable Unipolar/Bipolar Small Packages 8-Pin µMAX (MAX11606/MAX11607) 16-Pin QSOP (MAX11608–MAX11611) Ordering Information Applications Handheld Portable Applications Medical Instruments Battery-Powered Test Equipment Solar-Powered Remote Systems Received-Signal-Strength Indicators System Supervision PART TEMP RANGE PINI2C SLAVE PACKAGE ADDRESS MAX11606EUA+ -40°C to +85°C 8 µMAX 0110100 MAX11607EUA+ -40°C to +85°C 8 µMAX 0110100 MAX11608EEE+ -40°C to +85°C 16 QSOP 0110011 MAX11609EEE+ -40°C to +85°C 16 QSOP 0110011 MAX11610EEE+ -40°C to +85°C 16 QSOP 0110101 MAX11611EEE+ -40°C to +85°C 16 QSOP 0110101 +Denotes a lead(Pb)-free/RoHs-compliant package. AutoShutdown is a trademark of Maxim Integrated Products, Inc. µMAX is a registered trademark of Maxim Integrated Products, Inc. Pin Configurations, Typical Operating Circuit, and Selector Guide appear at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX11606–MAX11611 General Description MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V AIN0–AIN11, REF to GND ............-0.3V to the lower of (VDD + 0.3V) and 6V SDA, SCL to GND.....................................................-0.3V to +6V Maximum Current into Any Pin .........................................±50mA Continuous Power Dissipation (TA = +70°C) 8-Pin µMAX (derate 4.5mW/°C above +70°C) .............362mW 16-Pin QSOP (derate 8.3mW/°C above +70°C)........666.7mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-60°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VDD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF = 2.048V (MAX11607/MAX11609/MAX11611), VREF = 4.096V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 1) Resolution 10 Bits Relative Accuracy INL (Note 2) ±1 LSB Differential Nonlinearity DNL No missing codes over temperature ±1 LSB ±1 LSB Offset Error Offset-Error Temperature Coefficient Relative to FSR Gain Error (Note 3) Gain-Temperature Coefficient Relative to FSR 0.3 ppm/°C ±1 LSB 0.3 ppm/°C Channel-to-Channel Offset Matching ±0.1 LSB Channel-to-Channel Gain Matching ±0.1 LSB 60 dB DYNAMIC PERFORMANCE (fIN(SINE-WAVE) = 10kHz, VIN(P-P) = VREF, fSAMPLE = 94.4ksps) Signal-to-Noise Plus Distortion SINAD Total Harmonic Distortion THD Spurious Free Dynamic Range SFDR Up to the 5th harmonic -70 dB 70 dB Full-Power Bandwidth SINAD > 57dB 3.0 MHz Full-Linear Bandwidth -3dB point 5.0 MHz CONVERSION RATE Conversion Time (Note 4) Throughput Rate tCONV fSAMPLE Internal clock External clock 6.8 10.6 Internal clock, SCAN[1:0] = 01 53 Internal clock, SCAN[1:0] = 00 CS[3:0] = 1011 (MAX11610/MAX11611) 53 External clock Track/Hold Acquisition Time 2 µs ksps 94.4 800 _______________________________________________________________________________________ ns 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs (VDD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF = 2.048V (MAX11607/MAX11609/MAX11611), VREF = 4.096V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.) PARAMETER SYMBOL CONDITIONS MIN Internal Clock Frequency Aperture Delay (Note 5) TYP MAX 2.8 tAD External clock, fast mode 60 External clock, high-speed mode 30 UNITS MHz ns ANALOG INPUT (AIN0–AIN11) Input-Voltage Range, SingleEnded and Differential (Note 6) Unipolar 0 VREF Bipolar 0 ±VREF/2 Input Multiplexer Leakage Current On/off leakage current, VAIN_ = 0 or VDD Input Capacitance ±0.01 CIN ±1 22 V µA pF INTERNAL REFERENCE (Note 7) Reference Voltage VREF Reference-Voltage Temperature Coefficient TA = +25°C MAX11607/MAX11609/MAX11611 1.968 2.048 2.128 MAX11606/MAX11608/MAX11610 3.939 4.096 4.256 TCVREF 25 REF Short-Circuit Current ppm/°C 2 REF Source Impedance V 1.5 mA kΩ EXTERNAL REFERENCE REF Input-Voltage Range VREF (Note 8) REF Input Current IREF fSAMPLE = 94.4ksps 1 VDD V 40 µA DIGITAL INPUTS/OUTPUTS (SCL, SDA) Input High Voltage VIH Input Low Voltage VIL Input Hysteresis 0.7 x VDD 0.1 x VDD VHYST Input Current IIN Input Capacitance CIN Output Low Voltage VOL V 0.3 x VDD V V ±10 VIN = 0 to VDD 15 ISINK = 3mA µA pF 0.4 V POWER REQUIREMENTS Supply Voltage Supply Current VDD IDD MAX11607/MAX11609/MAX11611 2.7 3.6 MAX11606/MAX11608/MAX11610 4.5 5.5 fSAMPLE = 94.4ksps external clock Internal reference 900 1150 fSAMPLE = 40ksps internal clock External reference 670 900 Internal reference 530 External reference 230 fSAMPLE = 10ksps internal clock Internal reference 380 External reference 60 fSAMPLE =1ksps internal clock Internal reference 330 External reference Shutdown (internal reference off) V µA 6 0.5 10 _______________________________________________________________________________________ 3 MAX11606–MAX11611 ELECTRICAL CHARACTERISTICS (continued) MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF = 2.048V (MAX11607/MAX11609/MAX11611), VREF = 4.096V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ±0.01 ±0.5 LSB/V POWER REQUIREMENTS Power-Supply Rejection Ratio PSRR Full-scale input (Note 9) TIMING CHARACTERISTICS (Figure 1) (VDD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF = 2.048V (MAX11607/MAX11609/MAX11611), VREF = 4.096V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 400 kHz TIMING CHARACTERISTICS FOR FAST MODE Serial-Clock Frequency fSCL Bus Free Time Between a STOP (P) and a START (S) Condition tBUF 1.3 µs tHD,STA 0.6 µs Low Period of the SCL Clock tLOW 1.3 µs High Period of the SCL Clock tHIGH 0.6 µs Setup Time for a Repeated START Condition (Sr) tSU,STA 0.6 µs Data Hold Time tHD,DAT Data Setup Time tSU,DAT Hold Time for START (S) Condition (Note 10) 0 900 100 ns ns Rise Time of Both SDA and SCL Signals, Receiving tR Measured from 0.3VDD to 0.7VDD 20 + 0.1CB 300 ns Fall Time of SDA Transmitting tF Measured from 0.3VDD to 0.7VDD (Note 11) 20 + 0.1CB 300 ns Setup Time for STOP (P) Condition tSU,STO Capacitive Load for Each Bus Line CB 0.6 400 pF µs Pulse Width of Spike Suppressed tSP 50 ns 1.7 MHz TIMING CHARACTERISTICS FOR HIGH-SPEED MODE (CB = 400pF, Note 12) Serial-Clock Frequency 4 fSCLH (Note 13) Hold Time, Repeated START Condition (Sr) tHD,STA 160 ns Low Period of the SCL Clock tLOW 320 ns High Period of the SCL Clock tHIGH 120 ns Setup Time for a Repeated START Condition (Sr) tSU,STA 160 ns Data Hold Time tHD,DAT Data Setup Time tSU,DAT (Note 10) 0 10 _______________________________________________________________________________________ 150 ns ns 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs (VDD = 2.7V to 3.6V (MAX11607/MAX11609/MAX11611), VDD = 4.5V to 5.5V (MAX11606/MAX11608/MAX11610), VREF = 2.048V (MAX11607/MAX11609/MAX11611), VREF = 4.096V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C. See Tables 1–5 for programming notation.) PARAMETER SYMBOL CONDITIONS MAX UNITS 20 80 ns Measured from 0.3VDD to 0.7VDD 20 160 ns tFCL Measured from 0.3VDD to 0.7VDD 20 80 ns Rise Time of SDA Signal tRDA Measured from 0.3VDD to 0.7VDD 20 160 ns Fall Time of SDA Signal tFDA Measured from 0.3VDD to 0.7VDD (Note 11) 20 160 ns 400 pF 10 ns Rise Time of SCL Signal (Current Source Enabled) tRCL Measured from 0.3VDD to 0.7VDD Rise Time of SCL Signal after Acknowledge Bit tRCL1 Fall Time of SCL Signal Setup Time for STOP (P) Condition tSU,STO Capacitive Load for Each Bus Line CB Pulse Width of Spike Suppressed tSP MIN TYP 160 (Notes 10 and 13) 0 ns Note 1: For DC accuracy, the MAX11606/MAX11608/MAX11610 are tested at VDD = 5V and the MAX11607/MAX11609/MAX11611 are tested at VDD = 3V. All devices are configured for unipolar, single-ended inputs. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and offsets have been calibrated. Note 3: Offset nulled. Note 4: Conversion time is defined as the number of clock cycles needed for conversion multiplied by the clock period. Conversion time does not include acquisition time. SCL is the conversion clock in the external clock mode. Note 5: A filter on the SDA and SCL inputs suppresses noise spikes and delays the sampling instant. Note 6: The absolute input-voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD. Note 7: When the internal reference is configured to be available at AIN_/REF (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit). Note 8: ADC performance is limited by the converter’s noise floor, typically 300µVP-P. Note 9: Measured as follows for the MAX11607/MAX11609/MAX11611: ⎡ 2N − 1⎤ ⎢[VFS (3.6V) − VFS (2.7V)] × ⎥ VREF ⎦ ⎣ (3.6V − 2.7V) and for the MAX11606/MAX11608/MAX11610, where N is the number of bits: ⎡ 2N − 1⎤ ⎢[VFS (5.5V) − VFS (4.5V)] × ⎥ VREF ⎦ ⎣ (5.5V − 4.5V) Note 10: A master device must provide a data hold time for SDA (referred to VIL of SCL) to bridge the undefined region of SCL’s falling edge (see Figure 1). Note 11: The minimum value is specified at TA = +25°C. Note 12: CB = total capacitance of one bus line in pF. Note 13: fSCL must meet the minimum clock low time plus the rise/fall times. _______________________________________________________________________________________ 5 MAX11606–MAX11611 TIMING CHARACTERISTICS (Figure 1) (continued) Typical Operating Characteristics (VDD = 3.3V (MAX11607/MAX11609/MAX11611), VDD = 5V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25°C, unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL CODE 0.4 0.3 -40 -0.1 AMPLITUDE (dBc) INL (LSB) 0 0.1 0 -0.1 -0.2 -0.3 200 400 600 800 400 600 800 0 1000 20k 30k 40k FREQUENCY (Hz) SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 0.40 0.4 0.3 0.2 MAX11611/MAX11609/ EXTERNAL REFERENCE MAX11607 MAX11606 toc06 0.45 SUPPLY CURRENT (μA) 0.5 50k 0.50 MAX11606 toc05 SDA = SCL = VDD IDD (μA) SETUP BYTE EXT REF: 10111011 INT REF: 11011011 MAX11611/MAX11609/ MAX11607 INTERNAL REFERENCE MAX11610/MAX11608/ EXTERNAL REFERENCE MAX11606 0.6 MAX11606 toc04 MAX11610/MAX11608/ MAX11606 INTERNAL REFERENCE MAX11610/MAX11608/MAX11606 0.35 0.30 0.25 0.20 0.15 MAX11611/MAX11609/MAX11607 0.10 0.1 350 0.05 0 0 -40 -25 -10 5 20 35 50 65 80 3.2 2.7 TEMPERATURE (°C) 3.7 4.2 4.7 A 800 MAX11606 toc07 A) INTERNAL REFERENCE ALWAYS ON B) EXTERNAL REFERENCE 20 35 AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (EXTERNAL CLOCK) A) INTERNAL REFERENCE ALWAYS ON B) EXTERNAL REFERENCE 700 A B AVERAGE IDD (µA) AVERAGE IDD (μA) 5 600 500 B 400 300 MAX11610/MAX11608/MAX11606 0 10 20 30 40 50 60 70 80 90 100 CONVERSION RATE (ksps) 50 TEMPERATURE (°C) SUPPLY VOLTAGE (V) AVERAGE SUPPLY CURRENT vs. CONVERSION RATE (EXTERNAL CLOCK) 800 750 700 650 600 550 500 450 400 350 300 250 200 -40 -25 -10 5.2 MAX11606 toc08 300 6 10k DIGITAL OUTPUT CODE 450 400 200 DIGITAL OUTPUT CODE 700 500 -160 0 1000 800 550 -100 -140 -0.5 0 600 -80 -120 -0.4 650 -60 -0.3 -0.2 750 fSAMPLE = 94.4ksps fIN = 10kHz -20 0.2 0.1 DNL (LSB) 0 MAX11606 toc02 0.2 FFT PLOT 0.5 MAX11606 toc01 0.3 MAX11606 toc03 DIFFERENTIAL NONLINEARITY vs. DIGITAL CODE SUPPLY CURRENT (μA) MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX11611/MAX11609/MAX11607 200 0 20 40 60 80 CONVERSATION RATE (ksps) _______________________________________________________________________________________ 100 65 80 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs 1.0008 NORMALIZED TO REFERENCE VALUE TA = +25°C MAX11610/MAX11608/MAX11606 1.0002 1.0000 0.9998 0.9996 MAX11610/11608/MAX11606, NORMALIZED TO REFERENCE VALUE AT VDD = 5V 1.00008 1.00006 VREF NORMALIZED 1.0004 1.00004 1.00002 1.00000 0.99998 0.99996 0.9994 MAX11611/11609/MAX11607, NORMALIZED TO REFERENCE VALUE AT VDD = 3.3V 0.99994 MAX11611/MAX11609/MAX11607 0.9992 0.99992 0.9990 0.99990 -40 -25 -10 5 20 35 50 65 80 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 TEMPERATURE (°C) VDD (V) OFFSET ERROR vs. SUPPLY VOLTAGE OFFSET ERROR vs. TEMPERATURE -0.1 -0.2 OFFSET ERROR (LSB) -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 MAX11606 toc12 -0.1 OFFSET ERROR (LSB) 0 MAX11606 toc11 0 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.8 -0.9 -0.9 -1.0 -1.0 -40 -25 -10 5 20 35 50 65 2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 80 VDD (V) TEMPERATURE (°C) GAIN ERROR vs. TEMPERATURE GAIN ERROR vs. SUPPLY VOLTAGE 0.9 0.8 0.9 0.8 GAIN ERROR (LSB) 0.7 0.6 0.5 0.4 0.3 MAX11606 toc14 1.0 MAX11606 toc13 1.0 GAIN ERROR (LSB) VREF NORMALIZED 1.0006 1.00010 MAX11606 toc09 1.0010 MAX11606 toc10 NORMALIZED REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE 0.7 0.6 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 0 -40 -25 -10 5 20 35 50 TEMPERATURE (°C) 65 80 2.7 3.2 3.7 4.2 4.7 5.2 VDD (V) _______________________________________________________________________________________ 7 MAX11606–MAX11611 Typical Operating Characteristics (continued) (VDD = 3.3V (MAX11607/MAX11609/MAX11611), VDD = 5V (MAX11606/MAX11608/MAX11610), fSCL = 1.7MHz, external clock, fSAMPLE = 94.4ksps, single-ended, unipolar, TA = +25°C, unless otherwise noted.) 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX11606–MAX11611 Pin Description PIN MAX11606 MAX11607 MAX11608 MAX11609 MAX11610 MAX11611 NAME 1, 2, 3 5, 6, 7 5, 6, 7 AIN0, AIN1, AIN2 — 8–12 8–12 AIN3–AIN7 — — 4, 3, 2 AIN8–AIN10 4 — — AIN3/REF Analog Input 3/Reference Input or Output. Selected in the setup register (see Tables 1 and 6). — 1 — REF Reference Input or Output. Selected in the setup register (see Tables 1 and 6). — — 1 AIN11/REF 5 13 13 SCL 6 14 14 SDA Data Input/Output 7 15 15 GND Ground 8 16 16 VDD Positive Supply. Bypass to GND with a 0.1µF capacitor. — 2, 3, 4 — N.C. No Connection. Not internally connected. FUNCTION Analog Inputs Analog Input 11/Reference Input or Output. Selected in the setup register (see Tables 1 and 6). Clock Input A. F/S-MODE 2-WIRE SERIAL INTERFACE TIMING tR tF t SDA tSU.DAT tHD.DAT tLOW tHD.STA tBUF tSU.STA tSU.STO SCL tHD.STA tHIGH tR tF S A Sr P B. HS-MODE 2-WIRE SERIAL INTERFACE TIMING S tRDA tFDA SDA tSU.DAT tHD.DAT tLOW tBUF tHD.STA tSU.STO tSU.STA SCL tHD.STA tHIGH tRCL tFCL tRCL1 S Sr A P HS-MODE Figure 1. 2-Wire Serial-Interface Timing 8 _______________________________________________________________________________________ S F/S-MODE 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX11606–MAX11611 SDA SCL INPUT SHIFT REGISTER VDD SETUP REGISTER GND CONTROL LOGIC INTERNAL OSCILLATOR CONFIGURATION REGISTER AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11/REF T/H ANALOG INPUT MUX 10-BIT ADC OUTPUT SHIFT REGISTER AND RAM REF REFERENCE 4.096V (MAX11610) 2.048V (MAX11611) MAX11610 MAX11611 Figure 2. MAX11610/MAX11611 Functional Diagram 1.7MHz. Figure 2 shows the simplified internal structure for the MAX11610/MAX11611. VDD IOL Power Supply IOH The MAX11606–MAX11611 operates from a single supply and consumes 670µA (typ) at sampling rates up to 94.4ksps. The MAX11607/MAX11609/MAX11611 feature a 2.048V internal reference and the MAX11606/ MAX11608/MAX11610 feature a 4.096V internal reference. All devices can be configured for use with an external reference from 1V to VDD. VOUT SDA 400pF Analog Input and Track/Hold Figure 3. Load Circuit Detailed Description The MAX11606–MAX11611 analog-to-digital converters (ADCs) use successive-approximation conversion techniques and fully differential input track/hold (T/H) circuitry to capture and convert an analog signal to a serial 12-bit digital output. The MAX11606/MAX11607 are 4-channel ADCs, the MAX11608/MAX11609 are 8-channel ADCs, and the MAX11610/MAX11611 are 12-channel ADCs. These devices feature a high-speed 2-wire serial interface supporting data rates up to The MAX11606–MAX11611 analog-input architecture contains an analog-input multiplexer (mux), a fully differential track-and-hold (T/H) capacitor, T/H switches, a comparator, and a fully differential switched capacitive digital-to-analog converter (DAC) (Figure 4). In single-ended mode, the analog-input multiplexer connects C T/H between the analog input selected by CS[3:0] (see the Configuration/Setup Bytes (Write Cycle) section) and GND (Table 3). In differential mode, the analog- input multiplexer connects CT/H to the + and - analog inputs selected by CS[3:0] (Table 4). During the acquisition interval, the T/H switches are in the track position and CT/H charges to the analog input _______________________________________________________________________________________ 9 signal. At the end of the acquisition interval, the T/H switches move to the hold position retaining the charge on CT/H as a stable sample of the input signal. During the conversion interval, the switched capacitive DAC adjusts to restore the comparator input voltage to 0V within the limits of 10-bit resolution. This action requires 10 conversion clock cycles and is equivalent to transferring a charge of 11pF (VIN+ - VIN-) from CT/H to the binary weighted capacitive DAC, forming a digital representation of the analog input signal. clock pulse during the shifting out of the first byte of the result. The conversion is performed during the next 10 clock cycles. The time required for the T/H circuitry to acquire an input signal is a function of the input sample capacitance. If the analog-input source impedance is high, the acquisition time constant lengthens and more time must be allowed between conversions. The acquisition time (tACQ) is the minimum time needed for the signal to be acquired. It is calculated by: Sufficiently low source impedance is required to ensure an accurate sample. A source impedance of up to 1.5kΩ does not significantly degrade sampling accuracy. To minimize sampling errors with higher source impedances, connect a 100pF capacitor from the analog input to GND. This input capacitor forms an RC filter with the source impedance limiting the analog-input bandwidth. For larger source impedances, use a buffer amplifier to maintain analog-input signal integrity and bandwidth. When operating in internal clock mode, the T/H circuitry enters its tracking mode on the eighth rising clock edge of the address byte (see the Slave Address section). The T/H circuitry enters hold mode on the falling clock edge of the acknowledge bit of the address byte (the ninth clock pulse). A conversion or a series of conversions is then internally clocked and the MAX11606–MAX11611 holds SCL low. With external clock mode, the T/H circuitry enters track mode after a valid address on the rising edge of the clock during the read (R/W = 1) bit. Hold mode is then entered on the rising edge of the second tACQ ≥ 9 (RSOURCE + RIN) CIN where RSOURCE is the analog-input source impedance, RIN = 2.5kΩ, and CIN = 22pF. tACQ is 1.5/fSCL for internal clock mode and tACQ = 2/fSCL for external clock mode. Analog Input Bandwidth The MAX11606–MAX11611 feature input-tracking circuitry with a 5MHz small-signal bandwidth. The 5MHz input bandwidth makes it possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using under sampling techniques. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended. Analog Input Range and Protection Internal protection diodes clamp the analog input to VDD and GND. These diodes allow the analog inputs to HOLD ANALOG INPUT MUX REF CT/H AIN0 AIN1 HOLD AIN3/REF TRACK VDD/2 HOLD AIN2 CAPACITIVE DAC TRACK HOLD TRACK TRACK MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs CAPACITIVE DAC TRACK GND CT/H HOLD REF MAX11606 MAX11607 Figure 4. Equivalent Input Circuit 10 ______________________________________________________________________________________ 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs Single-Ended/Differential Input The SGL/DIF of the configuration byte configures the MAX11606–MAX11611 analog-input circuitry for singleended or differential inputs (Table 2). In single-ended mode (SGL/DIF = 1), the digital conversion results are the difference between the analog input selected by CS[3:0] and GND (Table 3). In differential mode (SGL/ DIF = 0), the digital conversion results are the difference between the + and the - analog inputs selected by CS[3:0] (Table 4). Unipolar/Bipolar When operating in differential mode, the BIP/UNI bit of the setup byte (Table 1) selects unipolar or bipolar operation. Unipolar mode sets the differential input range from 0 to VREF. A negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to ±VREF/2. The digital output code is binary in unipolar mode and two’s complement in bipolar mode. See the Transfer Functions section. In single-ended mode, the MAX11606–MAX11611 always operate in unipolar mode irrespective of BIP/UNI. The analog inputs are internally referenced to GND with a full-scale input range from 0 to VREF. 2-Wire Digital Interface The MAX11606–MAX11611 feature a 2-wire interface consisting of a serial-data line (SDA) and serial-clock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX11606–MAX11611 and the master at rates up to 1.7MHz. The MAX11606–MAX11611 are slaves that transfer and receive data. The master (typically a microcontroller) initiates data transfer on the bus and generates the SCL signal to permit that transfer. SDA and SCL must be pulled high. This is typically done with pullup resistors (750Ω or greater) (see the Typical Operating Circuit). Series resistors (RS) are optional. They protect the input architecture of the MAX11606– MAX11611 from high voltage spikes on the bus lines, minimize crosstalk, and undershoot of the bus signals. Bit Transfer One data bit is transferred during each SCL clock cycle. A minimum of 18 clock cycles are required to transfer the data in or out of the MAX11606– MAX11611. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy. START and STOP Conditions The master initiates a transmission with a START condition (S), a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), a low-to-high transition on SDA while SCL is high (Figure 5). A repeated START condition (Sr) can be used in place of a STOP condition to leave the bus active and the mode unchanged (see the HS Mode section). Sr S P SDA SCL Figure 5. START and STOP Conditions Acknowledge Bits Data transfers are acknowledged with an acknowledge bit (A) or a not-acknowledge bit (A). Both the master and the MAX11606–MAX11611 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 6). To generate a not-acknowledge, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. S NOT ACKNOWLEDGE SDA ACKNOWLEDGE SCL 1 2 8 9 Figure 6. Acknowledge Bits ______________________________________________________________________________________ 11 MAX11606–MAX11611 swing from (GND - 0.3V) to (VDD + 0.3V) without causing damage to the device. For accurate conversions the inputs must not go more than 50mV below GND or above VDD. MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs DEVICE SLAVE ADDRESS MAX11606/MAX11607 0110100 MAX11608/MAX11609 0110011 MAX11610/MAX11611 0110101 SLAVE ADDRESS MAX11606/MAX11607 S 0 1 1 0 1 0 0 R/W A SDA 1 SCL 2 3 4 5 6 7 8 9 Figure 7. MAX11606/MAX11607 Slave Address Byte Slave Address A bus master initiates communication with a slave device by issuing a START condition followed by a slave address. When idle, the MAX11606–MAX11611 continuously wait for a START condition followed by their slave address. When the MAX11606–MAX11611 recognize their slave address, they are ready to accept or send data. The slave address has been factory programmed and is always 0110100 for the MAX11606/MAX11607, 0110011 for the MAX11608/MAX11609, and 0110101 for MAX11610/MAX11611 (Figure 7). The least significant bit (LSB) of the address byte (R/W) determines whether the master is writing to or reading from the MAX11606– MAX11611 (R/W = 0 selects a write condition, R/W = 1 selects a read condition). After receiving the address, the MAX11606–MAX11611 (slave) issues an acknowledge by pulling SDA low for one clock cycle. up to 22.2ksps. The MAX11606–MAX11611 must operate in high-speed mode (HS mode) to achieve conversion rates up to 94.4ksps. Figure 1 shows the bus timing for the MAX11606–MAX11611’s 2-wire interface. HS Mode At power-up, the MAX11606–MAX11611 bus timing is set for F/S mode. The bus master selects HS mode by addressing all devices on the bus with the HS-mode master code 0000 1XXX (X = don’t care). After successfully receiving the HS-mode master code, the MAX11606–MAX11611 issue a not-acknowledge, allowing SDA to be pulled high for one clock cycle (Figure 8). After the not-acknowledge, the MAX11606–MAX11611 are in HS mode. The bus master must then send a repeated START followed by a slave address to initiate HS-mode communication. If the master generates a STOP condition the MAX11606–MAX11611 returns to F/S mode. Bus Timing At power-up, the MAX11606–MAX11611 bus timing is set for fast mode (F/S mode), allowing conversion rates HS-MODE MASTER CODE S 0 0 0 0 1 X X X A Sr SDA SCL F/S MODE HS MODE Figure 8. F/S-Mode to HS-Mode Transfer 12 ______________________________________________________________________________________ 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs configuration byte (Table 2). The master can write either one or two bytes to the slave in any order (setup byte then configuration byte; configuration byte then setup byte; setup byte or configuration byte only; Figure 9). If the slave receives a byte successfully, it issues an acknowledge. The master ends the write cycle by issuing a STOP condition or a repeated START condition. When operating in HS mode, a STOP condition returns the bus into F/S mode (see the HS Mode section). MASTER TO SLAVE SLAVE TO MASTER A. ONE-BYTE WRITE CYCLE 1 7 1 1 S SLAVE ADDRESS W A 8 1 1 NUMBER OF BITS SETUP OR A P or Sr CONFIGURATION BYTE MSB DETERMINES WHETHER SETUP OR CONFIGURATION BYTE B. TWO-BYTE WRITE CYCLE 7 1 S 1 1 SLAVE ADDRESS 8 SETUP OR W A CONFIGURATION BYTE 1 A 8 1 1 NUMBER OF BITS SETUP OR A P or Sr CONFIGURATION BYTE MSB DETERMINES WHETHER SETUP OR CONFIGURATION BYTE Figure 9. Write Cycle Table 1. Setup Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) REG SEL2 SEL1 SEL0 CLK BIP/UNI RST X BIT NAME 7 REG Register bit. 1 = setup byte, 0 = configuration byte (see Table 2). 6 SEL2 5 SEL1 4 SEL0 Three bits select the reference voltage and the state of AIN_/REF (MAX11606/MAX11607/MAX11610/MAX11611) or REF (MAX11608/MAX11609) (Table 6). Defaulted to 000 at power-up. 3 CLK 2 BIP/UNI 1 RST 0 X DESCRIPTION 1 = external clock, 0 = internal clock. Defaulted to 0 at power-up. 1 = bipolar, 0 = unipolar. Defaulted to 0 at power-up (see the Unipolar/Bipolar section). 1 = no action, 0 = resets the configuration register to default. Setup register remains unchanged. Don’t-care bit. This bit can be set to 1 or 0. ______________________________________________________________________________________ 13 MAX11606–MAX11611 Configuration/Setup Bytes (Write Cycle) A write cycle begins with the bus master issuing a START condition followed by seven address bits (Figure 7) and a write bit (R/W = 0). If the address byte is successfully received, the MAX11606–MAX11611 (slave) issues an acknowledge. The master then writes to the slave. The slave recognizes the received byte as the setup byte (Table 1) if the most significant bit (MSB) is 1. If the MSB is 0, the slave recognizes that byte as the MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs Table 2. Configuration Byte Format BIT 7 (MSB) BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 (LSB) REG SCAN1 SCAN0 CS3 CS2 CS1 CS0 SGL/DIF BIT NAME 7 REG 6 SCAN1 5 SCAN0 4 CS3 3 CS2 2 CS1 1 CS0 0 SGL/DIF DESCRIPTION Register bit. 1= setup byte (see Table 1), 0 = configuration byte. Scan select bits. Two bits select the scanning configuration (Table 5). Defaults to 00 at power-up. Channel select bits. Four bits select which analog input channels are to be used for conversion (Tables 3 and 4). Defaults to 0000 at power-up. For MAX11606/MAX11607, CS3 and CS2 are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0. 1 = single-ended, 0 = differential (Tables 3 and 4). Defaults to 1 at power-up. See the SingleEnded/Differential Input section. Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1) CS31 CS21 CS1 CS0 AIN0 0 0 0 0 + 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 RESERVED 1 1 0 1 RESERVED 1 1 1 0 RESERVED 1 1 1 1 RESERVED AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN112 GND - + + + + + + + + + + + - 1For the MAX11606/MAX11607, CS3 and CS2 are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0. 2When SEL1 = 1, a single-ended read of AIN3/REF (MAX11606/MAX11607) or AIN11/REF (MAX11610/MAX11611) is ignored; scan stops at AIN2 or AIN10. This does not apply to the MAX11608/MAX11609 as each provides separate pins for AIN7 and REF. 14 ______________________________________________________________________________________ 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs CS31 CS21 CS1 CS0 AIN0 0 0 0 0 + - 0 0 0 1 - + 0 0 1 0 + - 0 0 1 1 - + 0 1 0 0 1 0 1 0 AIN1 AIN2 AIN32 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 0 + - 0 1 - + 1 0 + - 1 1 1 - + 1 0 0 0 + - 1 0 0 1 - + 1 0 1 0 1 0 1 1 1 1 0 0 RESERVED 1 1 0 1 RESERVED 1 1 1 0 RESERVED 1 1 1 1 RESERVED AIN10 AIN112 + - - + 1For the MAX11606/MAX11607, CS3 and CS2 are internally set to 0. For the MAX11608/MAX11609, CS3 is internally set to 0. 2 When SEL1 = 1, a differential read between AIN2 and AIN3/REF (MAX11606/MAX11607) or AIN10 and AIN11/REF (MAX11610/MAX11611) returns the difference between GND and AIN2 or AIN10, respectively. For example, a differential read of 1011 returns the negative difference between AIN10 and GND. This does not apply to the MAX11608/MAX11609 as each provides separate pins for AIN7 and REF. In differential scanning, the address increments by 2 until the limit set by CS3–CS1 has been reached. Data Byte (Read Cycle) A read cycle must be initiated to obtain conversion results. Read cycles begin with the bus master issuing a START condition followed by seven address bits and a read bit (R/W = 1). If the address byte is successfully received, the MAX11606–MAX11611 (slave) issues an acknowledge. The master then reads from the slave. The result is transmitted in two bytes; first six bits of the first byte are high, then MSB through LSB are consecutively clocked out. After the master has received the byte(s), it can issue an acknowledge if it wants to continue reading or a not-acknowledge if it no longer wishes to read. If the MAX11606–MAX11611 receive a notacknowledge, they release SDA, allowing the master to generate a STOP or a repeated START condition. See the Clock Modes and Scan Mode sections for detailed information on how data is obtained and converted. Clock Modes The clock mode determines the conversion clock and the data acquisition and conversion time. The clock mode also affects the scan mode. The state of the setup byte’s CLK bit determines the clock mode (Table 1). At power-up, the MAX11606–MAX11611 are defaulted to internal clock mode (CLK = 0). Internal Clock When configured for internal clock mode (CLK = 0), the MAX11606–MAX11611 use their internal oscillator as the conversion clock. In internal clock mode, the MAX11606– MAX11611 begin tracking the analog input after a valid address on the eighth rising edge of the clock. On the falling edge of the ninth clock, the analog signal is acquired and the conversion begins. While converting the analog input signal, the MAX11606–MAX11611 holds SCL low (clock stretching). After the conversion completes, the results are stored in internal memory. If the scan mode is set for multiple conversions, they all happen in succession with each additional result stored in memory. The MAX11606/MAX11607 contain four 10-bit blocks of memory, the MAX11608/MAX11609 contain eight 10-bit blocks of memory, and the MAX11610/MAX11611 contain twelve 10bit blocks of memory. Once all conversions are complete, the MAX11606–MAX11611 release SCL, allowing it to be pulled high. The master may now clock the results out of the memory in the same order the scan conversion has been done at a clock rate of up to 1.7MHz. SCL is stretched for a maximum of 7.6µs per channel (see Figure 10). ______________________________________________________________________________________ 15 MAX11606–MAX11611 Table 4. Channel Selection in Differential Mode (SGL/DIF = 0) MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs MASTER TO SLAVE SLAVE TO MASTER A. SINGLE CONVERSION WITH INTERNAL CLOCK 1 7 S 1 1 SLAVE ADDRESS R A 8 CLOCK STRETCH 1 8 A RESULT 2 MSBs 1 NUMBER OF BITS A P or Sr RESULT 8 LSBs tACQ tCONV B. SCAN MODE CONVERSIONS WITH INTERNAL CLOCK 1 7 1 1 S SLAVE ADDRESS R A 8 CLOCK STRETCH tACQ1 CLOCK STRETCH tACQ2 tCONV2 tCONV1 1 8 1 8 RESULT 1 ( 2MSBs) A RESULT 1 (8 LSBs) A 1 8 1 1 NUMBER OF BITS RESULT N (8MSBs) A RESULT N (8LSBs) A P or Sr tACQN tCONVN Figure 10. Internal Clock Mode Read Cycles The device memory contains all of the conversion results when the MAX11606–MAX11611 release SCL. The converted results are read back in a first-in-first-out (FIFO) sequence. If AIN_/REF is set to be a reference input or output (SEL1 = 1, Table 6), AIN_/REF is excluded from a multichannel scan. This does not apply to the MAX11608/MAX11609 as each provides separate pins for AIN7 and REF. The memory contents can be read continuously. If reading continues past the result stored in memory, the pointer wraps around and point to the first result. Note that only the current conversion results are read from memory. The device must be addressed with a read command to obtain new conversion results. The internal clock mode’s clock stretching quiets the SCL bus signal, reducing the system noise during conversion. Using the internal clock also frees the bus master (typically a microcontroller) from the burden of running the conversion clock, allowing it to perform other tasks that do not need to use the bus. MASTER TO SLAVE SLAVE TO MASTER A. SINGLE CONVERSION WITH EXTERNAL CLOCK 1 7 1 1 8 1 8 1 1 S SLAVE ADDRESS R A RESULT (2 MSBs) A RESULT (8 LSBs) A P OR Sr NUMBER OF BITS tACQ tCONV B. SCAN MODE CONVERSIONS WITH EXTERNAL CLOCK 1 S 7 1 1 SLAVE ADDRESS R A 8 RESULT 1 (2 MSBs) 1 A 8 1 8 1 RESULT 2 (8 LSBs) A RESULT N (2 MSBs) A tACQ2 tACQN tACQ1 tCONV1 8 RESULT N (8 LSBs) 1 1 A P OR Sr tCONVN Figure 11. External Clock Mode Read Cycle 16 ______________________________________________________________________________________ NUMBER OF BITS 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs SCAN1 SCAN0 SCANNING CONFIGURATION 0 0 Scans up from AIN0 to the input selected by CS3–CS0. When CS3–CS0 exceeds 1011, the scanning stops at AIN11. When AIN_/REF is set to be a REF input/output, scanning stops at AIN2 or AIN10. 0 1 *Converts the input selected by CS3–CS0 eight times (see Tables 3 and 4). MAX11606/MAX11607: Scans upper half of channels. Scans up from AIN2 to the input selected by CS1 and CS0. When CS1 and CS0 are set for AIN0, AIN1, and AIN2, the only scan that takes place is AIN2 (MAX11606/MAX11607). When AIN/REF is set to be a REF input/output, scanning stops at AIN2. 1 0 MAX11608/MAX11609: Scans upper quartile of channels. Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only scan that takes place is AIN6 (MAX11608/MAX11609). MAX11610/MAX11611: Scans upper half of channels. Scans up from AIN6 to the input selected by CS3–CS0. When CS3–CS0 is set for AIN0–AIN6, the only scan that takes place is AIN6 (MAX11610/MAX11611). When AIN/REF is set to be a REF input/output, scanning stops at selected channel or AIN10. 1 1 *Converts channel selected by CS3–CS0. *When operating in external clock mode, there is no difference between SCAN[1:0] = 01 and SCAN[1:0] = 11, and converting occurs perpetually until not acknowledge occurs. External Clock When configured for external clock mode (CLK = 1), the MAX11606–MAX11611 use the SCL as the conversion clock. In external clock mode, the MAX11606– MAX11611 begin tracking the analog input on the ninth rising clock edge of a valid slave address byte. Two SCL clock cycles later the analog signal is acquired and the conversion begins. Unlike internal clock mode, converted data is available immediately after the first four empty high bits. The device continuously converts input channels dictated by the scan mode until given a not acknowledge. There is no need to re-address the device with a read command to obtain new conversion results (see Figure 11). The conversion must complete in 1ms or droop on the track-and-hold capacitor degrades conversion results. Use internal clock mode if the SCL clock period exceeds 60µs. The MAX11606–MAX11611 must operate in external clock mode for conversion rates from 40ksps to 94.4ksps. Below 40ksps internal clock mode is recommended due to much smaller power consumption. Scan Mode SCAN0 and SCAN1 of the configuration byte set the scan mode configuration. Table 5 shows the scanning configurations. If AIN_/REF is set to be a reference input or output (SEL1 = 1, Table 6), AIN_/REF is excluded from a multichannel scan. The scanned results are written to memory in the same order as the conversion. Read the results from memory in the order they were converted. Each result needs a 2-byte transmission, the first byte begins with six empty bits during which SDA is left high. Each byte has to be acknowledged by the master or the memory transmission is terminated. It is not possible to read the memory independently of conversion. Applications Information Power-On Reset The configuration and setup registers (Tables 1 and 2) default to a single-ended, unipolar, single-channel conversion on AIN0 using the internal clock with VDD as the reference and AIN_/REF configured as an analog input. The memory contents are unknown after power-up. Automatic Shutdown Automatic shutdown occurs between conversions when the MAX11606–MAX11611 are idle. All analog circuits participate in automatic shutdown except the internal reference due to its prohibitively long wake-up time. When operating in external clock mode, a STOP, notacknowledge or repeated START, condition must be issued to place the devices in idle mode and benefit from automatic shutdown. A STOP condition is not necessary in internal clock mode to benefit from automatic shutdown because power-down occurs once all conversion results are written to memory (Figure 10). When ______________________________________________________________________________________ 17 MAX11606–MAX11611 Table 5. Scanning Configuration MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs Table 6. Reference Voltage, AIN_/REF, and REF Format SEL2 SEL1 SEL0 REFERENCE VOLTAGE 0 0 X VDD AIN_/REF (MAX11606/ MAX11607/ MAX11610/ MAX11611) Analog input 0 1 X External reference Reference input Reference input Always off 1 0 0 Internal reference Analog input Not connected Always off 1 0 1 Internal reference Analog input Not connected Always on 1 1 0 Internal reference Reference output Reference output Always off 1 1 Internal reference Reference output Reference output Always on 1 X = Don’t care. using an external reference or VDD as a reference, all analog circuitry is inactive in shutdown and supply current is less than 0.5µA (typ). The digital conversion results obtained in internal clock mode are maintained in memory during shutdown and are available for access through the serial interface at any time prior to a STOP or a repeated START condition. When idle, the MAX11606–MAX11611 continuously wait for a START condition followed by their slave address (see Slave Address section). Upon reading a valid address byte the MAX11606–MAX11611 power-up. The internal reference requires 10ms to wake up, so when using the internal reference it should be powered up 10ms prior to conversion or powered continuously. Wake-up is invisible when using an external reference or VDD as the reference. Automatic shutdown results in dramatic power savings, particularly at slow conversion rates and with internal clock. For example, at a conversion rate of 10ksps, the average supply current for the MAX11607 is 60µA (typ) and drops to 6µA (typ) at 1ksps. At 0.1ksps the average supply current is just 1µA, or a minuscule 3µW of power consumption, see Average Supply Current vs. Conversion Rate in the Typical Operating Characteristics). REF (MAX11608/ MAX11609) INTERNAL REFERENCE STATE Not connected Always off Internal Reference The internal reference is 4.096V for the MAX11606/ MAX11608/MAX11610 and 2.048V for the MAX11607/ MAX11609/MAX11611. SEL1 of the setup byte controls whether AIN_/REF is used for an analog input or a reference (Table 6). When AIN_/REF is configured to be an internal reference output (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.1µF capacitor and a 2kΩ series resistor (see the Typical Operating Circuit). Once powered up, the reference always remains on until reconfigured. The internal reference requires 10ms to wake up and is accessed using SEL0 (Table 6). When in shutdown, the internal reference output is in a high-impedance state. The reference should not be used to supply current for external circuitry. The internal reference does not require an OUTPUT CODE MAX11606– MAX11611 FULL-SCALE TRANSITION 11 . . . 111 11 . . . 110 11 . . . 101 Reference Voltage SEL[2:0] of the setup byte (Table 1) control the reference and the AIN_/REF configuration (Table 6). When AIN_/REF is configured to be a reference input or reference output (SEL1 = 1), differential conversions on AIN_/REF appear as if AIN_/REF is connected to GND (see note 2 of Table 4). Single-ended conversion in scan mode on AIN_/REF is ignored by internal limiter, which sets the highest available channel at AIN2 or AIN10. FS = VREF ZS = GND V 1 LSB = REF 1024 00 . . . 011 00 . . . 010 00 . . . 001 00 . . . 000 0 1 2 3 INPUT VOLTAGE (LSB) FS FS - 3/2 LSB Figure 12. Unipolar Transfer Function 18 ______________________________________________________________________________________ 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs MAX11606–MAX11611 OUTPUT CODE 011 . . . 111 V FS = REF 2 011 . . . 110 ZS = 0 000 . . . 010 000 . . . 001 MAX11606– MAX11611 SUPPLIES 3V OR 5V -VREF 2 V 1 LSB = REF 1024 VLOGIC = 3V/5V GND -FS = 000 . . . 000 4.7μF R* = 5Ω 111 . . . 111 111 . . . 110 0.1μF 111 . . . 101 VDD GND 3V/5V DGND 100 . . . 001 100 . . . 000 0 - FS DIGITAL CIRCUITRY MAX11606– MAX11611 +FS - 1 LSB INPUT VOLTAGE (LSB) *VCOM ≥ VREF/2 *VIN = (AIN+) - (AIN-) *OPTIONAL Figure 13. Bipolar Transfer Function Figure 14. Power-Supply Grounding Connection external bypass capacitor and works best when left unconnected (SEL1 = 0). as possible. Route digital signals far away from sensitive analog and reference inputs. External Reference The external reference can range from 1V to VDD. For maximum conversion accuracy, the reference must be able to deliver up to 40µA and have an output impedance of 500Ω or less. If the reference has a higher output impedance or is noisy, bypass it to GND as close as possible to AIN_/REF with a 0.1µF capacitor. High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC’s fast comparator. Bypass VDD to the star ground with a network of two parallel capacitors, 0.1µF and 4.7µF, located as close as possible to the MAX11606–MAX11611 powersupply pin. Minimize capacitor lead length for best supply noise rejection, and add an attenuation resistor (5Ω) in series with the power supply, if it is extremely noisy. Transfer Functions Definitions Output data coding for the MAX11606–MAX11611 is binary in unipolar mode and two’s complement in bipolar mode with 1LSB = (VREF/2N) where N is the number of bits (10). Code transitions occur halfway between successive-integer LSB values. Figure 12 and Figure 13 show the input/output (I/O) transfer functions for unipolar and bipolar operations, respectively. Layout, Grounding, and Bypassing Only use PC boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not layout digital signal paths underneath the ADC package. Use separate analog and digital PCB ground sections with only one star point (Figure 14) connecting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground’s power supply is low impedance and as short Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The MAX11606– MAX11611’s INL is measured using the endpoint. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. ______________________________________________________________________________________ 19 MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs Aperture Delay Aperture delay (tAD) is the time between the falling edge of the sampling clock and the instant when an actual sample is taken. Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the fullscale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N Bits): SNRMAX[dB] = 6.02dB N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to RMS equivalent of all other ADC output signals. SINAD (dB) = 20 log (SignalRMS/NoiseRMS) Effective Number of Bits Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and 20 sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the ADC’s full-scale range, calculate the ENOB as follows: ⎡ ⎤ SignalRMS SINAD(dB) = 20 × log ⎢ ⎥ NoiseRMS + THDRMS ⎣ ⎦ ENOB = (SINAD - 1.76)/6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the input signal’s first five harmonics to the fundamental itself. This is expressed as: ⎛ THD = 20 × log ⎜⎜ ⎜ ⎝ ⎛ V 2 +V 2 +V 2 +V 2 ⎞ ⎞ 3 4 5 ⎟⎟ ⎜ 2 ⎜ ⎟⎟ V 1 ⎝ ⎠⎟ ⎠ where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd through 5th order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component. Chip Information PROCESS: BiCMOS ______________________________________________________________________________________ 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs TOP VIEW 3.3V or 5V + AIN0 1 8 VDD AIN1 2 7 GND 6 SDA 5 SCL 0.1μF VDD MAX11606 MAX11607 3 AIN2 AIN3/REF 4 ANALOG INPUTS AIN0 AIN1 RS * MAX11606– MAX11611 SDA SCL RS * RC NETWORK* 2kΩ μMAX (REF) AIN11/REF 1 CREF 0.1μF 16 VDD 15 GND (N.C.) AIN9 3 14 SDA MAX11608– MAX11611 RP 5V RP μC 13 SCL SDA SCL AIN0 5 12 AIN7 AIN1 6 11 AIN6 AIN2 7 10 AIN5 AIN3 8 9 *OPTIONAL **AIN11/REF (MAX11610/MAX11611) AIN4 QSOP Package Information ( ) INDICATES PINS ON THE MAX11608/MAX11609. For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Selector Guide PART GND 5V + (N.C.) AIN10 2 (N.C.) AIN8 4 AIN3**/REF INTERNAL SUPPLY INPUT INL REFERENCE VOLTAGE CHANNELS (LSB) (V) (V) MAX11606 4 4.096 4.5 to 5.5 ±1 MAX11607 4 2.048 2.7 to 3.6 ±1 MAX11608 8 4.096 4.5 to 5.5 ±1 MAX11609 8 2.048 2.7 to 3.6 ±1 MAX11610 12 4.096 4.5 to 5.5 ±1 MAX11611 12 2.048 2.7 to 3.6 ±1 PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 8 µMAX U8CN+1 21-0036 16 QSOP E16+1 21-0055 ______________________________________________________________________________________ 21 MAX11606–MAX11611 Typical Operating Circuit Pin Configurations MAX11606–MAX11611 2.7V to 3.6V and 4.5V to 5.5V, Low-Power, 4-/8-/12-Channel, 2-Wire Serial 10-Bit ADCs Revision History PAGES CHANGED REVISION NUMBER REVISION DATE 0 4/09 Introduction of the MAX11606/MAX11607 — 1 7/09 Introduction of the MAX11608–MAX116011 1 DESCRIPTION Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.