DISCRETE SEMICONDUCTORS DATA SHEET BSP254; BSP254A P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconductors, SC13b April 1995 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor FEATURES BSP254; BSP254A QUICK REFERENCE DATA • Direct interface to C-MOS, TTL, etc. SYMBOL PARAMETER − − −250 V open drain − − ±20 V ID = −200 mA; VDS = −25V 100 200 − mS drain current (DC) − − −0.2 A RDS(on) drain-source VGS = −10 V; on-state resistance ID = −200 mA − 10 15 Ω Ptot total power dissipation Tamb = 25 °C − − 1 W VDS drain-source voltage • No secondary breakdown. VGSO gate-source voltage DESCRIPTION Yfs forward transfer admittance ID • High-speed switching P-channel vertical D-MOS transistor in a TO-92 variant envelope and intended for use as a line current interruptor in relay, high-speed and line transformer drivers. CONDITIONS MIN. TYP. MAX. UNIT PINNING - TO-92 variant BSP254 PIN DESCRIPTION 1 gate 2 drain 3 source d handbook, halfpage 1 2 3 g PINNING - TO-92 variant BSP254A PIN MAM147 DESCRIPTION 1 source 2 gate 3 drain April 1995 s Fig.1 Simplified outline and symbol. 2 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP254; BSP254A LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT − 250 V open drain − 20 V drain current DC − 0.2 A drain current peak value − 0.6 A Ptot total power dissipation Tamb = 25 °C (note 1) − 1 W Tstg storage temperature range −65 +150 °C Tj junction temperature − 150 °C −VDS drain-source voltage V gate-source voltage −ID −IDM GSO THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER from junction to ambient (note 1) Note 1. Transistor mounted on printed circuit board, maximum lead length 4 mm, mounting pad for drain lead minimum 10 mm x 10 mm. Fig.2 Power derating curve. April 1995 3 MAX. 125 UNIT K/W Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP254; BSP254A CHARACTERISTICS Tj = 25 °C unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT −V(BR)DSS drain-source breakdown voltage −VGS = 0 −ID = 10 µA 250 − − V −IDSS drain-source leakage current −VDS = 200 V VGS = 0 − − 1 µA ±IGSS gate-source leakage current ±VGS = 20 V VDS = 0 − − 100 nA −VGS(th) gate-source threshold voltage VGS = VDS −ID = 1 mA 0.8 − 2.8 V RDS(on) drain-source on-resistance −VGS = 10 V −ID = 200 mA; − 10 15 Ω Yfs transfer admittance −VDS = 25 V −ID = 200 mA 100 200 − mS Ciss input capacitance note 1 − 65 90 pF Coss output capacitance note 1 − 20 30 pF Crss feedback capacitance note 1 − 6 15 pF ton turn-on time note 2 − 5 10 ns toff turn-off time note 2 − 20 30 ns Notes 1. Measured at f = 1 MHz; −VDS = 25 V; VGS = 0. 2. −VGS = 0 to 10 V; −ID = 250 mA; −VDD = 50 V. Fig.3 Switching times test circuit. April 1995 Fig.4 Input and output waveforms. 4 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor Fig.5 Typical output characteristics; Tj = 25 °C. Fig.7 April 1995 BSP254; BSP254A Fig.6 Typical on-resistance as a function of drain current, Tj = 25 °C. Fig.8 5 Typical transfer characteristic; VDS = −10 V; Tj = 25 °C. Typical capacitances as a function of drain-source voltage; VGS = 0; f = 1 MHz; Tj = 25 °C. Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor Fig.9 April 1995 BSP254; BSP254A Fig.10 6 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP254; BSP254A PACKAGE OUTLINES Plastic single-ended leaded (through hole) package; 3 leads (on-circle) SOT54 variant c L2 E d A L b 1 e1 2 e D 3 b1 L1 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A b b1 c D d E e e1 L L1(1) max L2 max mm 5.2 5.0 0.48 0.40 0.66 0.56 0.45 0.40 4.8 4.4 1.7 1.4 4.2 3.6 2.54 1.27 14.5 12.7 2.5 2.5 Notes 1. Terminal dimensions within this zone are uncontrolled to allow for flow of plastic and terminal irregularities. OUTLINE VERSION SOT54 variant April 1995 REFERENCES IEC JEDEC EIAJ TO-92 SC-43 7 EUROPEAN PROJECTION ISSUE DATE 97-04-14 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor BSP254; BSP254A DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1995 8 Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor NOTES April 1995 9 BSP254; BSP254A Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor NOTES April 1995 10 BSP254; BSP254A Philips Semiconductors Product specification P-channel enhancement mode vertical D-MOS transistor NOTES April 1995 11 BSP254; BSP254A Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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