CD4502BMS CMOS Strobed Hex Inverter/Buffer December 1992 Features Pinout • High Voltage Type (20V Rating) CD4502BMS TOP VIEW • 2 TTL Load Output Drive Capability • 3 State Outputs D3 1 16 VDD Q3 2 15 D6 D1 3 14 Q6 3 STATE 4 OUTPUT DISABLE Q1 5 13 D5 D2 6 11 Q5 Q2 7 10 D4 VSS 8 9 Q4 • Common Output Disable Control • Inhibit Control • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” 12 INHIBIT Functional Diagram Applications • 3 State Hex Inverter for Interfacing ICs with Data Buses • COS/MOS to TTL Hex Buffer 3 STATE 4 OUTPUT DISABLE 12 INHIBIT 3 D1 Description D2 CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic “1” on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic “1” on the INHIBIT input switches all six outputs to logic “0” if the OUTPUT DISABLE input is a logic “0”. This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC “B” series IOL standard. The CD4502BMS is supplied in these 16-lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4T H1F H6W CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-473 D3 D4 D5 D6 6 1 10 13 15 5 7 2 9 11 14 Q1 Q2 Q3 Q4 Q5 Q6 VDD = 16 VSS = 8 File Number 3334 Specifications CD4502BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current Input Leakage Current Input Leakage Current SYMBOL IDD IIL IIH CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 2 µA 2 +125 C - 200 µA VDD = 18V, VIN = VDD or GND 3 -55oC - 2 µA VIN = VDD or GND 1 +25oC -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV VIN = VDD or GND VDD = 20 VDD = 18V o Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 3.06 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 7.8 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 20.4 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA mA Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC Functional F VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL5 VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH5 VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL15 VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH15 VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V 1 +25oC -0.4 - µA Tri-State Output Leakage IOZH VIN = VDD or GND VOUT = VDD VDD = 20V 2 +125oC -12 - µA VDD = 18V 3 -55oC -0.4 - µA VDD = 20V 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-474 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4502BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Data or Inhibit to Output SYMBOL TPHL1 Propagation Delay Data or Inhibit to Output TPLH1 Propagation Delay Inhibit to Output TPHL2 Propagation Delay Inhibit to Output TPLH2 Propagation Delay Disable to Output TPHZ Propagation Delay Disable to Output TPZH Propagation Delay Disable to Output TPLZ Propagation Delay Disable to Output TPZL Transition Time TTHL Transition Time GROUP A SUBGROUPS TEMPERATURE CONDITIONS VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 1, 2) TTLH VDD = 5V, VIN = VDD or GND (Note 1, 2) 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 270 ns - 365 ns - 380 ns - 513 ns - 270 ns - 365 ns - 380 ns - 513 ns - 120 ns - 162 ns - 220 ns - 297 ns - 250 ns - 338 ns - 250 ns - 338 ns - 120 ns - 162 ns - 200 ns - 270 ns NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. VDD = 5V, CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 MIN MAX UNITS - 1 µA - 30 µA - 2 µA - 60 µA - 2 µA +125oC - 120 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 2.16 - mA -55oC 3.84 - mA 7-475 Specifications CD4502BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) SYMBOL IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 CONDITIONS VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V NOTES TEMPERATURE 1, 2, 4 +125oC 5.4 - mA -55oC 9.6 - mA 1, 2, 4 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V 1, 2 MIN MAX UNITS +125oC 14.4 - mA -55oC 25.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA o +125 C - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC +7 - V Propagation Delay Data to Output TPHL1 VDD = 10V 1, 2, 3 +25oC - 120 ns VDD = 15V 1, 2, 3 +25oC - 80 ns VDD = 10V 1, 2, 3 +25oC - 180 ns VDD = 15V 1, 2, 3 +25oC - 130 ns VDD = 10V 1, 2, 3 +25oC - 120 ns VDD = 15V 1, 2, 3 +25oC - 80 ns VDD = 10V 1, 2, 3 +25oC - 180 ns VDD = 15V 1, 2, 3 +25oC - 130 ns VDD = 10V 1, 2, 4 +25oC - 80 ns VDD = 15V 1, 2, 4 +25oC - 60 ns VDD = 10V 1, 2, 4 +25oC - 100 ns VDD = 15V 1, 2, 4 +25oC - 80 ns VDD = 10V 1, 2, 4 +25oC - 130 ns VDD = 15V 1, 2, 4 +25oC - 110 ns VDD = 10V 1, 2, 4 +25oC - 110 ns VDD = 15V 1, 2, 4 +25oC - 80 ns VDD = 10V 1, 2, 3 +25oC - 60 ns VDD = 15V 1, 2, 3 +25oC - 40 ns VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns 1, 2 +25oC - 7.5 pF Propagation Delay Data to Output Propagation Delay Inhibit to Output Propagation Delay Inhibit to Output Propagation Delay Disable to Output Propagation Delay Disable to Output Propagation Delay Disable to Output Propagation Delay Disable to Output Transition Time Transition Time Input Capacitance TPLH1 TPHL2 TPLH2 TPHZ TPZH TPLZ TPZL TTHL TTLH CIN Any Inputs NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 7-476 Specifications CD4502BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 7.5 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Supply Current N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP P Threshold Voltage Delta ∆VTP Functional F VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ± 0.2µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 7-477 Specifications CD4502BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 2, 5, 7, 9, 11, 14 1, 3, 4, 6, 8, 10, 12, 13, 15 16 Static Burn-In 2 Note 1 2, 5, 7, 9, 11, 14 8 1, 3, 4, 6, 10, 12, 13, 15, 16 Dynamic BurnIn Note 1 - 8 16 2, 5, 7, 9, 11, 14 8 1, 3, 4, 6, 10, 12, 13, 15, 16 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 2, 5, 7, 9, 11, 14 4 1, 3, 6, 10, 12, 13, 15 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram INVERTER/BUFFER NO. 1 TRUTH TABLE VDD DI * 3-STATE OUTPUT * DISABLE DISABLE INHIBIT Dn Qn 0 0 0 1 0 0 1 0 0 1 X 0 1 X X Z Q1 INHIBIT * VSS VDD TO 5 OTHER INVERTER/BUFFERS Logic 0 = Low Logic 1 = High * ALL INPUTS ARE PROTECTED Z = High Impedance BY CMOS PROTECTION NETWORK X = Don’t Care VSS FIGURE 1. LOGIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTER/BUFFERS Test Circuit and Waveform VDD D3 Q3 D1 PULSE GENERATOR DISABLE Q1 D2 Q2 VSS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VDD 0.01kµF D6 1kΩ Q6 A D5 CL INHIBIT Q5 50% 50% D4 Q4 tPZL 90% tPLZ 10% VOL 90% VOH TEST CONDITIONS TEST PIN 15 POINT A tPHZ VSS VSS tPLZ VDD VDD tPZL VDD VDD tPZH VSS VSS tPHZ FIGURE 2. DISABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS 7-478 VDD 10% tPZH VSS 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 -5 -10V DISSIPATION PER INVERTER/BUFFER (PD) (µW) OUTPUT VOLTAGE (VO) (V) 15 10V 10 5V 5 105 8 6 4 SUPPLY VOLTAGE (VDD) = 15V 2 10V 10V 104 5V 8 6 4 103 CL = 50pF CL = 15pF 2 8 6 4 2 102 8 6 4 2 AMBIENT TEMPERATURE (TA) = +25oC 10 2 20 -15 FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS SUPPLY VOLTAGE (VDD) = 15V 10 15 INPUT VOLTAGE (VI) (V) -10 -15V AMBIENT TEMPERATURE (TA) = +25oC 5 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 0 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC 1/6 OUTPUT LOW (SINK) CURRENT (IOL) (mA) 1/6 OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 100 25 FIGURE 7. TYPICAL VOLTAGE TRANSFER CHARACTERISTICS 7-479 4 68 2 4 6 8 2 4 6 8 101 102 103 INPUT FREQUENCY (fI) (kHz) 2 4 6 8 104 FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF INPUT FREQUENCY CD4502BMS (Continued) PROPAGATION DELAY TIME (tPLH, tPHL) (ns) Typical Performance Characteristics TRANSITION TIME (tTHL, tTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC 150 SUPPLY VOLTAGE (VDD) = 5V (tTLH) 100 5V (tTLH) 10V (tTLH) 50 15V (tTLH) 10V (tTHL) 15V (tTLH) 0 20 40 60 80 100 AMBIENT TEMPERATURE (TA) = +25oC 250 SUPPLY VOLTAGE (VDD) = 5V (tPLH) 200 5V (tPHL) 150 10V (tPLH) 100 15V (tPLH) 50 10V (tPHL) 15V (tPHL) 0 LOAD CAPACITANCE (CL) (pF) 20 40 60 80 100 LOAD CAPACITANCE (CL) (pF) FIGURE 9. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 10. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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