SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
D High Performance 1:5 PLL Clock
D
D
D
CTRL_
CLK
CTRL_
DATA
CP_OUT
OPA_IN
7
8
OPA_IP OPA_OUT
STATUS_
LOCK
GND
GND
GND
GND
C
I_REF
GND
AVCC
AVCC
AVCC
AVCC
AVCC
STATUS_
REF
D VCXO_IN
GND
GND
GND
GND
GND
VCC
STATUS_
VCXO
E
VCXO_IN
B
GND
VCC
VCC
VCC
VCC
VCC
F
Y0
GND
GND
GND
GND
GND
VCC
Y4B
G
Y0B
VCC
VCC
VCC
VCC
VCC
VCC
Y4
H
NPD
Y1
Y1B
Y2
Y2B
Y3
Y3B
NRESET
VCC
STATUS_LOCK
AVCC
GND
OPA_OUT
GND
OPA_IP
GND
AVCC
REF_IN
36
25
37
24
GND
REF_IN
AVCC
STATUS_REF
AVCC
STATUS_VCXO
I_REF
VCC
Top View
VCC
VCC
Thermal Pad
must be
soldered to
GND
VCXO_IN
description
6
B
OPA_IN
D
D
D
5
AVCC
D
D
4
CP_OUT
D
3
CTRL_DATA
D
D
A CTRL_LE
2
CTRL_CLK
D
D
1
NC
D
TERMINAL ASSIGNMENTS
(TOP VIEW)
CTRL_LE
D
Synchronizer
Two Clock Inputs: VCXO_IN Clock Is
Synchronized To REF_IN Clock
Synchronizes Frequencies Up To 800 MHz
(VCXO_IN)
Supports Five Differential LVPECL Outputs
Each Output Frequency Is Selectable By
x1, /2, /4, /8, /16
All Outputs Are Synchronized
Integrated Low-Noise OPA For External
Low-Pass Filter
Efficient Jitter Screening From Low PLL
Loop Bandwidth
Low-Phase Noise Characteristic
Programmable Delay For Phase
Adjustments
Predivider Loop BW Adjustment
SPI Controllable Division Setting
Power-Up Control Forces LVPECL Outputs
to 3-State at VCC < 1.5 V
3.3-V Power Supply
Packaged In 64-Pin BGA (0,8 mm Pitch −
ZVA) or 48-Pin QFN (RGZ)
Industrial Temperature Range –40°C
To 85°C
VCXO_INB
VCC
VCC
Y3B
Y3
VCC
VCC
Y2
Y2B
VCC
Y1B
Y1
VCC
NPD
VCC
Y4B
The CDC7005 is a high-performance, low-phase
VCC
Y4
noise, and low-skew clock synthesizer and jitter
Y0
VCC
cleaner that synchronizes the voltage controlled
Y0B
NRESET
crystal oscillator (VCXO) frequency to the
VCC
VCC
reference clock. The programmable predividers
48
13
1
12
M and N give a high flexibility to the frequency ratio
of the reference clock to VCXO: VCXO_IN/
REF_IN = (NxP)/M. The VCXO_IN clock operates
up to 800 MHz. Through the selection of external
VCXO and loop filter components, the PLL loop bandwidth and damping factor can be adjusted to meet different
system requirements. Each of the five differential LVPECL outputs are programmable by the serial peripheral
interface (SPI). The SPI allows individual control of frequency and enable/disable state of each output. The
device operates in 3.3-V environment. The built-in latches ensure that all outputs are synchronized.
VCC
The CDC7005 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2009, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%)
"!-('%& '!!"# %! &*)''$%!& *)" %.) %)"#& ! )/$& &%"(#)%&
&%$-$"- 0$""$%1 "!-('%! *"!')&&2 -!)& !% )')&&$",1 ',(-)
%)&%2 ! $,, *$"$#)%)"&
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
functional block diagram
OPA_IN
−
OPA_OUT
OPA
+
OPA_IP
STATUS_REF
STATUS_VCXO
STATUS_LOCK
HOLD
REF_IN
LVCMOS
Input
Prgm Divider
M
Prgm Delay
M
Prgm Divider
N
Prgm Delay
N
PFD
CP_OUT
Charge
Pump
CTRL_LE
VI
Reference
SPI LOGIC
CTRL_DATA
I_REF
CTRL_CLK
PECL-TOLVTTL
NPD
NRESET
MUX_SEL
VCXO_IN
VCXO_INB
PECL
Input
Y0
/1
PECL
MUX0
PECL
Latch
PECL
Output
PECL
MUX1
PECL
Latch
PECL
Output
PECL
MUX2
PECL
Latch
PECL
Output
PECL
MUX3
PECL
Latch
PECL
Output
PECL
MUX4
PECL
Latch
PECL
Output
Y0B
/2
Y1
/4
Y1B
/8
Y2
/16
Y2B
P Divider
Y3
Y3B
Y4
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Y4B
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
Pin Functions
PIN
NAME
TYPE
DESCRIPTION
BGA
QFN
AVCC
CP_OUT
C3, C4, C5, C6, C7
27, 30, 32, 38, 39
Power
A4
31
O
Charge pump output
CTRL_LE
A1
36
I
LVCMOS input, control load enable for serial programmable
interface (SPI) with hysteresis. Unused or floating inputs must be
tied to proper logic level. It is recommend to use a 20kΩ or larger
pull−up resistor to VCC.
CTRL_CLK
A2
35
I
LVCMOS input, serial control clock input for SPI, with hysteresis.
Unused or floating inputs must be tied to proper logic level. It is
recommend to use a 20kΩ or larger pull−up resistor to VCC.
CTRL_DATA
A3
33
I
LVCMOS input, serial control data input for SPI, with hysteresis.
Unused or floating inputs must be tied to proper logic level. It is
recommend to use a 20kΩ or larger pull−up resistor to VCC.
B2, B3, B4, B5, B6,
B7, B8, C2, D2, D3,
D4, D5, D6, E2, F2,
F3, F4, F5, F6
Thermal pad and
pin 24
Ground
C1
40
O
Current path for external reference resistor (12 kΩ ±1%) to support
an accurate charge pump current, optional. Do not use any
capacitor across this resistor to prevent noise coupling via this
node. If internal 12 kΩ is selected (default setting), this pin can be
left open.
GND
I_REF
NC
3.3-V analog power supply
Ground
−
34
−
Not connected
NPD
H1
1
I
LVCMOS input, asynchronous power down (PD) signal active on
low. Switches all current sources off, resets all dividers to default
values, and 3-states all outputs. Has an internal 150-kΩ pullup
resistor.
Note 2: It is recommended to ramp up NPD at the same time with
VCC and AVCC or later. The ramp up rate should not be faster than
the ramp up rate of VCC and AVCC
NRESET
H8
14
I
LVCMOS input, asynchronous reset signal active on low. Resets
the counter of all dividers to zero keeping its divider values the
same. It has an internal 150-kΩ pullup resistor. Yx outputs are
switched low during reset.
OPA_IN
A5
29
I
Inverting input of the op amp, see Note 1
OPA_OUT
A7
26
O
Output of the op amp, see Note 1
OPA_IP
A6
28
I
Noninverting input of the op amp, see Note 1
REF_IN
B1
37
I
LVCMOS reference clock input
STATUS_LOCK
A8
25
O
This pin is high if the PLL lock definition is valid. PLL lock definition
means the rising edge of REF_IN clock and VCXO_IN clock for
PFD are inside the lock detect window for at least five successive
input clock cycles. If the rising edge of REF_IN clock and VCXO_IN
clock are out of the selected lock detect window, this pin will be low,
but it does not refer to the real lock condition of the PLL. This
means, that i.e. due to a strong jitter at REF_IN or VCXO_IN
STATUS_LOCK can be low, even if the PLL is in Lock. The PLL is
in lock for sure, if STATUS_LOCK is high.See Table 8 and Figure 4.
STATUS_REF
C8
23
O
LVCMOS output provides the status of the reference input
(frequencies above 3.5 MHz are interpreted as valid clock, active
high)
STATUS_VCXO
D8
22
O
LVCMOS outputs provides the status of the VCXO input
(frequencies above 10 MHz are interpreted as valid clock, active
high)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
VCC
D7, E3, E4, E5, E6,
E7, E8, F7, G2, G3,
G4, G5, G6, G7
2, 5, 6, 9, 10, 13,
15, 18, 19, 20,
21, 41, 44, 45, 48
Power
VCXO_IN
D1
42
I
VCXO LVPECL input
VCXO_INB
E1
43
I
Complementary VCXO LVPECL input
F1, H2, H4, H6, G8
46, 3, 7, 11, 16
O
LVPECL output
Y[0:4]
3.3-V supply
VCC and AVCC should have always same supply voltage
Y[0:4]B
G1, H3, H5, H7, F8
47, 4, 8, 12, 17
O
Complementary LVPECL output
NOTE 1: If the internal operational amplifier is not used, these pins can be left open.
SPI control interface
The serial interface of the CDC7005 is a simple SPI-compatible interface for writing to the registers of the device.
It consists of three control lines: CTRL_CLK, CTRL_DATA, and CTRL_LE. There are four 32-bit wide registers,
which can be addressed by the two LSBs of a transferred word (bit 0 and bit 1). Every transmitted word must
have 32 bits, starting with MSB first. Each word can be written separately. It is recommended to program Word
0, Word 1, Word 2 and Word 3 right after power up and NPD becomes HIGH. The transfer is initiated with the
falling edge of CTRL_LE; as long as CTRL_LE is high, no data can be transferred. During CTRL_LE, low data
can be written. The data has to be applied at CTRL_DATA and has to be stable before the rising edge of
CTRL_CLK. The transmission is finished by a rising edge of CTRL_LE. With the rising edge of CTRL_LE, the
new word is asynchronously transferred to the internal register (e.g., N, M, P, ...). Each word has to be separately
transmitted by this procedure. Unused or floating inputs must be tied to proper logic level. It is recommend to
use a 20kΩ or larger pull−up resistor to VCC.
t4
t3
CTRL_CLK
th2
tsu1
CTRL_DATA
Bit31 (MSB)
Bit30
Bit2
Bit1
Bit0
t7
CTRL_LE
tsu5
tsu6
Figure 1. Timing Diagram SPI Control Interface
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
Table 1. Word 0
TYPE
POWER-UP
CONDITION
Register selection
W
0
C1
Register selection
W
0
M0
Reference divider M bit 0
W
1
M1
Reference divider M bit 1
W
1
M2
Reference divider M bit 2
W
1
5
M3
Reference divider M bit 3
W
1
6
M4
Reference divider M bit 4
W
1
7
M5
Reference divider M bit 5
W
1
8
M6
Reference divider M bit 6
W
1
9
M7
Reference divider M bit 7
W
0
10
M8
Reference divider M bit 8
W
0
BIT
BIT NAME
0
C0
1
2
3
4
DESCRIPTION / FUNCTION
Reference Divider M
11
M9
Reference divider M bit 9
W
0
12
MD0
Reference delay M bit 0
W
0
13
MD1
Reference delay M bit 1
W
0
Reference Delay M
PIN
AFFECTED
14
MD2
Reference delay M bit 2
W
0
15
PFD0
PFD pulse width PFD bit 0
W
0
A4
16
PFD1
PFD pulse width PFD bit 1
W
0
A4
17
PFD2
PFD pulse width PFD bit 2
W
0
A4
18
CP0
CP current setting bit 0
W
1
A4
19
CP1
CP current setting bit 1
W
0
A4
CP current setting bit 2
W
0
A4
CP current setting bit 3
W
1
A4
PFD Pulse Width
CP Current
20
CP2
21
CP3
22
Y03St
Y0 3-state (1 = output enabled)
W
1
F1, G1
23
Y13St
Y1 3-state (1 = output enabled)
W
1
H2, H3
24
Y23St
Y2 3-state (1 = output enabled)
W
1
H4, H5
25
Y33St
Y3 3-state (1 = output enabled)
W
1
H6, H7
26
Y43St
Y4 3-state (1 = output enabled)
W
1
G8, F8
27
CP3St
CP 3-state (1 = output enabled)
W
1
A4
28
OP3St
OPA 3-state and disable (1 = OPA enabled)
W
0
A7
29
MUXS0
MUXSEL select bit 0
W
1
30
MUXS1
MUXSEL select bit 1
W
1
31
MUXS2
MUXSEL select bit 2
W
0
Output 3-State
MUXSEL
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
Table 2. Word 1
BIT
BIT
NAME
TYPE
POWER-UP
CONDITION
0
C0
Register selection
W
1
1
2
C1
Register selection
W
0
N0
VCXO divider N bit 0
W
1
3
N1
VCXO divider N bit 1
W
1
4
N2
VCXO divider N bit 2
W
1
5
N3
VCXO divider N bit 3
W
1
6
N4
VCXO divider N bit 4
W
1
7
N5
VCXO divider N bit 5
W
1
8
N6
VCXO divider N bit 6
W
1
9
N7
VCXO divider N bit 7
W
0
10
N8
VCXO divider N bit 8
W
0
DESCRIPTION / FUNCTION
VCXO
Divider N{
11
N9
VCXO divider N bit 9
W
0
12
ND0
VCXO delay N bit 0
W
0
13
ND1
VCXO delay N bit 1
W
0
VCXO
Delay N
PIN
AFFECTED
14
ND2
VCXO delay N bit 2
W
0
15
MUX00
MUX0 select bit 0
W
0
F1, G1
16
MUX01
MUX0 select bit 1
W
0
F1, G1
17
MUX02
MUX0 select bit 2
W
0
F1, G1
18
MUX10
MUX1 select bit 0
W
1
H2, H3
19
MUX11
MUX1 select bit 1
W
0
H2, H3
20
MUX12
MUX1 select bit 2
W
0
H2, H3
21
MUX20
MUX2 select bit 0
W
0
H4, H5
22
MUX21
MUX2 select bit 1
W
1
H4, H5
23
MUX22
MUX2 select bit 2
W
0
H4, H5
24
MUX30
MUX3 select bit 0
W
1
H6, H7
25
MUX31
MUX3 select bit 1
W
1
H6, H7
26
MUX32
MUX3 select bit 2
W
0
H6, H7
27
MUX40
MUX4 select bit 0
W
1
G8, F8
28
MUX41
MUX4 select bit 1
W
1
G8, F8
29
MUX42
MUX4 select bit 2
W
0
G8, F8
30
CP_DIR
Determines in which direction CP should regulate, if
REF_CLK is faster than VCXO_CLK, and vice versa (see
Figure 2)
W
1
A4
MUX0
MUX1
MUX2
MUX3
MUX4
31
REXT
Enable external reference resistor (1 = enabled)
W
0
C1
† The frequency applied to the Divider N must be smaller than 250 MHz. A sufficient P Divider must be selected with the MUX_SEL to maintain
this criteria.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
Table 3. Word 2
TYPE
POWER-UP
CONDITION
Register selection
W
0
Register selection
W
1
Enables the hold functionality (1 = enabled)
W
0
PD current sources, resets the dividers and 3-states all outputs
(0 = active)
W
1
RESET all dividers (0 = active)
W
1
Enable bandgap (1 = enabled), see Note 2
W
1
C1
LOCKW 0
Lock detect window bit 0
W
0
A8
7
LOCKW 1
Lock detect window bit 1
W
0
A8
8
RES
Reserved
W
X
BIT
BIT NAME
0
C0
1
C1
2
HOLD
3
NPD
4
NRESET
5
ENBG
6
DESCRIPTION / FUNCTION
9
RES
Reserved
W
X
10
RES
Reserved
W
X
11
RES
Reserved
W
X
12
RES
Reserved
W
X
13
RES
Reserved
W
X
14
RES
Reserved
W
X
15
RES
Reserved
W
X
16
RES
Reserved
W
X
17
RES
Reserved
W
X
18
RES
Reserved
W
X
19
RES
Reserved
W
X
20
RES
Reserved
W
X
21
RES
Reserved
W
X
22
RES
Reserved
W
X
23
RES
Reserved
W
X
24
RES
Reserved
W
X
25
RES
Reserved
W
X
26
RES
Reserved
W
X
27
RES
Reserved
W
X
28
RES
Reserved
W
X
29
RES
Reserved
W
X
30
RES
Reserved
W
X
31
RES
Reserved
W
X
PIN
AFFECTED
A4
NOTE 2: The reference voltage for the charge pump and LVPECL output circuitry can be generated in two ways. One way is to enable ENBG
and the other way is to use the voltage divider circuitry (internal or external). It is recommended to enable ENBG because it gives an
accurate value and it is independent on temperature variation.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
Table 4. Word 3 (See Note 3)
TYPE
POWER-UP
CONDITION
Register selection
W
1
Register selection
W
1
Reserved
W
0
RES
Reserved
W
0
RES
Reserved
W
0
5
RES
Reserved
W
0
6
RES
Reserved
W
0
7
RES
Reserved
W
0
8
RES
Reserved
W
0
9
RES
Reserved
W
0
10
RES
Reserved
W
0
BIT
BIT NAME
0
C0
1
C1
2
RES
3
4
DESCRIPTION / FUNCTION
11
RES
Reserved
W
0
12
RES
Reserved
W
0
13
RES
Reserved
W
0
14
RES
Reserved
W
0
15
RES
Reserved
W
0
16
RES
Reserved
W
0
17
RES
Reserved
W
0
18
RES
Reserved
W
0
19
RES
Reserved
W
0
20
RES
Reserved
W
0
21
RES
Reserved
W
0
22
RES
Reserved
W
0
23
RES
Reserved
W
0
24
RES
Reserved
W
0
25
RES
Reserved
W
0
26
RES
Reserved
W
0
27
RES
Reserved
W
0
28
RES
Reserved
W
0
29
RES
Reserved
W
0
30
RES
Reserved
W
0
31
RES
Reserved
W
0
NOTE 3: It is recommended to program all register bits of Word 3 to 0 along with other Registers.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PIN
AFFECTED
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
functional description of the logic
Table 5. Reference Divider M and VCXO Divider N (See Note 4)
M9
M8
M7
M6
M5
M4
M3
M2
M1
M0
DIV BY{
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
0
0
1
1
4
1
1
1
1
128
DEFAULT
•
•
•
0
0
0
1
1
1
Yes
•
•
•
1
1
1
1
1
1
1
1
0
1
1022
1
1
1
1
1
1
1
1
1
0
1023
1
1
1
1
1
1
1
1
1
1
1024
NOTE 4: If the divider value is Q, then the code will be the binary value of (Q−1).
† The frequency applied to the Divider N must be smaller than 250 MHz. A sufficient P Divider must be selected with the MUX_SEL to maintain
this criteria.
Table 6. Reference Delay M and VCXO Delay N
MD2/ND2
MD1/ND1
MD0/ND0
DELAY†
DEFAULT
0
0
0
0 ps
Yes
0
0
1
150 ps
0
1
0
300 ps
0
1
1
450 ps
1
0
0
600 ps
1
0
1
750 ps
1
1
0
1.5 ns
1
1
1
† Typical values at VCC = 3.3 V, temperature = 25°C
2.75 ns
Table 7. PFD Pulse Width Delay
ADDITIONAL PULSE WIDTH†
DEFAULT
0
0 ps
Yes
1
300 ps
1
0
600 ps
1
1
900 ps
1
0
0
1.5 ns
1
0
1
2.1 ns
1
1
0
2.7 ns
PFD2
PFD1
PFD0
0
0
0
0
0
0
1
1
1
† Typical values at VCC = 3.3 V, temperature = 25°C
POST OFFICE BOX 655303
3.7 ns
• DALLAS, TEXAS 75265
9
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
functional description of the logic (continued)
Table 8. Lock Detect Window
LockW 1
LockW 0
REF_IN TO Yn TOLERABLE PHASE OFFSET (See Figure 4 and Note 1)
DEFAULT
0
0
±1.2 ns
Yes
0
1
±1.8 ns
1
0
±2.4 ns
1
1
±3 ns
NOTE 1: Determined at PFD − REF_IN and Yn feed through M/N Divider and M/N Delay.
Table 9. Charge Pump Current
CP3
CP2
CP1
CP0
NOMINAL CHARGE PUMP CURRENT†
0
0
0
0
0.625 mA
0
0
0
1
1.25 mA
0
0
1
0
1.875 mA
0
0
1
1
2.5 mA
0
1
0
0
3.125 mA
0
1
0
1
3.75 mA
0
1
1
0
4.375 mA
0
1
1
1
5 mA
1
0
0
0
1 mA
1
0
0
1
2 mA
1
0
1
0
3 mA
1
0
1
1
4 mA
1
1
0
0
5 mA
1
1
0
1
6 mA
1
1
1
0
7 mA
1
1
1
1
† With an internal or external reference resistor (12 kΩ) in use.
DEFAULT
Yes
8 mA
Table 10. MUXSEL Selection
10
MUXS2
MUXS1
MUXS0
SELECTED VCXO SIGNAL FOR THE PHASE
DISCRIMINATOR
0
0
0
Y0
0
0
1
Y1
0
1
0
Y2
0
1
1
Y3
1
0
0
Y4
1
0
1
Y3
1
1
0
Y3
1
1
1
Y3
POST OFFICE BOX 655303
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DEFAULT
Yes
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
functional description of the logic (continued)
Table 11. MUX0, MUX1, MUX2, MUX3, and MUX4 Selection
MUX2
MUX1
MUX0
SELECTED DIVIDED VCXO SIGNAL
DEFAULT
0
0
0
Div by 1
For Y0
0
0
1
Div by 2
For Y1
0
1
0
Div by 4
For Y2
0
1
1
Div by 8
For Y3 and Y4
1
0
0
Div by 16
1
0
1
Div by 8
1
1
0
Div by 8
1
1
1
Div by 8
REF_IN Clock Fed Through
the M Divider and Delay
VCXO_IN Clock Fed Through
the N Divider and Delay
V(PFD1) (Internal Signal)
0V
PFD Pulse
Width Delay
PFD Pulse
Width Delay
V(PFD2) (Internal Signal)
VCC
ICP (Bit 30 of Word 1 = 1,
Default State)
ICP (Bit 30 of Word 1 = 0)
NOTE: The purpose of the PFD pulse width delay is to improve spurious suppression. (See Table 7)
Figure 2. Charge Pump Current Direction
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11
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
functional description of the logic (continued)
Power Up or Reset
and REF_IN Active
STATE 1: PRE LOCK
Normal Operation VCXO_ IN
Synchronizes with REF_IN
Valid Ref. Frequency
Detected (f > 3.5 MHz)
Five Coherent Cycles
Lock Detect
STATE 2: HOLD CTRL
REF_IN is Sensed by
VCXO_IN
REF_IN Missing
STATE 3: HOLD OPERATION
CP is in 3-State
NOTES: A. For a proper hold functionality the following conditions must be maintained:
− Counter M and counter N need to have the same divider ratio
− fref_in max = 75 MHz
− Duty cycle of 45% to 55% for 25 MHz <= fref_in < 50 MHz
− Duty cycle of 40% to 60% for 50 MHz <= fref_in < 75 MHz
− Duty cycle of fVCXO should be in 50% range
The hold functionality is triggered by the first missing REF_IN cycle. It is disabled in default mode (bit 2 of word 2 = 0). While the
device is in frequency hold mode, a possible leakage current caused by the external filter and VCXO may change the VCXO control
voltage, and therefore changing the VCXO frequency. To keep the frequency drift as low as possible, a low leakage current filter
design is recommended or the number of the disrupted / missing REF_IN clock cycles should be kept low (< 100).
Figure 3. State Machine Operation
REF_IN Clock Fed Through
the M Divider and M Delay
t(lockdetect)
VCXO_IN Clock Fed Through
the N Divider and N Delay
NOTE: If the rising edge of REF_IN clock and VCXO_IN clock for PFD are inside the lock detect window (t(lockdetect)) for at least five successive
input clock periods, then the PLL is considered to be locked. In this case, the STATUS_LOCK output is set to high level. The size of the
lock detect window is programmable via the SPI control logic (bit 6 and 7 of word 2). (See Table 8)
Figure 4. Lock Detect Window
12
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SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC, AVCC (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input current (VI < 0, VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output current for LVPECL outputs (0 < VO < VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Maximum junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. All supply voltages must be the same value and must be supplied at the same time.
NOTES: 3. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
package thermal resistance for RGZ (QFN) package (see Note 4 and Note 5)
AIRFLOW (LFM)
qJA (5C/W)
qJC (5C/W)
qJP (5C/W)
22.4
1.5
YJT (5C/W)
0.2
0
29.9
15
24.7
0.2
250
23.2
0.2
500
21.5
0.3
NOTE 4: The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
NOTE 5: Connected to GND with nine thermal vias (0,3 mm diameter).
package thermal resistance for ZVA (BGA) package (see Note 6)
AIRFLOW (m/s)
qJA (5C/W)
qJC (5C/W)
qJB (5C/W)
0
54
29.9
44.5
1
49
0.9
2.5
47.2
0.9
YJT (5C/W)
0.9
NOTE 6: The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
recommended operating conditions
Supply voltage, VCC
Operating free-air temperature, TA
MIN
NOM
MAX
3
3.3
3.6
V
85
°C
0.3 VCC
V
−40
Low-level input voltage LVCMOS, VIL
High-level input voltage LVCMOS, VIH
0.7 VCC
Input threshold voltage LVCMOS, VIT
UNIT
V
0.5 VCC
V
High-level output current LVCMOS, IOH
−6
mA
Low-level output current LVCMOS, IOL
6
mA
Input voltage range LVCMOS, VI
0
Input amplitude LVPECL, VINPP [(VVCXO_IN − VVCXO_INB), See Note 7]
Common-mode input voltage LVPECL, VIC
3.6
V
0.5
1.3
V
VCC−2
VCC−0.4
V
NOTE 7: VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum
VINPP of 100 mV.
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13
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
timing requirements over recommended ranges of supply voltage, load, and operating free-air
temperature
PARAMETER
MIN
TYP
MAX
UNIT
180
MHz
REF_IN Requirements
fREF_IN
tr / tf
LVCMOS reference clock frequency
3.5
Rise and fall time of REF_IN signal from 20% to 80% of VCC
dutyREF
Duty cycle of REF_IN at VCC / 2
VCXO_IN, VCXO_INB Requirements
fVCXO_IN
tr / tf
LVPECL VCXO clock frequency
4
40%
60%
10
800
40%
60%
Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz (see Note 8)
dutyVCXO
Duty cycle of VCXO clock
SPI/Control Requirements (See Figure 1)
3
20
ns
MHz
ns
fCTRL_CLK
tsu1
CTRL_CLK frequency
CTRL_DATA to CTRL_CLK setup time
10
ns
th2
t3
CTRL_DATA to CTRL_CLK hold time
10
ns
CTRL_CLK high duration
25
ns
t4
tsu5
CTRL_CLK low duration
25
ns
CTRL_LE to CTRL_CLK setup time
10
ns
tsu6
t7
CTRL_CLK to CTRL_LE setup time
10
ns
CTRL_LE pulse width
20
tr / tf
Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of VCC
NPD / NRESET Requirements
tr / tf
Rise and fall time of the NRESET, NPD signal from 20% to 80% of VCC
NOTES: 8. Use a square wave for lower frequencies (< 80 MHz).
14
POST OFFICE BOX 655303
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MHz
ns
5
ns
4
ns
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
device characteristics over recommended operating free-air temperature range (unless otherwise
noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
230
265
mA
100
300
µA
150
ps
Overall
fVCXO = 245 MHz, fREF_IN = 30 MHz,
VCC = 3.6 V, AVCC = 3.6 V,
fPFD = 240 kHz, ICP = 2 mA,
(see Note 11 and Note 13)
ICC
Supply current (see Note 9)
ICCPD
Power-down current
tpho
Phase offset (REF_IN to Y output)
(see Note 10)
fIN = 0 MHz, VCC = 3.6 V,
AVCC = 3.6 V, VI = 0 V or VCC
VREF_IN = VCC/2,
Crossing point of Y, See Figure 12
−150
LVCMOS
VIK
II
LVCMOS input voltage
LVCMOS input current
VCC = 3 V, II = –18 mA
VI = 0 V or VCC, VCC = 3.6 V
IIH
LVCMOS input current for NPD,
NRESET
VI = VCC, VCC = 3.6 V
IIL
LVCMOS input current for NPD,
NRESET
VI = 0 V, VCC = 3.6 V
−15
2.1
−1.2
V
±5
µA
5
µA
−35
µA
V
VOH
VOL
LVCMOS high-level output voltage
LVCMOS low-level output voltage
IOH = −12 mA, VCC = 3 V
IOL = 12 mA, VCC = 3 V
CI
Input capacitance at REF_IN
VI = 0 V or VCC
2
pF
CI
Input capacitance at CTRL_LE,
CTRL_CLOCK, CTRL_DATA
VI = 0 V or VCC
2
pF
tdetectREF
Frequency detect time until
STATUS_REF is valid
fREF_IN = 3.5 MHz
5
µs
tdetectVCXO
Frequency detect time until
STATUS_VCXO is valid
fVCXO_IN = 10 MHz
5
µs
0.55
V
LVPECL
II
IOZ
LVPECL input current
LVPECL output current 3-state
VI = 0 V or VCC
VO = 0 V or VCC−0.8 V
VOH
VOL
LVPECL high-level output voltage
See Note 11
LVPECL low-level output voltage
See Note 11
±100
µA
20
µA
VCC−1.18
VCC−0.81
V
VCC−1.98
VCC−1.55
V
500
mV
|VOD|
Differential output voltage
10 ≤ fOUT ≤ 800 MHz, See Figure 6
† All typical values are at VCC = 3.3 V, temperature = 25°C.
NOTES: 9. For ICC over frequency see Figure 5.
10. This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M
and VCXO delay N).
11. Outputs are terminated through a 50-Ω resistor to VCC − 2 V.
12. The tsk(o) specification is only valid for equal loading of all outputs.
13. All output switching at default divider ratios.
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15
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
device characteristics over recommended operating free-air temperature range (unless otherwise
noted)(continued)
PARAMETER
TEST CONDITIONS
tPLH/tPHL
tsk(p)
Propagation delay rising/falling edge
tsk(o)
LVPECL output skew (see Note 14)
tr / tf
Rise and fall time
CI
Input capacitance at VCXO_IN,
VCXO_IB
TYP†
MAX
UNIT
950
ps
15
ps
See Figure 11, Mode 1−2−4−8−8
60
ps
See Figure 11, Mode 1−1−1−1−1
30
ps
350
ps
VCXO_IN to Yn
MIN
500
LVPECL pulse skew
20% to 80% of VOD, See Figure 10
180
1.5
pF
100
MHz
Phase Detector
fCPmax
Maximum charge pump frequency
Charge Pump
ICP
ICP3St
ICPA
ICPM
IVCPM
PFD pulse width delay is 0 ps
Charge pump sink/source current
range
VCP = 0.5 VCC, See Table 9
Charge pump 3-state current
0.5 V < VCP < VCC − 0.5 V
ICP absolute accuracy
Sink/source current matching
VCP = 0.5 VCC
VCP = 0.5 VCC
±0.625
1
±8
mA
30
nA
20%
5%
ICP vs VCP matching
Operational Amplifier
0.5 V < VCP < VCC − 0.5 V
IS
VIO
Supply current
AVCC = 3.6 V
IIB
IIO
Input bias current
(| IOPA_IP | + | IOPA_IN |) / 2
1
30
nA
Input offset current
| IOPA_IP − IOPA_IN |
1
10
nA
RI
Input resistance
0.5 VCC ±500 mV
VICR
AOL
Common-mode input voltage range
Open-loop voltage gain
See Figure 17, f = 1 kHz
70
dB
GBW
Gain bandwidth
See Figure 14
3
MHz
SR
Slew rate
See Figure 14, 20% − 80% of VO
1
V/µs
VO
Output voltage swing
RL = 10 kΩ
RL = 2 kΩ
RO
Output resistance
2
Input offset voltage
IOS
Short-circuit output current
CMRR
PSRR
5
2
mA
mV
10
MΩ
0.2
VCC−0.2
0.2
VCC−0.2
VCC−0.3
0.3
60
Sourcing
V
V
Ω
−20
mA
Sinking
50
Common-mode rejection ratio
VINPP = 500 mV and
f = 1 kHz, (see Figure 15)
80
dB
Power supply rejection ratio
AVCC modulated with sine wave
from
3 V to 3.6 V and f = 100 Hz (see
Figure 16)
60
dB
500
nV/√Hz
Vn
Input noise voltage
f = 1 kHz, see Figure 14, VIN = 0 V
† All typical values are at VCC = 3.3 V, temperature = 25°C.
NOTE 14: The tsk(o) specification is only valid for equal loading of all outputs.
16
10%
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SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
SUPPLY CURRENT / DEVICE POWER
CONSUMPTION
vs
NUMBER OF ACTIVE OUTPUTS
730
VCC = 3.6 V,
TA = 25°C
270
ICC − 5 Outputs Active
710
I CC − Supply Current − mA
260
690
250
PDEV − 5 Outputs Active
240
230
630
220
PDEV − 4 Outputs Active
210
610
590
ICC − 3 Outputs Active
200
570
PDEV − 3 Outputs Active
190
180
550
530
ICC − 2 Outputs Active
170
160
150
670
650
ICC − 4 Outputs Active
510
490
PDEV − 2 Outputs Active
50
150
250
350
450
550
650
PDEV − Device Power Consumption − mW
280
750
850
470
NOTE A: PDEV = PTot − PTerm
PDEV = Device power consumption, PTot = Total power consumption, PTerm = Termination power consumption
Figure 5. ICC / PDEV vs Frequency
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT FREQUENCY
0.90
TA = 25°C
VCC = 3.3 V
VOD − Differential Output Voltage − V
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
50
150
250
350 450
550
650 750
fOUT − Output Frequency − MHz
850
950
Figure 6. Differential Output Swing (VOD) vs Frequency
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17
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
APPLICATION INFORMATION
Phase Noise Reference Circuit (See the EVM)
VCXO
Low-Pass Filter
245.76 MHz
Gain = 21.3 kHz/V
R2
160 Ω
PECL_OUT_B
V_CTRL
PECL_OUT
C3
100 nF
CDC7005
OPA_OUT
REF_IN
OPA_IP
R1
4.7 kΩ
OPA_IN
CTRL_LE
CTRL_DATA
CTRL_CLK
SPI
VOC
R
130 Ω
VOC
R
130 Ω
CP_OUT
C1
22 µF
STATUS_REF
STATUS_VCXO
STATUS_LOCK
VCXO_IN
VCXO_IN_B
C2
100 nF
10 nF
Yn
Yn_B
10 nF
R
82 Ω
R
82 Ω
R
150 Ω
R
150 Ω
R
50 Ω
Figure 7. Typical Applications Diagram With Passive Loop Filter
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
R
50 Ω
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
application specific device characteristics over recommended operating free-air temperature
range (unless otherwise noted)
PARAMETER
REF_IN
PHASE
NOISE AT
30.72 MHz
VCXO
PHASE
NOISE AT
245.76 MHz
Yn PHASE NOISE AT
30.72 MHz
MIN
TYP†
UNIT
MAX
phn10
phn100
Phase noise at 10 Hz
−115
−77
−105
dBc/Hz
Phase noise at 100 Hz
−125
−95
−116
dBc/Hz
phn1k
phn10k
Phase noise at 1 kHz
−131
−118
−135
dBc/Hz
Phase noise at 10 kHz
−136
−136
−147
dBc/Hz
phn100k
phn240k
Phase noise at 100 kHz
−138
−138
−152
dBc/Hz
Phase noise at 240 kHz
−140
−143
−152
dBc/Hz
tstabi
PLL stabilization time, (see Note 15)
200
† Output phase noise is dependent on the noise of the REF_IN clock and VCXO clock noise floor.
NOTES: 15. The typical stabilization time is based on the above application example at a loop bandwidth of 20 Hz.
16. For further explanations as well as phase noise/jitter test results using various VCXOs, see application note SCAA067.
POST OFFICE BOX 655303
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ms
19
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
APPLICATION INFORMATION
information on the clock generation for interpolating DACs with the CDC7005
The CDC7005, with its specified phase noise performance, is an ideal sampling clock generator for high speed
ADCs and DACs. The CDC7005 is especially of interest for the new high speed DACs, which have integrated
interpolation filter. Such DACs achieve sampling rates up to 500 MSPS. This high data rate can typically not
be supported from the digital side driving the DAC (e.g., DUC, digital up-converter). Therefore, one approach
to interface the DUC to the DAC is the integration of an interpolation filter within the DAC to reduce the data rate
at the digital input of the DAC. In 3G systems, for example, a common sampling rate of a high speed DAC is
245.76 MSPS. With a four times interpolation of the digital data, the required input data rate results into
61.44 MSPS, which can be supported easily from the digital side. The DUC GC4116, which supports up to two
WCDMA carriers, provides a maximum output data rate of 100 MSPS. An example is shown in Figure 8, where
the CDC7005 supplies the clock signal for the DUC/DDC and ADC/DAC.
RF
GC4016
THS4502
LNA
I
DDC
To BB
12-Bit
ADC
Q
IF2
IF1
Duplexer
61.44 MHz
LO1
(PLL)
3.84 MHz
CDC7005
VCXO
245.76 MHz
245.76 MHz
61.44 MHz
I
61.44 MHz
FIR
FIR
16-Bit
DAC
PA
Σ
DUC
From BB
Q
FIR
GC4116
FIR
16-Bit
DAC
DAC5686
0
90
LO1
(PLL)
Figure 8. CDC7005 as a Clock Generator for High Speed ADCs and DACs
The generation of the two required clock signals (data input clock, clock for DAC) for such an interpolating DAC
can be done in different ways. The easiest way would be to provide an internal PLL multiplier, which is capable
of generating the fast sampling clock for the DAC from the data input clock signal. However, the process of the
DAC is usually not optimized for best phase noise performance, while the CDC7005 is optimized exactly for this.
The CDC7005 therefore provides the preferred clocking scheme for the DAC5686. The DAC5686 demands that
the edges of the two input clocks must be phase aligned within ±500 ps for latching the data properly. This phase
alignment is well achieved with the CDC7005, which assures a maximum skew of 200 ps of the different different
outputs to each other.
20
POST OFFICE BOX 655303
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SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
APPLICATION INFORMATION
Another advantage of this clock solution is that the ADC or DAC can be driven directly in an ac-coupling interface
as shown in Figure 9, with an external termination in a differential configuration. There is no need for a
transformer to generate a differential signal from a single-ended clock source.
PECL
Output
DAC
CLK1
CLK1C
RT
50 Ω
RT
50 Ω
VIT
Figure 9. Driving DAC or ADC with PECL Output of the CDC7005
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21
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
PARAMETER MEASUREMENT INFORMATION
Yn
VOH
Yn
VOL
80%
VOD
0V
20%
VOD = Yn*Yn
tr
tf
Figure 10. LVPECL Differential Output Voltage and Rise/Fall Time
Yn
Yn
tsk(0)
Any Yn
Any Yn
Any Yn
Any Yn
Figure 11. Output Skew
22
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SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
PARAMETER MEASUREMENT INFORMATION
VIH
50% VCC
REF_IN
VIL
tpho
Yn
VOH
Yn
VOL
Figure 12. Phase Offset
VCC
ZO = 50 Ω
Yn
CDC7005
Driver
LVPECL
RCVR
Yn
ZO = 50 Ω
50 Ω
50 Ω
VT+VCC*2 V
Figure 13. Typical Termination for Output Driver
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23
SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
PARAMETER MEASUREMENT INFORMATION
3.3 kΩ
AVCC
180 Ω
−
VIN
AVCC
450 Ω
VOUT
+
10 kΩ
50 Ω
(Oscilloscope)
10 kΩ
10 nF
Figure 14. OPA Slew Rate/Gain Bandwidth Test Circuit
900 Ω
AVCC
180 Ω
−
VIN
VOUT
180 Ω
+
900 Ω
NOTE: CMRR (dB) = 20 x Log (VIN/(VIN − VOUT)) x (1 + 900/180)
Figure 15. CMRR Test Circuits
900 Ω
AVCC
AVCC
10 kΩ
180 Ω
−
VOUT
+
10 kΩ
NOTE: PSRR (dB) = (∆AVCC/VOUT) x (900/180)
Figure 16. PSRR Test Circuit
24
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SCAS685L− DECEMBER 2002 − REVISED JUNE 2009
PARAMETER MEASUREMENT INFORMATION
1 kΩ
AVCC
1 kΩ
100 kΩ
−
VIN
VOUT
AVCC
+
1 kΩ
10 Ω
10 Ω
NOTE: A(OL) = (VIN / VOUT) x (1 + 100 kΩ/1 kΩ)
Figure 17. Open Loop Voltage Gain Test Circuit
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25
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CDC7005RGZ
PREVIEW
VQFN
RGZ
48
TBD
Call TI
Call TI
-40 to 85
CDC7005RGZR
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
CDC7005
CDC7005RGZRG4
ACTIVE
VQFN
RGZ
48
2500
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
CDC7005
CDC7005RGZT
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | Call TI
Level-3-260C-168 HR
-40 to 85
CDC7005
CDC7005RGZTG4
ACTIVE
VQFN
RGZ
48
250
Green (RoHS
& no Sb/Br)
Call TI
Level-3-260C-168 HR
-40 to 85
CDC7005
CDC7005ZVA
ACTIVE
BGA
ZVA
64
348
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
-40 to 85
CK7005Z
CDC7005ZVAR
ACTIVE
BGA
ZVA
64
1000
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
-40 to 85
CK7005Z
CDC7005ZVAT
ACTIVE
BGA
ZVA
64
250
Pb-Free
(RoHS)
SNAGCU
Level-3-260C-168 HR
-40 to 85
CK7005Z
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
CDC7005RGZR
VQFN
RGZ
48
CDC7005RGZT
VQFN
RGZ
CDC7005ZVAR
BGA
ZVA
CDC7005ZVAT
BGA
ZVA
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1.5
12.0
16.0
Q2
2500
330.0
16.4
7.3
7.3
48
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q2
64
1000
330.0
16.4
8.3
8.3
2.25
12.0
16.0
Q1
64
250
330.0
16.4
8.3
8.3
2.25
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDC7005RGZR
VQFN
RGZ
48
2500
336.6
336.6
28.6
CDC7005RGZT
VQFN
RGZ
48
250
336.6
336.6
28.6
CDC7005ZVAR
BGA
ZVA
64
1000
336.6
336.6
28.6
CDC7005ZVAT
BGA
ZVA
64
250
336.6
336.6
28.6
Pack Materials-Page 2
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