TI CDCE72010RGCTG4

CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
Ten Output High Performance Clock Synchronizer, Jitter Cleaner, and Clock Distributor
FEATURES
1
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High Performance LVPECL, LVDS, LVCMOS
PLL Clock Synchronizer
Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support
with Manual or Automatic Selection
Accepts Two Differential Input (LVPECL or
LVDS) References up to 500MHz (or Two
LVCMOS Inputs up to 250MHz) as PLL
Reference
VCXO_IN Clock is Synchronized to One of Two
Reference Clocks
VCXO_IN Frequencies up to 1.5GHz (LVPECL)
800Mhz for LVDS and 250MHz for LVCMOS
Level Signaling
Outputs Can be a Combination of LVPECL,
LVDS, and LVCMOS (Up to 10 Differential
LVPECL or LVDS Outputs or up to 20 LVCMOS
Outputs), Output 9 can be Converted to an
Auxiliary Input as a 2nd VC(X)O.
Output Divider is Selectable to Divide by 1, 2,
3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36,
40, 42, 48, 50, 56, 60, 64, 70, or 80 On Each
Output Individually up to Eight Dividers.
(Except for Output 0 and 9, Output 0 Follows
Output 1 Divider and Output 9 Follows Output
8 Divider)
SPI Controllable Device Setting
Individual Output Enable Control via SPI
Interface
Integrated On-Chip Non-Volatile Memory
(EEPROM) to Store Settings without the Need
to Apply High Voltage to the Device
Optional Configuration Pins to Select Between
Two Default Settings Stored in EEPROM
Efficient Jitter Cleaning from Low PLL Loop
Bandwidth
Very Low Phase Noise PLL Core
Programmable Phase Offset (Input Reference
to Outputs)
•
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•
•
Wide Charge-Pump Current Range From
200µA to 3mA
Dedicated Charge-Pump Supply for Wide
Tuning Voltage Range VCOs
Presets Charge-Pump to VCC_CP/2 for Fast
Center-Frequency Setting of VC(X)O,
Controlled Via the SPI Bus
SERDES Startup Mode (Depending on VCXO
Range)
Auxiliary Input: Output 9 can Serve as 2nd
VCXO Input to Drive All Outputs or to Serve as
PLL Feedback Signal
RESET or HOLD Input Pin to Serve as Reset or
Hold Functions
REFERENCE SELECT for Manual Select
Between Primary and Secondary Reference
Clocks
POWER DOWN (PD) to Put Device in Standby
Mode
Analog and Digital PLL Lock Indicator
Internally Generated VBB Bias Voltages for
Single-Ended Input Signals
Frequency Hold-Over Mode Activated by
HOLD Pin or SPI Bus to Improve Fail-Safe
Operation
Input to All Outputs Skew Control
Individual Skew Control for Each Output with
Each Output Divider
Packaged in a QFN-64 Package
ESD Protection Exceeds 2kV HBM
Industrial Temperature Range of –40°C to 85°
APPLICATIONS
•
•
Low Jitter Clock Driver for High-End Telecom
and Wireless Applications
High Precision Test Equipment
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2009, Texas Instruments Incorporated
CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
DESCRIPTION
The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a
VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two
reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The
following relationship applies to the dividers:
Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)
The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filter
components. The PLL loop bandwidth and damping factor can be adjusted to meet different system
requirements.
The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports
frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user
definable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. The
built-in synchronization latches ensure that all outputs are synchronized for very low output skew.
All device settings, including output signaling, divider value selection, input selection, and many more, are
programmable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the device
settings.
The device operates in a 3.3V environment and is characterized for operation from –40°C to +85°C.
U0P
U0N
U1P
Output Divider 1
U1N
PRI _I N
PFD
SE C_I N
Charge
Pump
Feedback
Divider
Output Divider 2
Output Divider 3
Output Divider 4
U2N
U3P
U3N
U4P
U4N
VCXO/ VCO IN
Output Divider 5
PLL_LOCK
REF_SEL
POWER DOWN
RESET or HOLD
MODE_SEL
AUX_SEL
U2P
U5P
U5N
U6P
Output Divider 6
Interface
& Control
U7P
EEPROM
Output Divider 7
SPI_MISO
SPI_LE (CD1)
SPI_CLK (CD2)
SPI_MOSI (CD3)
U6N
U7N
U8P
Output Divider 8
Auxiliary I nput
U8N
U9P or AUX IN+
U9N or AUX IN–
Figure 1. High Level Block Diagram of the CDCE72010
2
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CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
PACKAGE
The CDCE72010 is available in a 64-pin lead-free “green” plastic quad flatpack package with enhanced bottom
thermal pad for heat dissipation. The Texas Instruments package designator is RGC (S-PQFP-N64).
48
33
32
49
Bottom View
Top View
64
17
1
16
TERMINAL FUNCTIONS
TERMINAL
NAME
VCC
NO.
5,8,11,14,19
22,25,28,31
34,37,40, and
43
I/O
Power
DESCRIPTION
3.3V supply for the output buffers. There is no internal connection between VCC and AVCC.
It is recommended that each VCC uses its own supply filter.
VCC_PLL
4, 63
A. Power 3.3V PLL supply voltage for the PLL circuitry.
VCC_IN
57, 60
A. Power 3.3V reference input buffers and circuitry supply voltage.
VCC_VCXO
51, 54
A. Power 3.3V VCXO input buffer and circuitry supply voltage.
GND
32
Ground
Ground connected to thermal pad internally.
GND
PAD
Ground
Ground on thermal pad. See layout recommendations.
VCCA
48, 49
A. Power 3.3V for internal analog circuitry power supply
GND_CP
2
A.
Ground
VCC_CP
64
A. Power
SPI_MISO
15
DO
SPI_LE
or CD1
45
I
LVCMOS input, control latch enable for the Serial Programmable Interface (SPI), with
hysteresis in SPI mode.
In configuration default mode this pin becomes CD1.
SPI_CLK
or CD2
46
I
LVCMOS input, serial control clock input for the SPI bus interface, with hysteresis. In
configuration default mode this pin becomes CD2.
SPI_MOSI
or CD3
44
I
LVCMOS input, master out slave in as a serial control data input to CDCE72010 for the SPI
bus interface. In configuration default mode this pin becomes CD3 and it should be tied to
GND.
I
SPI MODE = H; when driven high or left unconnected, it defaults to SPI bus interface mode.
CD MODE = L; If tied low the device goes into configuration default mode which is
configured by CD1, CD2, CD3, and AUX_SEL (CTRL_LE, CTRL_CLK, and CTRL_MOSI).
In configuration default mode the device loads various configuration defaults from the
EEPROM into memory at start-up.
MODE_SEL
16
Analog ground for charge pump
Charge pump power supply pin used to have the same supply as the external VCO/VCXO.
It can be set from 2.3V to 3.6V.
In SPI mode it is an open drain output and it functions as a master and in slave out as a
serial control data output from the CDCE72010.
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CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
AUX_SEL
REF_SEL
POWER_DOWN
18
47
17
I/O
DESCRIPTION
I
This pin is used in CD mode only. If set to “1” or left unconnected, it disables output 9 and
enables the AUXILIARY input to drive all outputs from output0 to output8 depending on the
EEPROM configuration. If driven low in CD mode, it enables output 9 and makes all outputs
driven by the VCXO Input depending on the internal EEPROM configuration.
I
If Auto Reference Select mode is OFF, this pin acts as an External Input Reference Select
Pin;
The REF_SEL signal selects one of two input clocks:
REF_SEL [1]: PRI_REF is selected;
REF_SEL [0]: SEC_REF is selected;
The input has an internal 150-kΩ pull­up resistor and if left unconnected it will default to
logic level “1”.
If Auto Reference Select mode in ON, this pin not used.
I
This pin is active low and can be activated externally or by the corresponding bit in the SPI
register (in case of logic high, the SPI setting is valid).
This pin switches the device into powerdown mode
The input has an internal 150-kΩ pull­up resistor and if left unconnected it will default to
logic level “1”.
RESET or HOLD
33
I
This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET is the
default function. This pin is active low and can be activated external or via the
corresponding bit in the SPI register.
In the case of RESET, the CP (Charge Pump) is switched to 3-state and all counters are
reset to zero. The LVPECL outputs are static low (N) and high (P) respectively, and the
LVCMOS outputs are all low or high if inverted. In the case of HOLD, the CP (Charge
Pump) is switched into 3-state mode only. After HOLD is released and with the next valid
reference clock cycle, the charge pump is switched back into normal operation (CP stays in
3-state as long as no reference clock is valid). During HOLD, all outputs are at normal
operation. This mode allows external control of “frequency hold-over” mode. The input has
an internal 150-kΩ pull­up resistor.
VCXO IN+
53
I
VCXO input (+) for LVPECL+, LVDS+, and LVCMOS level inputs.
VCXO IN–
52
I
Complementary VCXO input for LVPECL-, LVDS- inputs. In the case of a LVCMOS level
input on VCXO IN+, ground this pin.
PRI REF+
59
I
Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the Primary Reference
Clock.
PRI REF–
58
I
Universal input buffer (LVPECL, LVDS) negative input for the Primary Reference Clock. In
the case of LVCMOS signaling, ground this pin.
SEC REF+
62
I
Universal input buffer (LVPECL, LVDS, LVCMOS) positive input for the Secondary
Reference Clock.
SEC REF–
61
I
Universal input buffer (LVPECL, LVDS,) negative input for the Secondary Reference Clock.
In the case of LVCMOS signaling, ground this pin.
TESTOUTA
1
A
Analog Test Point for TI internal testing. Connect a 1kΩ pull-down resistor or leave
unconnected.
STATUS
55
AO/O
CP_OUT
3
AO
Charge pump output
VBB
56
AO
Internal voltage bias analog output
AI/O
LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in lock. This
output can be programmed to be a digital lock detect or analog lock detect (see description
of Analog Lock). The PLL is locked (set high), if the rising edge of either the PRI_REF or
SEC_REF clock and the VCXO_IN clock at the PFD (Phase Frequency Detector) are inside
the lock detect window for a predefined number of successive clock cycles.
The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or SEC_REF clock
and the VCXO_IN clock at the PFD are outside the lock detect window.
The lock detect window and the number of successive clock cycles are user definable (via
the SPI interface).
PLL_LOCK
4
50
LVCMOS output for TI internal testing. Leave unconnected unless it is configured as the
IREF_CP pin. In this case it should be connected to a 12-kΩ resistor to GND.
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www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
I/O
NO.
U0P:U0N
U1P:U1N
U2P:U2N
U3P:U3N
U4P:U4N
U5P:U5N
U6P:U6N
U7P:U7N
U8P:U8N
DESCRIPTION
7,6
10,9
13,12
21,20
24,23
27,26
30,29
36,35
39,38
O
The main outputs of the CDCE72010 are user definable and can be any combination of up
to 9 LVPECL outputs, 9 LVDS outputs, or up to 18 LVCMOS outputs. The outputs are
selectable via the SPI interface. The power-up setting is EEPROM configurable.
U9P or AUXINP
42
I/O
Positive universal output buffer 9 can be 3-stated and used as a positive universal auxiliary
input buffer (It requires external termination). The auxiliary input signal can be routed to
drive the outputs or the feedback loop to the PLL.
U9N or AUXINN
41
I/O
Negative universal output buffer 9 can be 3-stated and used as a negative universal
auxiliary input buffer (It requires external termination). The auxiliary input signal can be
routed to drive the outputs or the feedback loop to the PLL.
PACKAGE THERMAL RESISTANCE FOR QFN (RGZ) PACKAGE (1) (2)
AIRFLOW
(LFM)
(1)
(2)
(3)
θJP (°C/W) (3)
θJA (°C/W)
0
JEDEC compliant board (6×6 VIAs on PAD)
1.5
28
100
JEDEC compliant board (6×6 VIAs on PAD)
1.5
17.6
0
Recommended layout (10×10 VIAs on PAD)
1.5
22.8
100
Recommended layout (10×10 VIAs on PAD)
1.5
13.8
The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 9 thermal vias (0.3 mm diameter).
θJP (Junction – Pad) is used for the QFN package, because the main heat flow is from the junction to the GND-pad of the QFN.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC,
AVCC,
VCC_CP
Supply voltage range (1)
–0.5
4.6
V
VI
Input voltage range (2)
–0.5 VCC + 0.5
V
VO
Output voltage range
(2)
V
VI < 0, VI > VCC
±20
mA
Output current for LVPECL/LVCMOS Outputs
0 < VO < VCC
±50
mA
125
°C
150
°C
TJ
Junction temperature
Tstg
Storage temperature range
(1)
(2)
–0.5 VCC + 0.5
Input current
–65
All supply voltages have to be supplied simultaneously.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
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CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
RECOMMENDED OPERATING CONDITIONS
for the CDCE72010 device for under the specified industrial temperature range of –40°C to 85°C
MIN
NOM
MAX
UNIT
Power Supply
VCC
Supply voltage
3
3.3
3.6
VCC_PLL,
VCC_IN,
VCC_VCXO,
VCCA
Analog supply voltage
3
3.3
3.6
VCC_CP
2.3
P LVPECL
REF at 30.72MHz VCXO at
491.52MHz Outputs are
LVPECL-HS
P LVDS
REF at 30.72MHz VCXO at
491.52MHz Outputs are LVDS-HS
P LVCMOS
REF at 30.72MHz VCXO at
122.88MHz Outputs are LVCMOS
P OFF
REF at 30.72MHz VCXO at
491.52MHz
P PD
Divider 1 set to divide by 8 (DCR
30%) Divider 2 set to divide by 4
(DCR 30%) Divider 3 set to divide
by 2 (DCR 30%) Divider 4 set to
divide by 2 (DCR 30%) Divider 5
set to divide by 1 (DCR 30%)
Divider 6 set to divide by 1 (DCR
0%) Divider 7 set to divide by 1
(DCR 0%) Divider 8 set to divide by
1 (DCR 0%) DCR: Divider Current
Reduction Setting
Dividers are disabled. Outputs are
disabled.
Device is powered down
VCC
V
V
2.9
W
2.0
W
2.2
W
775
mW
30
mW
Typical Operating Conditions at VCC=3.3V and 25°C unless otherwise specified.
Differential Input Mode (PRI_REF, SEC_REF, VCXO_IN and AUX_IN)
VINPP
Input amplitude (1)
VICM
Common-mode input voltage
IIH
Differential input current high ( No
internal termination)
VI = VCC, VCC = 3.6 V
IIL
Differential input current low( No
internal termination)
VI = 0 V, VCC = 3.6 V
(V_INP – VINN)
0.1
1.3
V
1.0
VCC– 0.3
V
20
µA
20
µA
–20
Input capacitance on PRI_REF, SEC_REF and VCXO_REF
3
pF
Input capacitance on AUX_IN
7
pF
LVCMOS Input Mode (SPI_CLK, SPI_MOSI, SPI_LE, PD, RESET, REF_SEL, MOD_SEL)
VIL
Low-level input voltage LVCMOS (2)
0
0.3 VCC
V
VIH
High-level input voltage LVCMOS (2)
0.7 VCC
VCC
V
VIK
LVCMOS input clamp voltage
VCC = 3 V, II = –18 mA
IIH
LVCMOS input current
VI = VCC, VCC = 3.6 V
IIL
LVCMOS input
VI = 0 V, VCC = 3.6 V
CI
Input capacitance (LVCMOS
signals)
VI = 0 V or VCC
(1)
(2)
6
–10
3
–1.2
V
20
µA
–40
µA
pF
VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP of
150mV.
VIL and VIH are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an AC coupling
to VCC/2 is provided.
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CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
TIMING REQUIREMENTS
over recommended ranges of supply voltage, load, and operating free-air temperature (1) (2) (3) (4)
PARAMETER
MIN
TYP
MAX
UNIT
PRI_REF/SEC_REFIN
fREF - Single
For single-ended inputs ( LVCMOS) on PRI_REF and SEC_REF
250
MHz
fREF - Diff
For differential inputs (LVDS and LVPECL) on PRI_REF and
SEC_REF
(R divider set to DIV2)
500
MHz
Duty Cycle
Single
Duty cycle of PRI_REF or SEC_REF at VCC/2
40%
Duty Cycle
Diff
Duty cycle of PRI_REF or SEC_REF at VCC/2
40%
60%
60%
VCXO_IN, AUX_IN
fREF - Single
For single-ended inputs ( LVCMOS)
fREF - Diff
For differential inputs (LVDS and LVPECL)
Duty Cycle
Single
Duty cycle of PRI_REF or SEC_REF at VCC/2
40%
Duty Cycle
Diff
Duty cycle of PRI_REF or SEC_REF at VCC/2
40%
250
MHz
1500
MHz
60%
60%
SPI/Control (SPI Bus Timing)
fCTRL_CLK
CTRL_CLK frequency
t2
SPI_MOSI to SPI_CLK setup time
10
20
MHz
ns
t3
SPI_MOSI to SPI_CLK hold time
10
ns
t4
SPI_CLK high duration
25
ns
t5
SPI_CLK low duration
25
ns
t1
SPI_LE to SPI_CLK setup time
10
ns
t6
SPI_CLK to SPI_LE setup time
10
ns
t7
SPI_LE pulse width
20
ns
t8
SPI_MISO to SPI_CLK data valid (first valid bit after LE)
10
ns
PD, RESET, Hold, REF_SEL
tr/tf
(1)
(2)
(3)
(4)
Rise and fall time of the PD, RESET, Hold, REF_SEL signal from 20%
to 80% of VCC
4
ns
From 250MHz to 500MHz is achieved by setting the divide by 2 in P’
If the feedback clock (derived from the VCXO input) is less than 2MHz, the device stays in normal operation mode but the frequency
detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This
affects the HOLD-Over-Function as well as the PLL_LOCK signal is no longer valid.
Use a square wave for lower frequencies (< 80 MHz).
Slew rate requirement
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CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
AC/DC CHARACTERISTICS
over the specified industrial temperature range of –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
SPI Output (MISO) / PLL Digital (Output Mode)
IOH
High-level output current
VCC = 3.3 V
VO = 1.65 V
–30
mA
IOL
Low-level output current
VCC = 3.3 V
VO = 1.65 V
33
mA
VOH
High-level output voltage
for LVCMOS outputs
VCC = 3 V
IOH = –100 µA
VOL
Low-level output voltage
for LVCMOS outputs
VCC = 3 V
IOL = 100 µA
CO
Output capacitance on
MISO
VCC = 3.3 V; VO = 0 V or VCC
IOZH
3-state output current
IOZL
3-state output current
VCC–0.5
V
0.3
V
3
pF
VO= VCC
VO= 0V
5
µA
–5
µA
22
µA
–22
µA
PLL Analog (Input Mode)
IOZH LOCK
High-impedance state
output current for PLL
LOCK output (2)
VO = 3.3 V (PD is set low)
IOZL LOCK
High-impedance state
output current for PLL
LOCK output
VO = 0 V (PD is set low)
VT+
Positive input threshold
voltage
VCC = min to max
VCC × 0.55
V
VT–
Negative input threshold
voltage
VCC = min to max
VCC × 0.35
V
VBB
VCXO termination voltage
depends on the settings
IBB = –0.2mA
of the VCXO/AUX_IN
Depending on the setting
input buffers
VBB
0.9
1.9
V
Input Buffers Internal Termination Resistors (VCXO_IN,PRI_REF and SEC_REF)
Termination resistance (3)
Single ended
Ω
53
Phase Detector
Maximum charge pump
frequency
fCPmax
Default PFD pulse width delay
100
MHz
Charge Pump
ICP3St
Charge pump 3-state
current
0.5 V < VCP < VCC_CP – 0.5 V
15
nA
ICPA
ICP absolute accuracy
VCP = 0.5 VCC_CP; internal reference resistor
20
%
ICPA
ICP absolute accuracy
VCP = 0.5 VCC_CP; external reference resistor
12kΩ (1%)
5
%
ICPM
Sink/source current
matching
0.5 V < VCP < VCC_CP – 0.5 V, SPI default
settings
4
%
IVCPM
ICP vs VCP matching
0.5 V < VCP < VCC_CP – 0.5 V
6
%
VI_REF_CP
Voltage on STATUS PIN
when configured as
I_REF_CP
12-kΩ resitor to GND
(External current path for accurate charge
pump current)
1.24
V
(1)
(2)
(3)
8
All typical values are at VCC = 3.3 V, TA = 25°C.
160-kΩ pull-down resistor
Termination resistor can vary by 20%.
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AC/DC CHARACTERISTICS (CONTINUED)
over the specified industrial temperature range of –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
250
MHz
LVCMOS Output
fclk
Output frequency (see
Figure 2 )
Load = 5 pF to GND
VOH
High-level output voltage
for LVCMOS outputs
VCC = min to max
IOH = –100 µA
VOL
Low-level output voltage
for LVCMOS outputs
VCC = min to max
IOL=100 µA
IOH
High-level output current
VCC = 3.3 V
VO = 1.65 V
–30
mA
IOL
Low-level output current
VCC = 3.3 V,
VO = 1.65 V
33
mA
tpho
Phase offset without
using available delay
adjustment
VCXO at 491.52MHz, Output 1 is divide by
16 and reference at 30.72MHz, M and N
delays are fixed to one value (set to 0).
13
ns
tpd(LH)/
Propagation delay from
VCXO_IN to Outputs
Crosspoint to VCC/2, load = 5 pF, (PLL
bypass mode)
3.3
ns
Divide by 1 for all dividers
75
Divide by 16 for all dividers
75
tpd(HL)
tsk(o)
Skew, output-to-output
LVCMOS single-ended
output
VCC – 0.5
V
0.3
Divide by 1 for divider 1 divide by 16 for all
other dividers
V
ps
1400
CO
Output capacitance on Y0
VCC = 3.3 V; VO = 0 V or VCC
to Y8
5
pF
CO
Output capacitance on Y9 VCC = 3.3 V; VO = 0 V or VCC
5
pF
IOZH
3-state LVCMOS output
current
VO = VCC
5
µA
IOZL
3-state LVCMOS output
current
VO = 0V
–5
µA
IOPDH
Power-down output
current
VO = VCC
25
µA
IOPDL
Power-down output
current
VO = 0V
5
µA
Duty cycle
LVCMOS
50% to 50%
45
55
%
tslew-rate
Output rise/fall slew rate
3.6
5.2
V/ns
(1)
All typical values are at VCC = 3.3 V, TA = 25°C.
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AC/DC CHARACTERISTICS (CONTINUED)
over the specified industrial temperature range of –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
0
800
MHz
160
270
mV
50
mV
LVDS Output
fclk
Output frequency
Open loop config. load, See Figure 2
|VOD|
Differential output voltage
RL = 100 Ω
ΔVOD
LVDS VOD magnitude
change
VOS
Offset voltage
ΔVOS
VOS magnitude change
tpho
(2)
tpd(LH)/
tpd(HL)
tsk(o)
(3)
–40°C to 85°C
1.24
V
40
mV
Short circuit VOUT+ to
ground
VOUT = 0
27
mA
Short circuit VOUT– to
ground
VOUT = 0
27
mA
Reference to output
phase offset without using
available delay
adjustment
VCXO at 491.52MHz, Output 1 is divide by
16 and reference at 30.72MHz, M and N
delays are fixed to one value (set to 0), PFD:
240kHz, (M and N = 128)
14
ns
Propagation delay time,
VCXO_IN to output
Crosspoint to crosspoint, load, see Figure 2
3.0
ns
Divide by 1 for all dividers
45
Divide by 16 for all dividers
50
Skew, output to output
LVDS output
Divide by 1 for divider 1
Divide by 16 for all other dividers
ps
2800
CO
Output capacitance on Y0
VCC = 3.3 V; VO = 0 V or VCC
to Y8
5
pF
CO
Output capacitance on Y9 VCC = 3.3 V; VO = 0 V or VCC 5
7
pF
IOPDH
Power-down output
current
VO = VCC
25
µA
IOPDL
Power-down output
current
VO = 0V
5
µA
Duty cycle
tr/tf
Rise and fall time
55
%
20% to 80% of Voutpp
110
45
140
160
ps
Crosspoint to VCC/2
0.9
1.4
1.9
ns
LVCMOS-TO-LVDS (4)
tskP_C
(1)
(2)
(3)
(4)
10
Output skew between
LVCMOS and LVDS
outputs
All typical values are at VCC = 3.3 V, TA = 25°C.
This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and
VCXO delay N).
The tsk(o) specification is only valid for equal loading of all outputs.
Operating the LVCMOS or LVDS outputs above the maximum frequency will not cause a malfunction to the device, but the output signal
swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.
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AC/DC CHARACTERISTICS (CONTINUED)
over the specified industrial temperature range of –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
0
800
MHz
270
550
mV
50
mV
LVDS Hi Swing Output
fclk
Output frequency
Open loop config. load, seeFigure 3
|VOD|
Differential output voltage
RL =100 Ω
ΔVOD
LVDS VOD magnitude
change
VOS
Offset voltage
ΔVOS
VOS magnitude change
tpho
(2)
tpd(LH)/
tpd(HL)
tsk(o)
(3)
–40°C to 85°C
1.24
V
40
mV
Short Circuit VOUT+ to
ground
VOUT = 0
27
mA
Short Circuit VOUT– to
ground
VOUT = 0
27
mA
Reference to output
phase offset without using
available delay
adjustment
VCXO at 491.52MHz, Output 1 is divide by
16 and reference at 30.72MHz. M and N
delays are fixed to one value. (Set to 0) PFD:
240kHz, (M and N = 128)
14
ns
Propagation delay time,
VCXO_IN to output
Crosspoint to crosspoint, load Figure 3
3.0
ns
Divide by 1 for all dividers
45
Divide by 16 for all dividers
50
LVDS output skew
Divide by 1 for divider 1
Divide by 16 for all other dividers
ps
2800
CO
Output capacitance on Y0
VCC = 3.3 V; VO = 0 V or VCC
to Y8
5
pF
CO
Output capacitance on Y9 VCC = 3.3 V; VO = 0 V or VCC
7
pF
IOPDH
Power-down output
current
VO = VCC
25
µA
IOPDL
Power-down output
current
VO = 0V
5
µA
55
%
Rise and fall time
20% to 80% of Voutpp
110
160
190
ps
Crosspoint to VCC/2
0.9
1.4
1.9
ns
Duty cycle
tr/tf
45
LVCMOS-TO-LVDS (4)
tskP_C
(1)
(2)
(3)
(4)
Output skew between
LVCMOS and LVDS
outputs
All typical values are at VCC = 3.3 V, TA = 25°C.
This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and
VCXO delay N).
The tsk(o) specification is only valid for equal loading of all outputs.
Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the output
signal swing may no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.
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AC/DC CHARACTERISTICS (CONTINUED)
over the specified industrial temperature range of –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
0
1500
MHz
LVPECL Output
fclk
Output frequency
VOH
LVPECL high-level output
Load, see Figure 5
voltage
VCC – 1.06
VCC – 0.88
V
VOL
LVPECL low-level output
voltage
Load, see Figure 5
VCC – 2.02
VCC – 1.58
V
|VOD|
Differential output voltage
Load, see Figure 5
610
970
tpho (2)
Reference to output
phase offset without using
available delay
adjustment
VCXO at 491.52MHz, Output 1 is divide by
16 and reference at 30.72MHz, M and N
delays are fixed to one value (set to 0), PFD:
240kHz, (M and N = 128)
14
ns
tpd(LH)/
tpd(HL)
Propagation delay time,
VCXO_IN to output
Crosspoint to crosspoint, load, see Figure 5
3.4
ns
Divide by 1 for all dividers
45
Divide by 16 for all dividers
50
tsk(o)
(3)
LVPECL output skew
Open loop config.
Divide by 1 for divider 1
Divide by 16 for all other dividers
mV
ps
2700
CO
Output capacitance on Y0
VCC = 3.3 V; VO = 0 V or VCC
to Y8
5
pF
CO
Output capacitance on Y9 VCC = 3.3 V; VO = 0 V or VCC
7
pF
IOPDH
Power-down output
current
VO = VCC
25
µA
IOPDL
Power-down output
current
VO = 0 V
5
µA
Duty cycle
tr/tf
Rise and fall time
55
%
20% to 80% of Voutpp
45
55
75
135
ps
Crosspoint to VCC/2;
0.9
1.1
1.3
ns
Crosspoint to VCC/2;
–150
260
700
ps
LVDS-TO-LVPECL
tskP_C
Output skew between
LVDS and LVPECL
outputs
LVCMOS-TO-LVPECL
tskP_C
(1)
(2)
(3)
(4)
12
Output skew between
LVCMOS and LVPECL
outputs (4)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and
VCXO delay N).
The tsk(o) specification is only valid for equal loading of all outputs. :
Operating the LVCMOS or LVPECL outputs above the maximum frequency will not cause a malfunction to the device, but the output
signal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS.
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AC/DC CHARACTERISTICS (CONTINUED)
over the specified industrial temperature range of –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP (1)
MAX
UNIT
0
1500
MHz
LVPECL Hi Swing Output
fclk
Output frequency
Open loop config.
VOH
LVPECL high-level
output voltage
Load, see Figure 5
VCC – 1.11
VCC – 0.87
V
VOL
LVPECL low-level output
Load, see Figure 5
voltage
VCC – 2.06
VCC – 1.73
V
|VOD|
Differential output
voltage
Load, see Figure 5
760
1160
Reference to output
phase offset without
using available delay
adjustment
VCXO at 491.52MHz, Output 1 is divide by 16
and reference at 30.72MHz, M and N delays
are fixed to one value (set to 0), PFD:
240kHz, (M and N = 128)
14
ns
Propagation delay time,
VCXO_IN to output
Crosspoint to crosspoint, load, see Figure 5
3.4
ns
Divide by 1 for all dividers
45
Divide by 16 for all dividers
50
tpho
(2)
tpd(LH)/
tpd(HL)
tsk(o)
(3)
LVPECL output skew
Divide by 1 for divider 1
Divide by 16 for all other dividers
mV
ps
2700
CO
Output capacitance on
Y0 to Y8
VCC = 3.3 V; VO = 0 V or VCC
5
pF
CO
Output capacitance on
Y9
VCC = 3.3 V; VO = 0 V or VCC
7
pF
IOPDH
Power-down output
current
VO = VCC
25
µA
IOPDL
Power-down output
current
VO = 0V
5
µA
55
%
Duty cycle
tr/tf
Rise and fall time
45
20% to 80% of Voutpp
55
75
135
ps
Crosspoint to VCC/2
0.9
1.1
1.3
ns
Crosspoint to VCC/2
–150
260
700
ps
LVDS-TO-LVPECL
tskP_C
Output skew between
LVDS and LVPECL
outputs
LVCMOS-TO-LVPECL
tskP_C
(1)
(2)
(3)
(4)
Output skew between
LVCMOS and LVPECL
outputs (4)
All typical values are at VCC = 3.3 V, TA = 25°C.
This is valid only for same REF_IN clock and Y output clock frequency. It can be adjusted by the SPI controller (reference delay M and
VCXO delay N).
The tsk(o) specification is only valid for equal loading of all outputs.
Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output
signal swing might no longer meet the output specification. The phase of LVCMOS is lagging in reference to the phase of LVDS and
LVPECL.
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PARAMETER MEASUREMENT INFORMATION
100 W
LVCMOS
Oscilloscope
5 pf
Figure 2. LVCMOS Output Termination Setup
Figure 3. LVDS DC Termination Setup
Oscilloscope
50 W
Oscilloscope
50 W
150 W
150 W
50 W
50 W
VCC-2
Figure 4. LVPECL AC Termination Setup
14
Figure 5. LVPECL DC Termination Setup
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TYPICAL CHARACTERISTICS
LVPECL OUTPUT SWING
vs
FREQUENCY
(mV)
1100
(mV)
1250
VCC = 3.6V
1050
Hi Swing LVPECL OUTPUT SWING
vs
FREQUENCY
TA = 25 ºC
Load 50 W to
VCC - 2C
1000
950
1100
VCC = 3.3V
1050
850
1000
800
950
750
900
700
VCC = 3.0V
800
750
Frequency - MHz
200
400
600
Frequency - MHz
800 1000 1200 1400 1600 1800
700
200
400
600
800 1000
1200 1400 1600 1800
Figure 6.
Figure 7.
LVDS OUTPUT SWING
vs
FREQUENCY
Hi Swing LVDS OUTPUT SWING
vs
FREQUENCY
(mV)
320
(mV)
500
300
TA = 25 ºC
Load 100 W
VCC = 3.6V
280
460
420
VCC = 3.3V
260
380
240
340
220
300
200
260
180
220
VCC = 3.0V
160
VCC = 3.3V
VCC = 3.6V
VCC = 3.0V
180
TA = 25 ºC
140 Load
100 W
140
120
100
VCC = 3.3V
850
VCC = 3.0V
650
550
VCC = 3.6V
1150
900
600
TA = 25 ºC
Load 50 W to
VCC– 2V
1200
100
Frequency - MHz
0
100
200
300
400
500
600
700
800
900
Frequency - MHz
60
0
100
Figure 8.
200
300
400
500
600
700
800
900
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
LVCMOS OUTPUT WING
vs
FREQUENCY
(V)
4.0
VC C = 3.6V
3.8
3.6
TA = 25 ºC
Load 5pF
VCC = 3.3V
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
VCC = 3.0V
Frequency - MHz
100
200
300
400
500
Figure 10.
16
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APPLICATION INFORMATION
PHASE NOISE ANALYSIS
Phase noise is measured in a closed loop mode of 491.52MHz VCXO and 30.72MHz reference and a 100Hz
loop. Output 1 is measured for divide by one, output 6 for divide by 4, and output 9 for divide by 16.
Table 1. Phase Noise for LVPECL High Swing
Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by
4 = 122.88MHz, Divide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA, Loop BW = 100Hz, Output 1 =
491.52 MHZ, Output Buffer: LVPECL-HS
PHASE NOISE
AT OFFSET
VCXO OPEN
LOOP
REFERENCE
30.72MHz
LVPECL-HS
DIVIDE BY 1
LVPECL-HS
DIVIDE BY 4
LVPECL-HS
DIVIDE BY 16
UNIT
10Hz
–64
–107
100Hz
–99
–123
–80
–92
–105
dBc/Hz
–92
–104
–116
dBc/Hz
1kHz
–113
10kHz
–135
–134
–115
–127
–139
dBc/Hz
–153
–135
–145
–158
100kHz
dBc/Hz
–148
–156
–146
–155
–162
dBc/Hz
1MHz
–148
–158
–146
–155
–162
dBc/Hz
10MHz
–149
–147
–156
dBc/Hz
Table 2. Phase Noise for LVDS High Swing
Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by
4 = 122.88MHz, DIvide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA Loop BW = 100Hz, Output 1 =
491.52 MHZ, Output Buffer: LVDS-HS
VCXO OPEN
LOOP
REFERENCE
LVDS–HS
DIVIDE BY 1
LVDS-HS
DIVIDE BY 4
LVDS-HS
DIVIDE BY 16
UNIT
10Hz
–64
–107
100Hz
–99
–123
–82
–94
–104
dBc/Hz
–92
–105
–117
1kHz
–113
dBc/Hz
–134
–114
–127
–139
10kHz
dBc/Hz
–135
–153
–135
–145
–151
dBc/Hz
100kHz
–148
–156
–145
–152
–153
dBc/Hz
1MHz
–148
–158
–146
–152
–153
dBc/Hz
10MHz
–149
–146
–152
PARAMETER
dBc/Hz
Table 3. Phase Noise for LVCMOS
Phase Noise Specifications under following configuration: VCXO = 491.52MHz, REF = 30.72MHz, Divide by = 491.52MHz, Divide by
4 = 122.88MHz, DIvide by 16 = 30.72MHz, PFD Frequency = 240KHz, Charge Pump Current = 2mA, Loop BW = 100Hz, Output 1 =
491.52 MHZ, Output Buffer: LVCMOS
VCXO OPEN
LOOP
REFERENCE
LVCMOS
DIVIDE BY 4
LVCMOS
DIVIDE BY 16
UNIT
10Hz
–64
100Hz
–99
–107
–91
–105
dBc/Hz
–123
–104
–116
dBc/Hz
1kHz
10kHz
–113
–134
–127
–139
dBc/Hz
–135
–153
–140
–151
dBc/Hz
100kHz
–148
–156
–151
–159
dBc/Hz
1MHz
–148
–158
–153
–160
dBc/Hz
10MHz
–149
PARAMETER
N/A
–154
dBc/Hz
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SPI CONTROL INTERFACE
The serial interface of the CDCE72010 is a simple bidirectional SPI interface for writing and reading to and from
the registers of the device. It consists of four control lines: SPI_CLK, SPI_MOSI, SPI_MISO, and SPI_LE. There
are twelve 28-bit wide registers that can be saved to the EEPROM on-chip, and one status register that is a read
only register. Those registers can be addressed by the four LSBs of a transferred word (bit 0, 1, 2, and bit 3).
Every transmitted word must have 32 bits, starting with LSB first. Each word can be written separately. The
transfer is initiated with the falling edge of SPI_LE; as long as SPI_LE is high, no data can be transferred. During
SPI_LE low, data can be written. The data has to be applied at SPI_MOSI and has to be stable before the rising
edge of SPI_CLK. The transmission is finished by a rising edge of SPI_LE.
t4
t5
SPI_CLK
t2
SPI_MOSI
Bit0
t3
Bit1
……
Bit29
Bit30
Bit31
t7
SPI_LE
t6
t1
Figure 11. Timing Diagram for SPI Write Command
SPI_CLK
t3
t2
SPI_MOSI
Bit30
Bit31
SPI_MISO
Bit0
Bit1
Bit2
t7
SPI_LE
t6
t8
Figure 12. Timing Diagram for SPI Read Command
18
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Table 4. Register Map
REGISTER
COMMENTS
WRITE PAYLOAD ( DATA)
WRITE COMMAND ON MOSI
ADDRESS
31,30,29,28….…………..…………………………………….………4,3,2,1,0
Register0
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
0000
Register1
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
0001
Register2
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
0010
Register3
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
0011
Register4
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
0100
Register5
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
0101
Register6
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
0110
Register7
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
0111
Register8
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
1000
Register9
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
1001
Register10
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
1010
Register11
Configuration
RAM/EEPROM
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
1011
Register12
Status/Control
RAM Only
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
1100
Register13
Reserved
XXXX XXXX XXXX XXXX XXXX XXXX XXXX
1101
Instruction
Read command (address on 4 LSBs of
payload)
XXXX XXXX XXXX XXXX XXXX XXXX AAAA
1110
Instruction
Write configuration to EEPROM - UNLOCKED XXXX XXXX XXXX XXXX XXXX XXXX 0001
1111
Instruction
Write configuration to EEPROM – LOCKED
1111
READ COMMAND ON MISO
DATA PAYLOAD IN READ COMMAND
Payload after issuing a read command on
MOSI
(1)
XXXX XXXX XXXX XXXX 1010 XXXX 0011
DDDD DDDD DDDD DDDD DDDD DDDD DDDD
XXXX (1)
During a SPI READ instruction the address field of the payload should be ignored since it does not represent the address of the read
register.
The SPI serial protocol accepts Word Write operation only. The 12 words include the register settings of the
programmable functions of the device that can be modified to the customer application by changing one or more
bits.
At powerup or if the Power Down (PD) control signal is applied, the EEPROM loads its content into the registers.
When issuing an EEPROM programming (LOCKED or UNLOCKED) instruction, a wait period of 50ms has to be
inserted before another instruction is written to the device or power is removed.
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CDCE72010 Default Configuration
The CDCE72010 on-board EEPROM has been factory preset to the default settings listed in Table 5
Table 5. CDCE72010 Default Configuration Settings
REGISTER
DEFAULT SETTING
REGISTER
DEFAULT SETTING
REG0000
002C0040
REG0007
EB040717
REG0001
83840051
REG0008
010C0158
REG0002
83400002
REG0009
01000049
REG0003
83400003
REG0010
0BFC07CA
REG0004
81800004
REG0011
C000058B
REG0005
81800005
REG0012
61E09B0C
REG0006
EB040006
The default configuration programmed in the EEPROM is: a 10MHz primary reference single-ended, a
491.52MHz LVPECL VCXO running at 80kHz, and PFD with a 10Hz external loop filter. Reference Auto Select is
off, M divider is set for 125, N divider is set to 768, charge pump current is set to 2.2mA, and feedback divider is
set to divide by 8. Divider 1 is set to divide by 4, Dividers 2 and 3 are set to divide by 1, Dividers 4 and 5 are set
to divide by 2, Dividers 6 and 7 are set to divide by 8, and Divider 8 is set to divide by 16.Output0:LVCMOS,
Output1:Hi-LVPECL, Output2: Hi-LVPECL, Output3:Hi_LVPECL, Output4:LVPECL, Output5:LVPECL,
Output6:Hi-LVDS, Output7:Hi-LVDS, Output8:LVCMOS and Output9:LVCMOS.
20
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Register 0: SPI Mode
SPI
BIT
RAM
Bit
BIT NAME
RELATED BLOCK
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
0
4
0
INBUFSELX
5
1
INBUFSELY
6
2
PRISEL
7
3
SECSEL
8
4
VCXOSEL
9
5
REFSELCNTRL
10
6
DELAY_PFD0
11
7
DELAY_PFD1
12
8
CP_MODE
13
9
CP_DIR
14
10
CP_SRC
Reference Input
Buffers
Primary and secondary Buffer Type Select (LVPECL,LVDS or LVCMOS)
XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive pin
EEPROM
Reference Input
Buffer
When REFSELCNTRL is set to 1, the following settings apply:
If RAM Bits (2,3): 00 – No input buffer is selected/active
If RAM Bits (2,3): 10 – PRI_BUF is selected, SEC_BUF is powered down
If RAM Bits (2,3): 01 – SEC_BUF is selected, PRI_BUF is powered down (1)
If RAM Bits (2,3): 11 – Auto Select (PRI then SEC).
EEPROM
Divider START
DETERM-Block
When set to 0, PRI- or SEC-clock is selected, depending on bits 2 and 3
(default)
When set to 1, VCXO/AUX-clock is selected, overwrites bits 2 and 3
EEPROM
Reference Select Control to select if the control of the reference is from the
internal bit in Register 0 RAM bits 2 and 3 or from the external select pin.
- When set to 0: the external pin REF_SEL takes over the selection between
PRI and SEC. Autoselect is not available.
- When set to 1: The external pin REF_SEL is ignored. The table in (Register 0
<2 and 3> ) describes which reference input clock is selected and available
(none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing
diagram.
EEPROM
PFD pulse width PFD bit 0
PFD pulse width PFD bit 1
EEPROM
Selects 3V option [0] or 5V option [1]
EEPROM
Determines which direction CP current will regulate (Reference Clock leads to
Feedback Clock, Positive CP output current [0], Negative CP output current [1])
EEPROM
Switches the current source in the charge pump on when set to 1 (TI
Test-GTME)
EEPROM
Reference
Selection
Control
PFD
Charge Pump
Charge Pump
Diagnostics
15
11
CP_SNK
Switches the current sink in the charge pump on when set to 1 (TI Test-GTME)
EEPROM
16
12
CP_OPA
Switches the charge pump op-amp off when set to 1 (TI Test-GTME)
EEPROM
17
13
CP_PRE
Preset charge pump output voltage to VCC_CP/2, on [1], off [0]
EEPROM
18
14
ICP0
CP current setting bit 0
EEPROM
19
15
ICP1
CP current setting bit 1
EEPROM
20
16
ICP2
CP current setting bit 2
EEPROM
21
17
ICP3
CP current setting bit 3
EEPROM
22
18
RESERVED
23
19
RESERVED
24
20
IREFRES
25
21
PECL0HISWING
26
22
CMOSMODE0PX
27
23
CMOSMODE0PY
28
24
CMOSMODE0NX
29
25
CMOSMODE0NY
30
26
OUTBUFSEL0X
Charge Pump
EEPROM
EEPROM
Charge Pump
Diagnostics
Enables the 12-kΩ pull-down resistor at I_REF_CP pin when set to 1 (TI
Test-GTME)
EEPROM
Output 0
High output voltage swing in LVPECL mode if set to 1
EEPROM
Output 0
LVCMOS mode select for OUTPUT 0 positive pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
Output 0
LVCMOS mode select for OUTPUT 0 negative pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
Output 0
OUTPUT TYPE
LVPECL
LVDS
31
27
OUTBUFSEL0Y
Output 0
LVCMOS
All Outputs Disabled
(1)
(2)
POWER UP
CONDITION
DESCRIPTION/FUNCTION
RAM BITS
22
23
24
25
26
27
0
0
0
0
0
1
0
1
0
1
1
1
See Settings Above (2)
0
0
1
0
0
1
0
1
EEPROM
EEPROM
This setting is only available if the Register 11 Bit 2 is set to 0 (Feedback Divider clock is set to CMOS type).
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.
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Register 1: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED BLOCK
0
A0
Address 0
1
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
0
4
0
ACDCSEL
Input Buffers
If set to 0 AC Termination, If set to 1 DC termination
EEPROM
5
1
HYSTEN
Input Buffers
If set to 1 Input Buffers Hysteresis enabled
EEPROM
6
2
TERMSEL
Input Buffers
If set to 0 Input Buffer Internal Termination enabled
EEPROM
7
3
PRIINVBB
Input Buffers
If set to 1 Primary Input Negative pin biased with internal VBB voltage
EEPROM
8
4
SECINVBB
Input Buffers
If set to 1 Secondary Input Negative pin biased with internal VBB voltage
EEPROM
9
5
FAILSAFE
Input Buffers
If set to 1 Fail Safe is enabled for all input buffers
EEPROM
10
6
PH1ADJC0
11
7
PH1ADJC1
12
8
PH1ADJC2
13
9
PH1ADJC3
Output 0 and 1
Coarse phase adjust select for Output Divider 1
EEPROM
14
10
PH1ADJC4
15
11
PH1ADJC5
16
12
PH1ADJC6
17
13
OUT1DIVRSEL0
18
14
OUT1DIVRSEL1
19
15
OUT1DIVRSEL2
20
16
OUT1DIVRSEL3
Output 0 and 1
Output Divider 1 ratio select
(seeTable 7)
EEPROM
21
17
OUT1DIVRSEL4
22
18
OUT1DIVRSEL5
23
19
OUT1DIVRSEL6
24
20
EN01DIV
Output 0 and 1
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
25
21
PECL1HISWING
Output 1
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
26
22
CMOSMODE1PX
27
23
CMOSMODE1PY
Output 1
LVCMOS mode select for OUTPUT 1 Positive Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
28
24
CMOSMODE1NX
29
25
CMOSMODE1NY
Output 1
LVCMOS mode select for OUTPUT 1 Negative Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
30
26
OUTBUFSEL1X
OUTPUT TYPE
Output 1
LVPECL
LVDS
31
27
OUTBUFSEL1Y
Output 1
LVCMOS
All Outputs Disabled
(1)
22
POWER UP
CONDITION
DESCRIPTION/FUNCTION
RAM BITS
22
23
24
25
26
27
0
0
0
0
0
1
0
1
0
1
1
1
See Settings Above (1)
0
0
1
0
0
1
0
1
EEPROM
EEPROM
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.
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Register 2: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED BLOCK
0
A0
Address 0
0
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
0
Reference phase delay M bit0
4
0
DLYM0
5
1
DLYM1
6
2
DLYM2
7
3
DLYN0
8
4
DLYN1
9
5
DLYN2
10
6
PH2ADJC0
11
7
PH2ADJC1
12
8
PH2ADJC2
13
9
PH2ADJC3
14
10
PH2ADJC4
15
11
PH2ADJC5
16
12
PH2ADJC6
17
13
OUT2DIVRSEL0
18
14
OUT2DIVRSEL1
19
15
OUT2DIVRSEL2
20
16
OUT2DIVRSEL3
21
17
OUT2DIVRSEL4
22
18
OUT2DIVRSEL5
23
19
OUT2DIVRSEL6
24
20
25
26
DELAY M
Reference phase delay M bit1
EEPROM
Reference phase delay M bit2
Feedback phase delay N bit0
DELAY N
Feedback phase delay N bit1
EEPROM
Feedback phase delay N bit2
Output 2
Coarse phase adjust select for output divider 2
EEPROM
Output 2
Output Divider 2 ratio select
(seeTable 7)
EEPROM
EN2DIV
Output 2
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
21
PECL2HISWING
Output 2
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
22
CMOSMODE2PX
27
23
CMOSMODE2PY
Output 2
LVCMOS mode select for OUTPUT 2 Positive Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
28
24
CMOSMODE2NX
29
25
CMOSMODE2NY
Output 2
LVCMOS mode select for OUTPUT 2 Negative Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
30
26
OUTBUFSEL2X
OUTPUT TYPE
Output 2
LVPECL
LVDS
31
27
OUTBUFSEL2Y
Output 2
LVCMOS
All Outputs Disabled
(1)
POWER UP
CONDITION
DESCRIPTION/FUNCTION
RAM BITS
22
23
24
25
26
27
0
0
0
0
0
1
0
1
0
1
1
1
See Settings Above (1)
0
0
1
0
0
1
0
1
EEPROM
EEPROM
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs.
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Register 3: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED BLOCK
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
0
When set to 0, the REF-clock frequency detector is ON
When set to 1, it is switched OFF
EEPROM
When set to 1, the feedback path frequency detector is switched OFF
(TI Test-GTME)
EEPROM
Output Divider
0 and 1
When BIAS_DIV01<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
Output Divider
2 and 3
When BIAS_DIV23<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
Output 3
Coarse phase adjust select for Output Divider 3
EEPROM
Output 3
Output Divider 3 ratio select
(seeTable 7)
EEPROM
4
0
DIS_FDET_REF
5
1
DIS_FDET_FB
6
2
BIAS_DIV01<0>
7
3
BIAS_DIV01<1>
8
4
BIAS_DIV23<0>
PLL Freq. Detect
Diagnostics
9
5
BIAS_DIV23<1>
10
6
PH3ADJC0
11
7
PH3ADJC1
12
8
PH3ADJC2
13
9
PH3ADJC3
14
10
PH3ADJC4
15
11
PH3ADJC5
16
12
PH3ADJC6
17
13
OUT3DIVRSEL0
18
14
OUT3DIVRSEL1
19
15
OUT3DIVRSEL2
20
16
OUT3DIVRSEL3
21
17
OUT3DIVRSEL4
22
18
OUT3DIVRSEL5
23
19
OUT3DIVRSEL6
24
20
EN3DIV
Output 3
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
25
21
PECL3HISWING
Output 3
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
26
22
CMOSMODE3PX
27
23
CMOSMODE3PY
Output 3
LVCMOS mode select for OUTPUT 3 Positive Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
28
24
CMOSMODE3NX
29
25
CMOSMODE3NY
Output 3
LVCMOS mode select for OUTPUT 3 Negative Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
30
26
OUTBUFSEL3X
31
27
OUTBUFSEL3Y
OUTPUT TYPE
Output 3
Output 3
24
RAM BITS
22
23
24
25
26
27
LVPECL
0
0
0
0
0
1
LVDS
0
1
0
1
1
1
See Settings Above (1)
0
0
1
0
LVCMOS
All Outputs Disabled
(1)
POWER UP
CONDITION
DESCRIPTION/FUNCTION
0
1
0
1
EEPROM
EEPROM
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
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Register 4: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED BLOCK
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
1
3
A3
Address 3
0
4
0
RESERVED
EEPROM
5
1
RESERVED
EEPROM
6
2
RESERVED
EEPROM
7
3
RESERVED
8
4
HOLDONLOR
9
5
RESERVED
10
6
PH4ADJC0
11
7
PH4ADJC1
12
8
PH4ADJC2
13
9
PH4ADJC3
14
10
PH4ADJC4
15
11
PH4ADJC5
16
12
PH4ADJC6
17
13
OUT4DIVRSEL0
18
14
OUT4DIVRSEL1
19
15
OUT4DIVRSEL2
20
16
OUT4DIVRSEL3
21
17
OUT4DIVRSEL4
22
18
OUT4DIVRSEL5
23
19
OUT4DIVRSEL6
24
20
25
26
EEPROM
HOLD-Over
If set to 1 it will 3-state the charge pump to act as a HOLD on Loss of
Reference Clocks ( Primary and Secondary)
EEPROM
EEPROM
Output 4
Coarse phase adjust select for Output Divider 4
EEPROM
Output 4
Output Divider 4 ratio select
(seeTable 7)
EEPROM
EN4DIV
Output 4
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
21
PECL4HISWING
Output 4
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
22
CMOSMODE4PX
27
23
CMOSMODE4PY
Output 4
LVCMOS mode select for OUTPUT 4 Positive Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
28
24
CMOSMODE4NX
29
25
CMOSMODE4NY
Output 4
LVCMOS mode select for OUTPUT 4 Negative Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
30
26
OUTBUFSEL4X
OUTPUT TYPE
Output 4
LVPECL
LVDS
31
27
OUTBUFSEL4Y
Output 4
LVCMOS
All Outputs Disabled
(1)
POWER UP
CONDITION
DESCRIPTION/FUNCTION
RAM BITS
22
23
24
25
26
27
0
0
0
0
0
1
0
1
0
1
1
1
See Settings Above (1)
0
0
1
0
0
1
0
1
EEPROM
EEPROM
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
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Register 5: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED BLOCK
0
A0
Address 0
1
1
A1
Address 1
0
2
A2
Address 2
1
3
A3
Address 3
0
Output Divider
4 and 5
When BIAS_DIV45<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
Output Divider
6 and 7
When BIAS_DIV67<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
4
0
BIAS_DIV45<0>
5
1
BIAS_DIV45<1>
6
2
BIAS_DIV67<0>
7
3
BIAS_DIV67<1>
8
4
RESERVED
EEPROM
9
5
RESERVED
EEPROM
10
6
PH5ADJC0
11
7
PH5ADJC1
12
8
PH5ADJC2
13
9
PH5ADJC3
14
10
PH5ADJC4
15
11
PH5ADJC5
16
12
PH5ADJC6
17
13
OUT5DIVRSEL0
18
14
OUT5DIVRSEL1
19
15
OUT5DIVRSEL2
20
16
OUT5DIVRSEL3
21
17
OUT5DIVRSEL4
22
18
OUT5DIVRSEL5
23
19
OUT5DIVRSEL6
24
20
25
26
Output 5
Coarse phase adjust select for Output Divider 5
EEPROM
Output 5
Output Divider 5 ratio select
(seeTable 7)
EEPROM
EN5DIV
Output 5
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
21
PECL5HISWING
Output 5
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
22
CMOSMODE5PX
27
23
CMOSMODE5PY
Output 5
LVCMOS mode select for OUTPUT 5 Positive Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
28
24
CMOSMODE5NX
29
25
CMOSMODE5NY
Output 5
LVCMOS mode select for OUTPUT 5 Negative Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
30
26
OUTBUFSEL5X
31
27
OUTBUFSEL5Y
OUTPUT TYPE
Output 5
Output 5
26
RAM BITS
22
23
24
LVPECL
0
0
0
LVDS
0
1
0
LVCMOS
All Outputs Disabled
(1)
POWER UP
CONDITION
DESCRIPTION/FUNCTION
25
26
27
0
0
1
1
1
1
0
0
1
0
See Settings Above (1)
0
1
0
1
EEPROM
EEPROM
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
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Register 6: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED BLOCK
POWER UP
CONDITION
DESCRIPTION/FUNCTION
0
A0
Address 0
0
1
A1
Address 1
1
2
A2
Address 2
1
3
A3
Address 3
0
0 Feedback Frequency Detector is connected to the Lock Detector
1 Feedback Frequency Detector is disconnected from the Lock Detector
4
0
FB_FD_DESEL
5
1
RESERVED
Set to 0
6
2
FBDETERM_DIV_SEL
0 FB-Deterministic Clock divided by 1
1 FB- Deterministic Clock divided by 2
7
3
FBDETERM_DIV2_DIS
8
4
FB_START_BYPASS
9
5
DET_START_BYPASS
10
6
PH6ADJC0
11
7
PH6ADJC1
12
8
PH6ADJC2
13
9
PH6ADJC3
14
10
PH6ADJC4
15
11
PH6ADJC5
16
12
PH6ADJC6
17
13
OUT6DIVRSEL0
18
14
OUT6DIVRSEL1
19
15
OUT6DIVRSEL2
20
16
OUT6DIVRSEL3
21
17
OUT6DIVRSEL4
22
18
OUT6DIVRSEL5
23
19
OUT6DIVRSEL6
24
20
25
26
LOCK-DET
EEPROM
FB0 FB-Deterministic-DIV2-Block in normal operation
Divider/Deterministi
1 FB-Deterministic-DIV2 reset (here REG6_RB<2> == 0)
c Blocks
0 FB-Divider started with delay block (RC), normal operation
1 FB-Divider can be started with external REF_SEL-signal (pin)
All Output Dividers
EEPROM
0 Output-Dividers started with delay block (RC), normal operation
1 Output-Dividers can be started with external NRESET-signal (pin)
EEPROM
Coarse phase adjust select for Output Divider 6
EEPROM
Output 6
Output Divider 6 ratio select
(seeTable 7)
EEPROM
EN6DIV
Output 6
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
21
PECL6HISWING
Output 6
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
22
CMOSMODE6PX
27
23
CMOSMODE6PY
Output 6
LVCMOS mode select for OUTPUT 6 Positive Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
28
24
CMOSMODE6NX
29
25
CMOSMODE6NY
Output 6
LVCMOS mode select for OUTPUT 6 Negative Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
30
26
OUTBUFSEL6X
Output 6
OUTPUT TYPE
Output 6
LVPECL
LVDS
31
27
OUTBUFSEL6Y
Output 6
LVCMOS
All Outputs Disabled
(1)
RAM BITS
22
23
24
25
26
27
0
0
0
0
0
1
0
1
0
1
1
1
0
0
1
0
See Settings Above (1)
0
1
0
1
EEPROM
EEPROM
Use description for bits 22,23,24, and 25 for setting the LVCMOS outputs
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Register 7: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED BLOCK
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
1
3
A3
Address 3
0
4
0
LOCKW 0
Lock-detect window Bit 0 (Refer to Reg 9 RAM Bits 6 and 7)
5
1
LOCKW 1
Lock-detect window Bit 1 (Refer to Reg 9 RAM Bits 6 and 7)
6
2
RESERVED
7
3
LOCKC0
8
4
LOCKC1
Number of coherent lock events Bit 1
9
5
ADLOCK
Selects Digital PLL_LOCK 0, Selects Analog PLL_LOCK 1
10
6
PH7ADJC0
11
7
PH7ADJC1
12
8
PH7ADJC2
13
9
PH7ADJC3
14
10
PH7ADJC4
15
11
PH7ADJC5
16
12
PH7ADJC6
17
13
OUT7DIVRSEL0
18
14
OUT7DIVRSEL1
19
15
OUT7DIVRSEL2
20
16
OUT7DIVRSEL3
21
17
OUT7DIVRSEL4
22
18
OUT7DIVRSEL5
23
19
OUT7DIVRSEL6
24
20
25
26
LOCK-DET
Number of coherent lock events Bit 0
EEPROM
Output 7
Coarse phase adjust select for Output Divider 7
EEPROM
Output 7
Output Divider 7 ratio select
(seeTable 7)
EEPROM
EN7DIV
Output 7
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
21
PECL7HISWING
Output 7
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
22
CMOSMODE7PX
27
23
CMOSMODE7PY
Output 7
LVCMOS mode select for OUTPUT 7 Positive Pin
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
28
24
CMOSMODE7NX
29
25
CMOSMODE7NY
Output 7
LVCMOS mode select for OUTPUT 7 Negative Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
30
26
OUTBUFSEL7X
OUTPUT TYPE
Output 7
LVDS
31
27
OUTBUFSEL7Y
Output 7
LVCMOS
All Outputs Disabled
28
EEPROM
Set to 0
LVPECL
(1)
POWER UP
CONDITION
DESCRIPTION/FUNCTION
RAM BITS
22
23
24
0
0
0
0
1
0
26
27
0
1
1
1
1
See Settings Above (1)
0
0
1
0
0
1
0
25
0
1
EEPROM
EEPROM
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
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CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
Register 8: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED BLOCK
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
1
VCXO and AUX Input Buffer Type Select (LVPECL,LVDS or LVCMOS)
XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin
4
0
VCXOBUFSELX
5
1
VCXOBUFSELY
6
2
VCXOACDCSEL
7
3
VCXOHYSTEN
8
4
VCXOTERMSEL
9
5
VCXOINVBB
10
6
PH8ADJC0
11
7
PH8ADJC1
12
8
PH8ADJC2
13
9
PH8ADJC3
14
10
PH8ADJC4
15
11
PH8ADJC5
16
12
PH8ADJC6
17
13
OUT8DIVRSEL0
18
14
OUT8DIVRSEL1
19
15
OUT8DIVRSEL2
20
16
OUT8DIVRSEL3
21
17
OUT8DIVRSEL4
22
18
OUT8DIVRSEL5
23
19
OUT8DIVRSEL6
24
20
EN89DIV
25
21
PECL8HISWING
26
22
CMOSMODE8PX
27
23
CMOSMODE8PY
28
24
CMOSMODE8NX
29
25
CMOSMODE8NY
30
26
OUTBUFSEL8X
VCXO and AUX
Input Buffers
If Set to 0 AC Termination, If set to 1 DC Termination
If Set to 0 Input Buffer Internal Termination enabled
VCXO Input Buffer
If Set to 1 It Biases VCXO Input negative pin with internal VCXOVBB Voltage
EEPROM
Output 8 and 9
Coarse phase adjust select for Output Divider 8
EEPROM
Output 8 and 9
Output Divider 8 ratio select
(seeTable 7)
EEPROM
Output 8 and 9
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
Output 8
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
Output 8
LVCMOS mode select for OUTPUT 8 Positive Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
Output 8
LVCMOS mode select for OUTPUT 8 Negative Pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
OUTPUT TYPE
Output 8
LVDS
31
27
OUTBUFSEL8Y
EEPROM
If Set to 1 Input Buffers Hysteresis enabled
LVPECL
Output 8
LVCMOS
All Outputs Disabled
(1)
POWER UP
CONDITION
DESCRIPTION/FUNCTION
RAM BITS
22
23
24
25
26
27
0
0
0
0
0
1
0
1
0
1
1
1
See Settings Above (1)
0
0
1
0
0
1
0
1
EEPROM
EEPROM
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
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Register 9: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
0
A0
Address 0
1
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
1
Enables the Frequency Hold-Over (External Hold Over Function based on the
external circuitry) on 1, off 0
4
0
HOLDF
5
1
RESERVED
6
2
HOLD
7
3
HOLDTR
8
4
HOLD_CNT0
3-State Charge Pump 0 - (equal to HOLD pin function)
HOLD function always activated 1 (recommended for test purposes, only)
Triggered by analog PLL Lock detect outputs
If analog PLL Lock Signal is [1] (PLL locked), HOLD is activated
If analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated
HOLD-Over
9
5
HOLD_CNT1
10
6
LOCKW 2
11
7
LOCKW 3
12
8
NOINV_RESHOL_INT
13
9
DIVSYNC_DIS
When GTME = 0, this Bit has no functionality, But when GTME = 1, then:
Diagnostic: PLL
When set to 0, START-Signal is synchronized to N/M Divider Input Clocks
N/M Divider
When set to 1, START-Sync N/M Divider in PLL are bypassed
EEPROM
14
10
START_BYPASS
Divider START When set to 0, START-Signal is synchronized to VCXO-Clock
DETERM-Block When set to 1, START-Sync Block is bypassed
EEPROM
15
11
INDET_BP
Divider START When set to 0, Sync Logic active when VCXO/AUX-Clocks are available
DETERM-Block When set to 1, Sync Logic is independent from VCXO- and/or AUX-Clocks
EEPROM
16
12
PLL_LOCK_BP
Divider START When set to 0, Sync Logic waits for 1st PLL_LOCK state
DETERM-Block When set to 1, Sync Logic independent from 1st PLL_LOCK
EEPROM
17
13
LOW_FD_FB_EN
When set to 0, Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD)
Divider START
When set to 1, Sync Logic is started for VCXO/DIV_FB > ~600KHz, stopped for
DETERM-Block
VCXO/DIV_FB < ~600KHz
EEPROM
18
14
NPRESET_MDIV
19
15
BIAS_DIV_FB<0>
20
16
BIAS_DIV_FB<1>
21
17
BIAS_DIV89<0>
22
18
BIAS_DIV89<1>
23
19
AUXINVBB
24
20
DIS_AUX_Y9
25
21
PECL9HISWING
26
22
CMOSMODE9PX
27
23
CMOSMODE9PY
28
24
CMOSMODE9NX
29
25
CMOSMODE9NY
30
26
OUTBUFSEL9X
Extended Lock-detect window Bit 2 (also refer to Reg 7 RAM Bits 0 and 1)
LOCK-DET
When set to 0, SPI/HOLD_INT and SPI/RESET_INT inverted (default)
When set to 1, SPI/HOLD_INT and SPI/RESET_INT not inverted
Chip CORE
PLL
M/FB-Divider
Feedback
Divider
Output Divider
8 and 9
AUX Input
Buffer
27
OUTBUFSEL9Y
EEPROM
Extended Lock-detect window Bit 3 (also refer to Reg 7 RAM Bits 0 and 1)
EEPROM
When set to 0, M-Divider uses NHOLD as NPRESET
When set to 1, M-Divider NOT preseted by NHOLD
EEPROM
When BIAS_DIV_FB<1:0> =
00, No current reduction for FB-Divider
01, Current reduction for FB-Divider by about 20%
10, Current reduction for FB-Divider by about 30%
EEPROM
When BIAS_DIV89<1:0> =
00, No current reduction for all output-rivider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
If set to 1 it biases AUX Input Negative pin with internal VCXOVBB voltage.
If set to 1 AUX in Input Mode Buffer Is disabled. If set to 0 it follows the behavior of
FB_MUX_SEL and OUT_MUX_SEL bits settings.
EEPROM
Output 9
High output voltage swing in LVPECL Mode if set to 1
EEPROM
Output 9
LVCMOS mode select for OUTPUT 9 Positive pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
Output 9
LVCMOS mode select for OUTPUT 9 Negative pin.
(X,Y) = 00: Active, 10: Inverting, 11: Low, 01: 3-State
EEPROM
OUTPUT TYPE
Output 9
LVDS
31
Output 9
LVCMOS
All Outputs Disabled
30
EEPROM
HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by
(HOLD_CNT0,HOLD_CNT1) : X = Number of Clock Cycles.
For (00) : X = 64, (01) : X = 128, (10) : X = 256, (11) : X = 512 Clock Cycles
LVPECL
(1)
POWER UP
CONDITION
DESCRIPTION/FUNCTION
RAM BITS
22
23
24
25
26
27
0
0
0
0
0
1
0
1
0
1
1
1
See Settings Above (1)
0
0
1
0
0
1
0
1
EEPROM
EEPROM
Use description for bits 22, 23, 24, and 25 for setting the LVCMOS outputs
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CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
Register 10: SPI Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
0
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
1
4
0
M0
Reference Divider M Bit 0
5
1
M1
Reference Divider M Bit 1
6
2
M2
Reference Divider M Bit 2
7
3
M3
Reference Divider M Bit 3
8
4
M4
Reference Divider M Bit 4
9
5
M5
Reference Divider M Bit 5
Reference
(PRI/SEC) Divider
M
10
6
M6
11
7
M7
12
8
M8
Reference Divider M Bit 8
13
9
M9
Reference Divider M Bit 9
14
10
M10
Reference Divider M Bit 10
15
11
M11
Reference Divider M Bit 11
16
12
M12
Reference Divider M Bit 12
17
13
M13
Reference Divider M Bit 13
18
14
N0
VCXO Divider N Bit 0
19
15
N1
VCXO Divider N Bit 1
20
16
N2
VCXO Divider N Bit 2
21
17
N3
VCXO Divider N Bit 3
22
18
N4
VCXO Divider N Bit 4
23
19
N5
VCXO Divider N Bit 5
24
20
N6
25
21
N7
26
22
N8
VCXO Divider N Bit 8
27
23
N9
VCXO Divider N Bit 9
28
24
N10
VCXO Divider N Bit 10
29
25
N11
VCXO Divider N Bit 11
30
26
N12
VCXO Divider N Bit 12
31
27
N13
VCXO Divider N Bit 13
VCXO/AUX/SEC
Divider N
Reference Divider M Bit 6
Reference Divider M Bit 7
VCXO Divider N Bit 6
VCXO Divider N Bit 7
EEPROM
EEPROM
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Register 11: SPI Mode
SPI
BIT
(1)
RAM
BIT
RELATED
BLOCK
BIT NAME
POWER UP
CONDITION
DESCRIPTION/FUNCTION
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
4
0
PRI_DIV2
5
1
SEC_DIV2
1
Input Buffers
If set to 1 enables Primary Reference Divide by 2
EEPROM
Input Buffers
If set to 1 enables Secondary Reference Divide by 2
EEPROM
When set to 0, FB divider is active
When set to 1, FB divider is disabled
EEPROM
When set to 0, FB clock is CMOS type (1)
When set to 1, FB clock is CML type and uses CML2CMOS converter in PLL
EEPROM
When set to 0, Input clock for FB not inverted (normal mode, low speed)
When set to 1, Input clock for FB inverted (higher speed mode)
EEPROM
6
2
FB_DIS
FB Path Integer
Counter 32
7
3
FB_CML_SEL
FB Path Integer
Counter 32
8
4
FB_INCLK_INV
9
5
FB_COUNT32_0
Feedback Counter Bit0
10
6
FB_COUNT32_1
Feedback Counter Bit1
11
7
FB_COUNT32_2
12
8
FB_COUNT32_3
13
9
FB_COUNT32_4
Feedback Counter Bit4
14
10
FB_COUNT32_5
Feedback Counter Bit5
15
11
FB_COUNT32_6
Feedback Counter Bit6
16
12
FB_PHASE0
Feedback Phase Adjust Bit0
17
13
FB_PHASE1
Feedback Phase Adjust Bit1
18
14
FB_PHASE2
19
15
FB_PHASE3
20
16
FB_PHASE4
Feedback Phase Adjust Bit4
21
17
FB_PHASE5
Feedback Phase Adjust Bit5
22
18
FB_PHASE6
Feedback Phase Adjust Bit6
23
19
PD_PLL
24
20
FB_MUX_SEL
See Table 6
25
21
OUT_MUX_SEL
See Table 6
26
22
FB_SEL
27
23
NRESHAPE1
FB-Divider/
Deterministic
Blocks
Feedback Counter Bit2
FB Path Integer
Counter 32
Feedback Counter Bit3
EEPROM
Feedback Phase Adjust Bit2
FB Path Integer
Counter 32
Feedback Phase Adjust Bit3
EEPROM
If set to 0, PLL is in normal mode
If set to 1, PLL is powered down
EEPROM
When set to 0, the VCXO Clock is selected for the Clock Tree and FB-Div and
Det
When set to 1, the AUX Clock is selected for the Clock Tree and FB-Div and
Det
EEPROM
Clock Tree
If Set to 0 it selects the VCXO Clock and if Set to 1 it selects the AUX Clock
EEPROM
Diagnostics
Feed Back Path Selects FB/VCXO-Path when set to 0 (TI Test-GTME)
The Secondary Reference clock input is selected when set to 1 (TI Test-GTME)
EEPROM
Reshapes the Reference Clock Signal 0, Disable Reshape 1
EEPROM
If set to 0 it enables short delay for fast operation
If Set to 1 Long Delay recommended for Input References below 150Mhz
EEPROM
If set to 1 the RESET or HOLD pin acts as HOLD, set to 0 it acts as RESET
EEPROM
PLL
Clock Tree and
Deterministic
Block
Reference
Selection Control
28
24
SEL_DEL1
29
25
RESET_HOLD
30
26
EPLOCK
Status
Read only. If EPLOCK reads a 0, the EEPROM is unlocked. If EPLOCK reads a
1, then the EEPROM is locked.
EEPROM
31
27
EPSTATUS
Status
EEPROM Status
EEPROM
Reset Circuitry
When Feedback Divider clock is set to CMOS type, only feedback divider values greater than 5 are available.
Table 6. Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT 9 Selection
32
FB_MUX_SEL
OUT_MUX_SEL
0
0
VCXO::PLL, VCXO::Y0…Y9 and Deterministic Block
PLL FEED AND OUTPUTS FEED
OUTPUT 9 is enabled
1
0
AUXIN::PLL, VCXO::Y0…Y8 and Deterministic Block
AUX IN is enabled
0
1
VCXO::PLL, AUXIN::Y0…Y8 and Deterministic Block
AUX IN is enabled
1
1
AUXIN::PLL, AUXIN::Y0…Y8 and Deterministic Block
AUX IN is enabled
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CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
Register 12: SPI Mode (RAM only Register)
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
POR
DEFAULT
DESCRIPTION/FUNCTION
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
1
3
A3
Address 3
1
4
0
RESERVED
RAM
5
1
RESERVED
RAM
6
2
RESERVED
RAM
7
3
RESERVED
RAM
8
4
INDET_AUX
Status
(Read Only)
9
5
INDET_VCXO
Status
(Read Only)
It indicates that a clock is present at VCXO-input , when set to 1
RAM
10
6
PLL_LOCK
Status
(Read Only)
It indicates that the PLL is locked when set to 1
RAM
11
7
PD
Power Down
Power-down mode on when set to 0, Off when set to 1
1
RAM
Reset
If set to 0 this bit forces “RESET or HOLD” depending on the setting of
RESET_HOLD bit in Register 11. If set to 0 RESET or HOLD are asserted.
Set for 1 for normal operation.
1
RAM
Diagnostics
General Test Mode Enable, Test Mode is only enabled, if this bit is set to 1
This bit controls many test modes on the device.
0
RAM
It indicates that a clock is present at AUX-input (Y9) , when set to 1
RAM
12
8
RESET or
HOLD
13
9
GTME
14
10
REVISION0
Status
Read only: Revision Control Bit 0
RAM
15
11
REVISION1
Status
Read only: Revision Control Bit 1
RAM
16
12
REVISION2
Status
Read only: Revision Control Bit 2
RAM
17
13
PD_IO
Diagnostics
When set to 0, all blocks are on. (TI Test-GTME)
When set to 1, the VCXO Input, AUX Input and all output buffers and divider
blocks are disabled. This test is done to measure the effect of the I/O circuitry
on the Charge Pump. (TI Test-GTME)
18
14
SXOIREF
Diagnostics
If set to 0 that Status pin is used as CMOS output to enable TI test modes.
Set to 1 when IREFRES is set to 1 and 12-KΩ resistor is connected. (TI
Test-GTME)
0
RAM
19
15
SHOLD
Diagnostics
Routes the HOLD signal to the PLL_LOCK pin when set to 1 (TI Test-GTME)
0
RAM
20
16
RESERVED
0
RAM
21
17
STATUS0
22
18
STATUS1
23
19
STATUS2
24
20
STATUS3
25
21
26
22
27
0
RAM
Diagnostics
TI test registers. For TI use only
Route internal signals to external STATUS pin.
STATUS3, STATUS2, STATUS1, STATUS0 (S3, S2, S1, S0) will select that
internal status signal that will be routed to the external STATUS pin.
1
RAM
TITSTCFG0
Diagnostics
TI test registers. For TI use only
0
RAM
TITSTCFG1
Diagnostics
TI test registers. For TI use only
0
RAM
23
TITSTCFG2
Diagnostics
TI test registers. For TI use only
0
RAM
28
24
TITSTCFG3
Diagnostics
TI test registers. For TI use only
0
RAM
29
25
PRIACTIVITY
Status
It indicates activity on the Primary when set to - (read only bit)
RAM
30
26
SECACTIVITY
Status
It indicates activity on the Secondary when set to - (read only bit)
RAM
31
27
RESERVED
RAM
NOTE:
If TI test bits (Register 12< RAM bits 17,18,19, 20> are set to 1000, Reference Select
from the Smart Mux will show on the STATUS pin ( High = Primary REF is selected
and Low = Secondary REF is selected).
When TI test bits are set to 0000 the Reference Clock Frequency Detector shows up
on the STATUS pin. In this mode the STATUS pin goes high if a clock is detected and
low if a clock is not detected. In this configuration Register 3 Bit 0 should be set to 0.
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OUTPUT DIVIDERS SETTINGS
The CDCE72010 has a complex multi stage output divider. The table below describes the setting of Bits 13:19 of
Register 1 to 8 and the setting for the feedback divider bits 5:11 of register 11. The table below describes divider
settings and the phase relation of the outputs with respect to divide by one clock. To calculate the phase relation
between 2 different dividers see Output Divider and Phase Adjust Section in this document.
Table 7. Output Dividers and Feedback Divide Settings and Phase Output
FOR REGISTER 1 TO 8 RAM BITS {19[BIT6] TO
13[BIT0]}
FOR REGISTER 11 RAM BITS {11[BIT6] TO 5[BIT0]}
DIVIDE BY
TOTAL
PHASE LAG FROM DIVIDE BY 1
[Bit 6]
[Bit 5]
[Bit 4]
[Bit 3]
[Bit 2]
[Bit 1]
[Bit 0]
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
2
0.5
180
1
0
0
0
0
0
1
3
0
0
1
0
0
0
0
1
0
4
0.5
180
1
0
0
0
0
1
1
5
0
0
0
0
0
0
0
0
0
4'
14.5
5220
0
0
0
0
0
0
1
6
21
7560
0
0
0
0
0
1
0
8
28.5
10260
0
0
0
0
0
1
1
10
35
12600
0
0
0
0
1
0
0
8'
16.5
5940
0
0
0
0
1
0
1
12
24
8640
0
0
0
0
1
1
0
16
32.5
11700
0
0
0
0
1
1
1
20
40
14400
0
0
0
1
0
0
0
12'
18.5
6660
0
0
0
1
0
0
1
18
27
9720
0
0
0
1
0
1
0
24
36.5
13140
0
0
0
1
0
1
1
30
45
16200
0
0
0
1
1
0
0
16'
20.5
7380
0
0
0
1
1
0
1
24'
30
10800
0
0
0
1
1
1
0
32
40.5
14580
0
0
0
1
1
1
1
40
50
18000
0
0
1
0
0
0
0
20'
22.5
8100
0
0
1
0
0
0
1
30'
33
11880
0
0
1
0
0
1
0
40'
44.5
16020
0
0
1
0
0
1
1
50
55
19800
0
0
1
0
1
0
0
24'
24.5
8820
0
0
1
0
1
0
1
36
36
12960
0
0
1
0
1
1
0
48
48.5
17460
0
0
1
0
1
1
1
60
60
21600
0
0
1
1
0
0
0
28
26.5
9540
0
0
1
1
0
0
1
42
39
14040
0
0
1
1
0
1
0
56
52.5
18900
0
0
1
1
0
1
1
70
65
23400
0
0
1
1
1
0
0
32'
28.5
10260
0
0
1
1
1
0
1
48'
42
15120
0
0
1
1
1
1
0
64
56.5
20340
0
0
1
1
1
1
1
80
70
25200
34
Cycle
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Degree
Copyright © 2008–2009, Texas Instruments Incorporated
Product Folder Link(s): CDCE72010
CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
CONFIGURATION DEFAULT MODE
The CDCE72010 has two modes of operation, SPI Interface and Configuration Default Mode. The Configuration
Default mode is selected when MODE_SELECT Pin is driven low and it is used where SPI interface is not
available. In the CD Mode configuration, the SPI interface Pins become static control pins CD1, CD2, CD3 and
AUX_SEL as shown in the Pin description. The CD Mode signals are sampled only at power up or after Power
Down are asserted.
In CD Mode BYPASS, CD1 and CD2 are used to switch between EEPROM saved configurations. -CD1 allows
swapping Divider and Phase Adjust value between output couples.
• CD2 allows changing the output type for each output.
• AUX_SEL Controls the Output Mux between VCXO and AUX Input.
• CD3 must be grounded in CD Mode.
Without any interface a single device with a single program can have multiple configurations that can be
implemented on more than one socket.
RAM Resistors
PLL_LOCK
REF_SEL
POWER DOWN
RESET or HOLD
MODE_SEL
AUX_SEL
Interface
& Control
EEPROM
RAM Resistors
PLL_LOCK
REF_SEL
POWER DOWN
RESET or HOLD
MODE_SEL
AUX_SEL
SPI_MISO
SPI_LE (CD1)
SPI_CLK (CD2)
SPI_MOSI (CD3)
Interface
& Control
EEPROM
CD1
CD2
CD3
Figure 13. Writing to EEPROM via SPI Bus in
Manufacutring,
3rd Party Vendor or at TI Test
Figure 14. Using CD1, CD2 to Control What is Copied
From EEPROM Into RAM Registers at Power Up
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CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
Register 0: CD Mode
SPI
BIT
(1)
36
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
0
4
0
INBUFSELX
5
1
INBUFSELY
6
2
PRISEL
7
3
SECSEL
8
4
VCXOSEL
Reference Input
Buffers
Primary and Secondary Buffer Type Select (LVPECL,LVDS or LVCMOS)
XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin
EEPROM
Reference Input
Buffer
When REFSELCNTRL is set to 1 the following settings apply:
If RAM Bit (2,3): 00 – no Input Buffer is selected/active
If RAM Bit (2,3): 10 – PRI_BUF is selected, SEC_BUF is powered down
If RAM Bit (2,3): 01 – SEC_BUF is selected, PRI_BUF is powered down (1)
If RAM Bit (2,3): 11 – Auto Select (PRI then SEC).
EEPROM
Divider START
DETERM-Block
When set to 0, PRI- or SEC-Clocks are selected, depending on Bits 2 and 3
(default)
When set to 1, VCXO/AUX-clock selected, overwrites Bits 2 and 3
EEPROM
Reference Select Control to select if the control of the reference is from the
internal bit in Register 0 RAM bits 2 and 3 or from the external select pin.
- When set to 0: The external pin REF_SEL takes over the selection between
PRI and SEC. Autoselect is not available.
- When set to 1: The external pin REF_SEL is ignored. The Table in (Register 0
<2 and 3> ) describes, which reference input clock is selected and available at
(none, PRI, SEC or Autoselect). In autoselect mode, refer to the timing diagram
EEPROM
Reference
Selection Control
9
5
REFSELCNTRL
10
6
DELAY_PFD0
PFD
PFD Pulse Width PFD Bit 0
EEPROM
11
7
DELAY_PFD1
PFD
PFD Pulse Width PFD Bit 1
EEPROM
12
8
CP_MODE
Selects 3V option [0] or 5V option [1]
EEPROM
Determines in which direction CP current will regulate (Reference Clock leads to
Feedback Clock; Positive CP output current [0]; Negative CP output current [1]
EEPROM
Switches the current source in the Charge Pump on when set to 1 (TI
Test-GTME)
EEPROM
13
9
CP_DIR
14
10
CP_SRC
Charge Pump
Diagnostics
15
11
CP_SNK
Switches the current sink in the Charge Pump on when set to 1 (TI Test-GTME)
EEPROM
16
12
CP_OPA
Switches the Charge Pump op-amp off when set to 1 (TI Test-GTME)
EEPROM
17
13
CP_PRE
Preset Charge Pump output voltage to VCC_CP/2, on [1], off [0]
EEPROM
18
14
ICP0
CP Current Setting Bit 0
EEPROM
19
15
ICP1
CP Current Setting Bit 1
EEPROM
20
16
ICP2
CP Current Setting Bit 2
EEPROM
21
17
ICP3
CP Current Setting Bit 3
EEPROM
22
18
RESERVED
23
19
RESERVED
Charge Pump
EEPROM
EEPROM
Diagnostics
Enables the 12k pull-down resistor at I_REF_CP Pin when set to 1 (TI
Test-GTME)
EEPROM
High output voltage swing in LVPECL Mode if set to 1
EEPROM
24
20
IREFRES
25
21
PECL0HISWING
26
22
RESERVED
EEPROM
27
23
RESERVED
EEPROM
28
24
OUTBUF0CD2LX
29
25
OUTBUF0CD2LY
30
26
OUTBUF0CD2HX
31
27
OUTBUF0CD2HY
Output 0
CD2 Low
Output Buffer 0 Signaling Selection when CD2 In low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
CD2 High
Output Buffer 0 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: output disable
EEPROM
This setting is only avaiable if the Register 11 Bit 2 is set to 0 (Feedback Divider clock is set to CMOS type).
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Product Folder Link(s): CDCE72010
CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
Register 1: CD Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
1
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
0
4
0
ACDCSEL
Input Buffers
If Set to 0 AC Termination, If set to 1 DC termination
EEPROM
5
1
HYSTEN
Input Buffers
If Set to 1 Input Buffers Hysteresis enabled
EEPROM
6
2
TERMSEL
Input Buffers
If Set to 0 Input Buffer Internal Termination enabled
EEPROM
7
3
PRIINVBB
Input Buffers
If Set to 1 Primary Input Negative Pin biased with internal VBB voltage.
EEPROM
8
4
SECINVBB
Input Buffers
If Set to 1 Secondary Input Negative Pin biased with internal VBB voltage
EEPROM
9
5
FAILSAFE
Input Buffers
If Set to 1 Fail Safe is enabled for all input buffers.
EEPROM
10
6
PH1ADJC0
11
7
PH1ADJC1
12
8
PH1ADJC2
13
9
PH1ADJC3
Output 0 and 1
Coarse phase adjust select for output divider 1
EEPROM
14
10
PH1ADJC4
15
11
PH1ADJC5
16
12
PH1ADJC6
17
13
OUT1DIVRSEL0
18
14
OUT1DIVRSEL1
19
15
OUT1DIVRSEL2
20
16
OUT1DIVRSEL3
Output 0 and 1
OUTPUT DIVIDER 1 Ratio Select
(See Table 7)
EEPROM
21
17
OUT1DIVRSEL4
22
18
OUT1DIVRSEL5
23
19
OUT1DIVRSEL6
24
20
EN01DIV
Output 0 and 1
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
25
21
PECL1HISWING
Output 1
High output voltage swing in LVPECL Mode if set to 1
EEPROM
EEPROM
EEPROM
26
22
DIVPHA1CD1H
CD1 High
CD1 PIN is high and DIVPHA1CD1H is set to low
Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 1
CD1 PIN is high and DIVPHA1CD1H is set to high
Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 1
27
23
DIVPHA1CD1L
CD1 Low
CD1 PIN is low and DIVPHA1CD1L is set to low
Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 1
CD1 PIN is low and DIVPHA1CD1L is set to high
Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 1
28
24
OUTBUF1CD2LX
25
OUTBUF1CD2LY
CD2 Low
Output Buffer 1 Signaling Selection when CD2 in low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
29
30
26
OUTBUF1CD2HX
27
OUTBUF1CD2HY
CD2 High
Output Buffer 1 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
31
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CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
Register 2: CD Mode
SPI
BIT
38
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
0
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
0
Reference Phase Delay M Bit0
4
0
DLYM0
5
1
DLYM1
6
2
DLYM2
7
3
DLYN0
8
4
DLYN1
9
5
DLYN2
10
6
PH2ADJC0
11
7
PH2ADJC1
12
8
PH2ADJC2
13
9
PH2ADJC3
14
10
PH2ADJC4
15
11
PH2ADJC5
16
12
PH2ADJC6
17
13
OUT2DIVRSEL0
18
14
OUT2DIVRSEL1
19
15
OUT2DIVRSEL2
20
16
OUT2DIVRSEL3
21
17
OUT2DIVRSEL4
22
18
OUT2DIVRSEL5
23
19
OUT2DIVRSEL6
24
20
25
21
DELAY M
Reference Phase Delay M Bit1
EEPROM
Reference Phase Delay M Bit2
Feedback Phase Delay N Bit0
DELAY N
Feedback Phase Delay N Bit1
EEPROM
Feedback Phase Delay N Bit2
Output 2
Coarse phase adjust select for output divider 2
EEPROM
Output 2
OUTPUT DIVIDER 2 Ratio Select
(See Table 7)
EEPROM
EN2DIV
Output 2
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
PECL2HISWING
Output 2
High output voltage swing in LVPECL Mode if set to 1
EEPROM
EEPROM
26
22
DIVPHA2CD1H
CD1 High
CD1 PIN is high and DIVPHA2CD1H is set to low
Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 2
CD1 PIN is high and DIVPHA2CD1H is set to high
Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 2
27
23
DIVPHA2CD1L
CD1 Low
CD1 PIN is low and DIVPHA2CD1L is set to low
Loads Output Divider 2 and Phase Adjust 2 into OUTPUT 2
CD1 PIN is low and DIVPHA2CD1L is set to high
Loads Output Divider 1 and Phase Adjust 1 into OUTPUT 2
EEPROM
28
24
OUTBUF2CD2LX
29
25
OUTBUF2CD2LY
CD2 Low
Output Buffer 2 Signaling Selection when CD2 in low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
30
26
OUTBUF2CD2HX
31
27
OUTBUF2CD2HY
CD2 High
Output Buffer 2 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
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Product Folder Link(s): CDCE72010
CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
Register 3: CD Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
0
When set to 0, the REF-clock frequency detector is ON
When set to 1, it is switched OFF
EEPROM
When set to 1, the feedback path frequency detector is switched OFF
(TI Test-GTME)
EEPROM
4
0
DIS_FDET_REF
5
1
DIS_FDET_FB
6
2
BIAS_DIV01<0>
7
3
BIAS_DIV01<1>
8
4
BIAS_DIV23<0>
PLL Freq. Detect
Diagnostics
When BIAS_DIV01<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
Output Divider
0 and 1
When BIAS_DIV23<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
Output Divider
2 and 3
Output 3
Coarse phase adjust select for output divider 3
EEPROM
Output 3
OUTPUT DIVIDER 3 Ratio Select
(See Table 7)
EEPROM
EEPROM
9
5
BIAS_DIV23<1>
EEPROM
10
6
PH3ADJC0
11
7
PH3ADJC1
12
8
PH3ADJC2
13
9
PH3ADJC3
14
10
PH3ADJC4
15
11
PH3ADJC5
16
12
PH3ADJC6
17
13
OUT3DIVRSEL0
18
14
OUT3DIVRSEL1
19
15
OUT3DIVRSEL2
20
16
OUT3DIVRSEL3
21
17
OUT3DIVRSEL4
22
18
OUT3DIVRSEL5
23
19
OUT3DIVRSEL6
24
20
EN3DIV
Output 3
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
25
21
PECL3HISWING
Output 3
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
EEPROM
26
22
DIVPHA3CD1H
CD1 High
CD1 PIN is high and DIVPHA3CD1H is set to low
Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 3
CD1 PIN is high and DIVPHA3CD1H is set to high
Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 3
27
23
DIVPHA3CD1L
CD1 Low
CD1 PIN is Low and DIVPHA3CD1L is set to low
Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 3
CD1 PIN is Low and DIVPHA3CD1L is set to high
Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 3
EEPROM
28
24
OUTBUF3CD2LX
29
25
OUTBUF3CD2LY
CD2 Low
Output Buffer 3 Signaling Selection when CD2 in low
(X,Y) = 01:LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
30
26
OUTBUF3CD2HX
31
27
OUTBUF3CD2HY
CD2 High
Output Buffer 3 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
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Register 4: CD Mode
SPI
BIT
40
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
1
3
A3
Address 3
0
4
0
RESERVED
EEPROM
5
1
RESERVED
EEPROM
6
2
RESERVED
EEPROM
7
3
RESERVED
8
4
HOLDONLOR
9
5
RESERVED
10
6
PH4ADJC0
11
7
PH4ADJC1
12
8
PH4ADJC2
13
9
PH4ADJC3
14
10
PH4ADJC4
15
11
PH4ADJC5
16
12
PH4ADJC6
17
13
OUT4DIVRSEL0
18
14
OUT4DIVRSEL1
19
15
OUT4DIVRSEL2
20
16
OUT4DIVRSEL3
21
17
OUT4DIVRSEL4
22
18
OUT4DIVRSEL5
23
19
OUT4DIVRSEL6
24
20
25
21
EEPROM
HOLD- Over
If set to 1 it will 3-state the charge pump to act as a HOLD on Loss of Reference
Clocks ( Primary and Secondary)
EEPROM
EEPROM
Output 4
Coarse phase adjust select for output divider 4
EEPROM
Output 4
OUTPUT DIVIDER 4 Ratio Select
(See Table 7)
EEPROM
EN4DIV
Output 4
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
PECL4HISWING
Output 4
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
EEPROM
26
22
DIVPHA4CD1H
CD1 High
CD1 PIN is high and DIVPHA4CD1H is set to low
Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 4
CD1 PIN is high and DIVPHA4CD1H is set to high
Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 4
27
23
DIVPHA4CD1L
CD1 Low
CD1 PIN is low and DIVPHA4CD1L is set to low
Loads Output Divider 4 and Phase Adjust 4 into OUTPUT 4
CD1 PIN is low and DIVPHA4CD1L is set to high
Loads Output Divider 3 and Phase Adjust 3 into OUTPUT 4
EEPROM
28
24
OUTBUF4CD2LX
29
25
OUTBUF4CD2LY
CD2 Low
Output Buffer 4 Signaling Selection when CD2 in low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
30
26
OUTBUF4CD2HX
31
27
OUTBUF4CD2HY
CD2 High
Output Buffer 4 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
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Product Folder Link(s): CDCE72010
CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
Register 5: CD Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
1
1
A1
Address 1
0
2
A2
Address 2
1
3
A3
Address 3
0
Output Divider
4 and 5
When BIAS_DIV45<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
Output Divider
6 and 7
When BIAS_DIV67<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
4
0
BIAS_DIV45<0>
5
1
BIAS_DIV45<1>
6
2
BIAS_DIV67<0>
7
3
BIAS_DIV67<1>
8
4
RESERVED
EEPROM
9
5
RESERVED
EEPROM
10
6
PH5ADJC0
11
7
PH5ADJC1
12
8
PH5ADJC2
13
9
PH5ADJC3
14
10
PH5ADJC4
15
11
PH5ADJC5
16
12
PH5ADJC6
17
13
OUT5DIVRSEL0
18
14
OUT5DIVRSEL1
19
15
OUT5DIVRSEL2
20
16
OUT5DIVRSEL3
21
17
OUT5DIVRSEL4
22
18
OUT5DIVRSEL5
23
19
OUT5DIVRSEL6
24
20
25
21
Output 5
Coarse phase adjust select for output divider 5
EEPROM
Output 5
OUTPUT DIVIDER 5 Ratio Select
(See Table 7)
EEPROM
EN5DIV
Output 5
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
PECL5HISWING
Output 5
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
EEPROM
26
22
DIVPHA5CD1H
CD1 High
CD1 PIN is high and DIVPHA5CD1H is set to low
Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 5
CD1 PIN is high and DIVPHA5CD1H is set to high
Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 5
27
23
DIVPHA5CD1L
CD1 Low
CD1 PIN is low and DIVPHA5CD1L is set to low
Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 5
CD1 PIN is low and DIVPHA5CD1L is set to high
Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 5
EEPROM
28
24
OUTBUF5CD2LX
29
25
OUTBUF5CD2LY
CD2 Low
Output Buffer 5 Signaling Selection when CD2 in low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
30
26
OUTBUF5CD2HX
31
27
OUTBUF5CD2HY
CD2 High
Output Buffer 5 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
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41
CDCE72010
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Register 6: CD Mode
SPI
BIT
42
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
0
1
A1
Address 1
1
2
A2
Address 2
1
3
A3
Address 3
0
0 Feedback Frequency Detector is connected to the Lock Detector
1 Feedback Frequency Detector is disconnected from the Lock Detector
4
0
FB_FD_DESEL
5
1
RESERVED
Set to “0”
6
2
FBDETERM_DIV_SEL
0 FB-Deterministic Clock divided by 1
1 FB- Deterministic Clock divided by 2
7
3
FBDETERM_DIV2_DIS
8
4
FB_START_BYPASS
9
5
DET_START_BYPASS
10
6
PH6ADJC0
11
7
PH6ADJC1
12
8
PH6ADJC2
13
9
PH6ADJC3
14
10
PH6ADJC4
15
11
PH6ADJC5
16
12
PH6ADJC6
17
13
OUT6DIVRSEL0
18
14
OUT6DIVRSEL1
19
15
OUT6DIVRSEL2
20
16
OUT6DIVRSEL3
21
17
OUT6DIVRSEL4
22
18
OUT6DIVRSEL5
23
19
OUT6DIVRSEL6
24
20
25
21
LOCK-DET
FB-Divider /
Deterministic
Blocks
0 FB-Deterministic-DIV2-Block in normal operation
1 FB-Deterministic-DIV2 reset (here REG6_RB<2> == “0”)
EEPROM
EEPROM
0 FB-Divider started with delay block (RC), normal operation
1 FB-Divider can be started with external REF_SEL-signal (pin)
All Output
Dividers
0 Output-Dividers started with delay block (RC), normal operation
1 Output-Dividers can be started with external NRESET-signal (pin)
EEPROM
Output 6
Coarse phase adjust select for output divider 6
EEPROM
Output 6
OUTPUT DIVIDER 6 Ratio Select
(See Table 7)
EEPROM
EN6DIV
Output 6
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
PECL6HISWING
Output 6
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
EEPROM
26
22
DIVPHA6CD1H
CD1 High
CD1 PIN is high and DIVPHA6CD1H is set to low
Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 6
CD1 PIN is high and DIVPHA6CD1H is set to high
Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 6
27
23
DIVPHA6CD1L
CD1 Low
CD1 PIN is low and DIVPHA6CD1L is set to low
Loads Output Divider 6 and Phase Adjust 6 into OUTPUT 6
CD1 PIN is low and DIVPHA6CD1L is set to high
Loads Output Divider 5 and Phase Adjust 5 into OUTPUT 6
EEPROM
28
24
OUTBUF6CD2LX
29
25
OUTBUF6CD2LY
CD2 Low
Output Buffer 6 Signaling Selection when CD2 in low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
30
26
OUTBUF6CD2HX
31
27
OUTBUF6CD2HY
CD2 High
Output Buffer 6 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
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Register 7: CD Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
1
3
A3
Address 3
0
4
0
LOCKW 0
Lock-detect window bit 0 (Refer to Reg 9 RAM Bits 6 and 7)
5
1
LOCKW 1
Lock-detect window bit 1 (Refer to Reg 9 RAM Bits 6 and 7)
6
2
RESERVED
7
3
LOCKC0
8
4
LOCKC1
Number of coherent lock events bit 1
9
5
ADLOCK
Selects Digital PLL_LOCK 0 ,Selects Analog PLL_LOCK 1
10
6
PH7ADJC0
11
7
PH7ADJC1
12
8
PH7ADJC2
13
9
PH7ADJC3
14
10
PH7ADJC4
15
11
PH7ADJC5
16
12
PH7ADJC6
17
13
OUT7DIVRSEL0
18
14
OUT7DIVRSEL1
19
15
OUT7DIVRSEL2
20
16
OUT7DIVRSEL3
21
17
OUT7DIVRSEL4
22
18
OUT7DIVRSEL5
23
19
OUT7DIVRSEL6
24
20
25
21
LOCK-DET
Set to 0
EEPROM
Number of coherent lock events bit 0
Output 7
Coarse phase adjust select for output divider 7
EEPROM
Output 7
OUTPUT DIVIDER 7 Ratio Select
(See Table 7)
EEPROM
EN7DIV
Output 7
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
PECL7HISWING
Output 7
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
EEPROM
26
22
DIVPHA7CD1H
CD1 High
CD1 PIN is high and DIVPHA7CD1H is set to low
Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 7
CD1 PIN is high and DIVPHA7CD1H is set to high
Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 7
27
23
DIVPHA7CD1L
CD1 Low
CD1 PIN is low and DIVPHA7CD1L is set to low
Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 7
CD1 PIN is low and DIVPHA7CD1L is set to high
Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 7
EEPROM
28
24
OUTBUF7CD2LX
29
25
OUTBUF7CD2LY
CD2 Low
Output Buffer 7 Signaling Selection when CD2 in low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
30
26
OUTBUF7CD2HX
31
27
OUTBUF7CD2HY
CD2 High
Output Buffer 7 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
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Register 8: CD Mode
SPI
BIT
44
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
0
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
1
VCXO and AUX Input Buffer Type Select (LVPECL,LVDS or LVCMOS)
4
0
VCXOBUFSELX
5
1
VCXOBUFSELY
6
2
VCXOACDCSEL
7
3
VCXOHYSTEN
8
4
VCXOTERMSEL
9
5
VCXOINVBB
10
6
PH8ADJC0
11
7
PH8ADJC1
12
8
PH8ADJC2
13
9
PH8ADJC3
14
10
PH8ADJC4
15
11
PH8ADJC5
16
12
PH8ADJC6
17
13
OUT8DIVRSEL0
18
14
OUT8DIVRSEL1
19
15
OUT8DIVRSEL2
20
16
OUT8DIVRSEL3
21
17
OUT8DIVRSEL4
22
18
OUT8DIVRSEL5
23
19
OUT8DIVRSEL6
24
20
EN89DIV
25
21
PECL8HISWING
XY(10) LVPECL, (11) LVDS, (00) LVCMOS- Input is Positive Pin
VCXO and AUX
Input Buffers
If Set to 0 AC Termination, If set to 1 DC Termination
VCXO Input Buffer
If Set to 1 Input Buffers Hysteresis enabled
EEPROM
If Set to 0 Input Buffer Internal Termination enabled
VCXO Input Buffer If Set to 1 It biases VCXO Input negative pin with internal VCXOVBB voltage
EEPROM
Output 8 and 9
Coarse phase adjust select for output divider 8 and 9
EEPROM
Output 8 and 9
OUTPUT DIVIDER 8 and 9 Ratio Select
(See Table 7)
EEPROM
Output 8 and 9
When set to 0, the divider is disabled
When set to 1, the divider is enabled
EEPROM
Output 8
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
EEPROM
26
22
DIVPHA8CD1H
CD1 High
CD1 PIN is high and DIVPHA8CD1H is set to low
Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 8
CD1 PIN is high and DIVPHA8CD1H is set to high
Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 8
27
23
DIVPHA8CD1L
CD1 Low
CD1 PIN is low and DIVPHA8CD1L is set to low
Loads Output Divider 8 and Phase Adjust 8 into OUTPUT 8
CD1 PIN is low and DIVPHA8CD1L is set to high
Loads Output Divider 7 and Phase Adjust 7 into OUTPUT 8
EEPROM
28
24
OUTBUF8CD2LX
29
25
OUTBUF8CD2LY
CD2 Low
Output Buffer 8 Signaling Selection when CD2 in low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
30
26
OUTBUF8CD2HX
31
27
OUTBUF8CD2HY
CD2 High
Output Buffer 8 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
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Register 9: CD Mode
SPI
BIT
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
1
1
A1
Address 1
0
2
A2
Address 2
0
3
A3
Address 3
1
4
0
HOLDF1
Enables the Frequency Hold-Over Function 1 on 1, off 0
5
1
HOLDF2
Enables the Frequency Hold-Over Function 2 on 1, off 0
6
2
HOLD
3-State Charge Pump 0 - (equal to HOLD-Pin function)
7
3
HOLDTR
8
4
HOLD_CNT0
9
5
HOLD_CNT1
10
6
LOCKW 2
11
7
LOCKW 3
12
8
NOINV_RESHOL_IN
T
13
9
DIVSYNC_DIS
14
10
15
HOLD function always activated “1” (recommended for test purposes, only)
Triggered by analog PLL Lock detect outputs
If analog PLL Lock Signal is [1] (PLL locked), HOLD is activated
If analog PLL Lock Signal is [0] (PLL not lock), HOLD is deactivated
HOLD- Over
EEPROM
HOLD1 Function is reactivated after X Ref Clock Cycles. Defined by
(HOLD_CNT0,HOLD_CNT1)::X= Number of Clock Cycles.
For (00)::X=64, (01) ::X=128, (10)::X=256, (11)::X=512 Clock Cycles.
Extended Lock-detect window Bit 2 (Also refer to Reg 7 RAM Bits 0 and 1)
LOCK-DET
Extended Lock-detect window Bit 3 (Also refer to Reg 7 RAM Bits 0 and 1)
EEPROM
When set to 0, SPI/HOLD_INT and SPI/RESET_INT inverted (default)
When set to 1, SPI/HOLD_INT and SPI/RESET_INT not inverted
EEPROM
Diagnostic: PLL
N/M Divider
When GTME = 0, this bit has no functionality, But when GTME = 1, then:
When set to 0, START-Signal is synchronized to N/M Divider Input Clocks
When set to 1, START-Sync N/M Divider in PLL are bypassed
EEPROM
START_BYPASS
Divider START
DETERM-Block
When set to 0, START-Signal is synchronized to VCXO-Clock
When set to 1, START-Sync Block is bypassed
EEPROM
11
INDET_BP
Divider START
DETERM-Block
When set to 0, Sync Logic active when VCXO/AUX-Clocks are available
When set to 1, Sync Logic is independent from VCXO- and/or AUX-Clocks
EEPROM
16
12
PLL_LOCK_BP
Divider START
DETERM-Block
When set to 0, Sync Logic waits for 1st PLL_LOCK state
When set to 1, Sync Logic independent from 1st PLL_LOCK
EEPROM
17
13
LOW_FD_FB_EN
Divider START
DETERM-Block
When set to 0, Sync Logic is independent from VCXO/DIV_FB freq. (PLL-FD)
When set to 1, Sync Logic is started for VCXO/DIV_FB > ~600KHz,
stopped for VCXO/DIV_FB < ~600KHz
EEPROM
18
14
NPRESET_MDIV
PLL
M/FB-Divider
When set to 0, M-Divider uses NHOLD1 as NPRESET
When set to 1, M-Divider NOT preseted by NHOLD1
EEPROM
19
15
BIAS_DIV_FB<0>
When BIAS_DIV_FB<1:0> =
00, No current reduction for FB-Divider
01, Current reduction for FB-Divider by about 20%
10, Current reduction for FB-Divider by about 30%
EEPROM
When BIAS_DIV89<1:0> =
00, No current reduction for all output-divider
01, Current reduction for all output-divider by about 20%
10, Current reduction for all output-divider by about 30%
EEPROM
20
16
BIAS_DIV_FB<1>
21
17
BIAS_DIV89<0>
22
18
BIAS_DIV89<1>
23
19
AUXINVBB
Chip CORE
Feedback
Divider
Output Divider
8 and 9
If Set to 1 it Biases AUX Input Negative Pin with internal VCXOVBB voltage.
AUX Buffer
If Set to 1 AUX in input Mode Buffer is disabled. If Set to 0 it follows the
behavior of FB_MUX_SEL and OUT_MUX_SEL bits settings.
EEPROM
High Output Voltage Swing in LVPECL Mode if set to 1
EEPROM
24
20
DIS_AUX_Y9
25
21
PECL9HISWING
26
22
RESERVED
EEPROM
27
23
RESERVED
EEPROM
28
24
OUTBUF9CD2LX
29
25
OUTBUF9CD2LY
30
26
OUTBUF9CD2HX
31
27
OUTBUF9CD2HY
Output 9
CD2 Low
Output Buffer 9 Signaling Selection when CD2 in low
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
CD2 High
Output Buffer 9 Signaling Selection when CD2 in high
(X,Y) = 01: LVPECL, 11: LVDS, 00: LVCMOS, 10: Output Disable
EEPROM
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Register 10: CD Mode
SPI
BIT
46
RAM
BIT
BIT NAME
RELATED
BLOCK
DESCRIPTION/FUNCTION
POWER UP
CONDITION
0
A0
Address 0
0
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
1
4
0
M0
Reference Divider M bit 0
5
1
M1
Reference Divider M bit 1
6
2
M2
Reference Divider M bit 2
7
3
M3
Reference Divider M bit 3
8
4
M4
Reference Divider M bit 4
9
5
M5
Reference Divider M bit 5
Reference
(PRI/SEC)
Divider M
10
6
M6
11
7
M7
Reference Divider M bit 6
12
8
M8
Reference Divider M bit 8
13
9
M9
Reference Divider M bit 9
14
10
M10
Reference Divider M bit 10
15
11
M11
Reference Divider M bit 11
16
12
M12
Reference Divider M bit 12
17
13
M13
Reference Divider M bit 13
18
14
N0
VCXO Divider N bit 0
19
15
N1
VCXO Divider N bit 1
20
16
N2
VCXO Divider N bit 2
21
17
N3
VCXO Divider N bit 3
22
18
N4
VCXO Divider N bit 4
23
19
N5
VCXO Divider N Bit 5
24
20
N6
25
21
N7
26
22
N8
VCXO Divider N Bit 8
27
23
N9
VCXO Divider N Bit 9
28
24
N10
VCXO Divider N Bit 10
29
25
N11
VCXO Divider N Bit 11
30
26
N12
VCXO Divider N Bit 12
31
27
N13
VCXO Divider N Bit 13
Reference Divider M bit 7
VCXO/AUX/SEC
Divider N
VCXO Divider N Bit 6
VCXO Divider N Bit 7
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EEPROM
EEPROM
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CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
Register11: CD Mode
SPI
BIT
RAM
BIT
RELATED
BLOCK
BIT NAME
POWER UP
CONDITION
DESCRIPTION/FUNCTION
0
A0
Address 0
1
1
A1
Address 1
1
2
A2
Address 2
0
3
A3
Address 3
4
0
PRI_DIV2
5
1
SEC_DIV2
1
Input Buffers
If set to 1 Enables Primary Reference Divide by 2
EEPROM
Input Buffers
If set to 1 Enables Secondary Reference Divide by 2
EEPROM
When set to 0, FB divider is active
When set to 1, FB divider is disabled
EEPROM
When set to 0, FB clock is CMOS type
When set to 1, FB clock is CML type and uses CML2CMOS converter in PLL
EEPROM
When set to 0, Input clock for FB not inverted (normal mode, low speed)
When set to 1, Input clock for FB inverted (higher speed mode)
EEPROM
6
2
FB_DIS
FB Path Integer
Counter 32
7
3
FB_CML_SEL
FB Path Integer
Counter 32
8
4
FB_INCLK_INV
9
5
FB_COUNT32_0
Feedback Counter Bit0
10
6
FB_COUNT32_1
Feedback Counter Bit1
11
7
FB_COUNT32_2
12
8
FB_COUNT32_3
13
9
FB_COUNT32_4
14
10
FB_COUNT32_5
Feedback Counter Bit5
15
11
FB_COUNT32_6
Feedback Counter Bit6
16
12
FB_PHASE0
Feedback Phase Adjust Bit0
17
13
FB_PHASE1
Feedback Phase Adjust Bit1
18
14
FB_PHASE2
19
15
FB_PHASE3
20
16
FB_PHASE4
21
17
FB_PHASE5
Feedback Phase Adjust Bit5
22
18
FB_PHASE6
Feedback Phase Adjust Bit6
23
19
PD_PLL
24
20
FB_MUX_SEL
Table 8
25
21
OUT_MUX_SEL
Table 8
26
22
FB_SEL
27
23
NRESHAPE1
28
24
SEL_DEL1
29
25
RESET_HOLD
30
26
EPLOCK
31
27
EPSTATUS
FB-Divider /
Deterministic
Blocks
FB Path Integer
Counter 32
(P divider)
FB Path Integer
Counter 32
(P Divider)
PLL
Clock Tree and
Deterministic
Block
Diagnostics
Reference
Selection Control
Feedback Counter Bit2
Feedback Counter Bit3
EEPROM
Feedback Counter Bit4
Feedback Phase Adjust Bit2
Feedback Phase Adjust Bit3
EEPROM
Feedback Phase Adjust Bit4
If set to 0, PLL is in normal mode
If set to 1, PLL is powered down
EEPROM
When set to 0, the VCXO Clock is selected for the Clock Tree and FB-Div/Det
When set to 1, the AUX Clock is selected for the Clock Tree and FB-Div/Det.
EEPROM
If Set to 0 it selects the VCXO Clock and if Set to 1 it selects the AUX Clock
EEPROM
Feed Back Path Selects FB/VCXO-Path when set to 0 (TI Test-GTME)
The Secondary Reference clock input is selected when set to 1 (TI Test-GTME)
EEPROM
Reshapes the Reference Clock Signal 0, Disable Reshape 1
If set to 0 it enables short delay for fast operation
If Set to 1 Long Delay recommended for input references below 150Mhz.
EEPROM
If set to 1 the RESET or HOLD pin acts as HOLD, set to 0 it acts as RESET.
EEPROM
Status
Read only. If EPLOCK reads a 0, the EEPROM is unlocked. If EPLOCK reads a
1, then the EEPROM is locked.
EEPROM
Status
EEPROM Status
EEPROM
Reset Circuitry
Table 8. Output Buffers Source Feed, PLL Source Feed, and AUX IN/OUTPUT 9 Selection
(1)
FB_MUX_SEL
OUT_MUX_SEL
0
0
VCXO::PLL, VCXO::Y0…Y9 and Deterministic Block
PLL FEED AND OUTPUT FEED
OUTPUT 9 is Enabled (1)
AUX INPUT OR OUTPUT 9
1
0
AUXIN::PLL, VCXO::Y0…Y8 and Deterministic Block
AUX IN is Enabled
0
1
VCXO::PLL, AUXIN::Y0…Y8 and Deterministic Block
AUX IN is Enabled
1
1
AUXIN::PLL, AUXIN::Y0…Y8 and Deterministic Block
AUX IN is Enabled
Default
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INTERFACE, CONFIGURATION, AND CONTROL
The CDCE72010 is designed to support various applications with SPI bus interface and without. In the case
where systems lack the SPI bus or a Boot up configuration is required at start up before the management layer is
up the built in EEPROM is used to provide this function.
The Interface bus takes the serialized address and data and writes to the specified RAM bits. The content of the
RAM bits are connected to logical functions in the device. Changing the content of the RAM bits (high or low)
instantly changes the logical functions inside the device.
At power up or after power down is de-asserted the contents of the EEPROM bits are copied to their
corresponding RAM bits. After that the content of RAM can be changed via the SPI bus. When writing to
EEPROM commands are detected on the SPI bus the control logic begins writing the content of the RAM bits
into the corresponding EEPROM bits. This process takes about 50ms. During this time the power supply should
be above 3.2V.
The on-chip EEPROM can be operated in its unlocked or locked mode. An unlocked EEPROM indicates that the
stored bit values can be changed on another EEPROM write sequence (available for up to a 100 EEPROM write
sequences). A locked EEPROM indicates that the stored bit values cannot be changed on another EEPROM
write sequence.
Control Signals
RAM Registers
SPI
Interface & Control
EEPROM Cells
Figure 15. Interface Control
UNIVERSAL INPUT AND REFERENCE CLOCK BUFFERS
The CDCE72010 is designed to support what is referred to as a Universal Input Buffer structure. This type of
buffer is designed to accept Differential or single ended inputs and it is sensitive enough to act as a LVPECL or
LVDS in differential mode and LVCMOS in Single ended mode. With the proper external termination various
types of inputs signals can be supported. Those inputs will be discussed in a separate document (application
Notes).
The CDCE72010 has two internal voltage biasing circuitries. One to set the termination voltage for references
(PRI_REF and SEC_REF) and the second biasing circuitry is to set the termination voltage to the VCXO_IN and
AUX_IN. This means that we can only have one type of differential signal on PRI_REF and SEC_REF and only
one type of differential signal on VCXO_IN and AUX_IN.
PRI_REF Buffer Settings
PRI_REF & SEC_REF Input Buffer Settings
Configuration
Settings
0.0 0.1 1.0 1.1
0
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
X
X
X
0
1
X
0
1
X
X
X
1
1
1
1
1
1
1
0
1
1.2 1.3/4
X
0
0
1
0
0
1
X
X
X
0
0
X
0
0
X
X
X
Hyst
Mode
Coup
PRI_REF
Input
Term
Vbb
50W 50W
ON
ON
ON
ON
ON
ON
ON
OFF
ON
LVCMOS
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVDS
---
DC
AC
DC
-AC
DC
----
N/A
Internal
Internal
External
Internal
Internal
External
---
-1.9V
1.2V
-1.2V
1.2V
----
VBB
P
N
Register / Bits
0.0
0
X
X
X
0.1
0
X
1
1
1.2
X
1
0
0
1.3
X
P
O
X
0
1
O
C
C
Switch
N
O
O
C
C
INV
O
O
C
O
INV
SEC_REF Buffer Settings
INV
P
Register / Bits
N
50W 50W
SEC_REF
Input
0.0
0
X
X
X
0.1
0
X
1
1
1.2
X
1
0
0
1.4
X
P
O
X
0
1
O
C
C
Switch
N
O
O
C
C
INV
O
O
C
O
Figure 16. PRI_REF and SEC_REF Voltage Biasing Circuitry
48
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VCXO Input Buffer Settings
VCXO & AUX Input Buffer Settings
8.0 8.1 8.2 8.3
0
1
1
1
1
1
1
X
X
0
0
0
0
1
1
1
X
X
X
0
1
X
0
1
X
X
X
1
1
1
1
1
1
1
0
1
Register / Bits
Configuration
Settings
8.4
8.5
Hyst
Mode
Coup
Term
Vbb
X
0
0
1
0
0
1
X
X
X
0
0
X
0
0
X
X
X
ON
ON
ON
ON
ON
ON
ON
OFF
ON
LVCMOS
LVPECL
LVPECL
LVPECL
LVDS
LVDS
LVDS
---
DC
AC
DC
-AC
DC
----
N/A
Internal
Internal
External
Internal
Internal
External
---
-1.9V
1.2V
-1.2V
1.2V
----
VCXO
Input
50W 50W
VBB
P
8.0
0
X
X
X
8.1
0
X
1
1
8.4
X
1
0
0
8.5
X
P
O
X
0
1
O
C
C
Switch
N
O
O
C
C
INV
O
O
C
O
N
INV
AUX
Input
Figure 17. VCXO_IN and AUX_IN Voltage Biasing Circuitry
AUTOMATIC/MANUAL REFERENCE CLOCK SWITCHING (SMART MUX)
The CDCE72010 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary
clock input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected
by the dedicated SPI register. In the manual mode the external REF_SEL signal selects one of the two input
clocks
In the automatic mode the primary clock is selected by default even if both clocks are available. In case the
primary clock is not available or fails, then the input switches to the secondary clock until the primary clock is
back. The figure below shows the automatic clock selection.
PRI_REF
1
1
SEC_REF
2
3
4
2
Internal
Reference Clock
Auto-Reference
primary
secondary
primary
VCXO With
100Hz Loop
Figure 18. Automatic Clock Select Timing
In the automatic mode the frequencies of both clock signals has to be similar but may differ by up to 20%. There
is no limitation placed on the phase relationship between the two inputs.
The clock input circuitry is designed to suppress glitches during switching between the primary and secondary
clock in the manual and automatic mode. This insures that the clock outputs continue to clock reliably when a
transition from a clock input occurs.
The phase of the output clock will slowly follow the new input phase. The speed of this transition is determined
by the loop bandwidth. However, there is no phase build-out function supported (like in SONET/SDH
applications).
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PHASE FREQUENCY DETECTOR
The main function of the CDCE72010 device is to synchronize a Voltage Control Oscillator (VCO) or a Voltage
Control Crystal Oscillator (VCXO) output to a reference clock input. The phase detector compares 2 signals and
outputs the difference between them. It is symbolized by an XOR. The compared signals are derived from the
Reference clock and from the VCO/VCXO clocks. The Reference clock is divided by the “R” Divider (1 or 2) and
“M” divider (14 Bits) and presented to the PFD. The VCO/VCXO clock is divided by the Feedback Divider “P” (1
to 80) and the “N” Divider (14 Bits) and presented to the PFD.
Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)
The PFD is a classical style with UP and DOWN signals generating flip-flops and a common reset path. Some
special functions were implemented:
• Bit CP_DIR (register 0 RAM bit<9> can swap internally the REF- and FB-CLK inputs to the PFD flip-flops.
• The reset path can be typically delayed with the bits DELAY_PFD <1:0> (register 0 RAM bit<7:6>) from 1.5ns
to 6.0ns.
PFD Pulse Width Delay (Register 0 RAM Bits [7:6])
The “PFD pulse width delay” gets around the dead zone of the PFD transfer function and reduces phase noise
and reference spurs.
Table 9. PFD Pulse Width Delay
(1)
PFD1
PFD0
PFD PULSE WIDTH DELAY
0
0
1.5ns (1)
0
1
3.0ns
1
0
4.5ns
1
1
6.0ns
Default
The PFD receives two clocks of the similar frequencies and decides if one is lagging or leading. This
Lagging/Leading signals are feed to the Charge Pump. The Charge Pump in its turn takes the Lagging/Leading
signals and translate them into current pulses that are feed to the external filter. The Output of the external filter
is a DC level that controls the Voltage reference of the VCO/VCXO sitting outside and feeding the CDCE72010
at the VCXO Input. The VCO/VCXO drifts its outputs frequency with respect to the voltage applied to its Voltage
Control pin. This is how the loop is closed.
PRI_REF
Maximum Frequency = 250 MHz
Div 1,2
Register 11::
0
Register 2
RAM Bit 5:0
1
SEC_REF
VCXO_IN
Feedback Mux
Div 1,2
R’ Divider
Smart Mux
Feedback Divider
1,2,3,4,5,6,8,10,12…..80
P Divider
AUX_IN
Divide Function Register 11:: 5
6
7
8
9
10 11
Phase Function Register 11:: 12 13 14 15 16 17 18
0
1
2
3
4
5
6
M Delay
M Divider (14 Bits)
N Delay
N Divider (14 Bits)
14 15 16 17 18 19 20
7
8
9
10 11 12
13 ::Register 10
PFD Out to
Charge Pump
21 22 23 24 25 26 27 ::Register 10
Maximum Frequency = 250 MHz
Figure 19. Phase Frequency Detection
50
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Table 10. Feedback Divider Settings
FEEDBACK DIVIDER SETTINGS (REGISTER 11: BITS)
11
10
9
8
7
6
5
DIVIDER
SETTING
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
2
1
0
0
0
0
0
1
3
1
0
0
0
0
1
0
4
1
0
0
0
0
1
1
5
0
0
0
0
0
0
0
4'
0
0
0
0
0
0
1
6
0
0
0
0
0
1
0
8
0
0
0
0
0
1
1
10
0
0
0
0
1
0
0
8'
0
0
0
0
1
0
1
12
0
0
0
0
1
1
0
16
0
0
0
0
1
1
1
20
0
0
0
1
0
0
0
12'
0
0
0
1
0
0
1
18
0
0
0
1
0
1
0
24
0
0
0
1
0
1
1
30
0
0
0
1
1
0
0
16'
0
0
0
1
1
0
1
24'
0
0
0
1
1
1
0
32
0
0
0
1
1
1
1
40
0
0
1
0
0
0
0
20'
0
0
1
0
0
0
1
30'
0
0
1
0
0
1
0
40'
0
0
1
0
0
1
1
50
0
0
1
0
1
0
0
24'
0
0
1
0
1
0
1
36
0
0
1
0
1
1
0
48
0
0
1
0
1
1
1
60
0
0
1
1
0
0
0
28
0
0
1
1
0
0
1
42
0
0
1
1
0
1
0
56
0
0
1
1
0
1
1
70
0
0
1
1
1
0
0
32'
0
0
1
1
1
0
1
48'
0
0
1
1
1
1
0
64
0
0
1
1
1
1
1
80
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PHASE DELAY FOR M AND N
Delay Block in M/N Path
Table 11. Reference Delay M (PRI_REF or SEC_REF) and Feedback Delay N (VCXO) Phase Adjustment
(Register 2 RAM Bits [5:0]) (1)
(1)
(2)
DLYM2/DLYN2
DLYM1/DLYN1
DLYM0/DLYN0
PHASE OFFSET
0
0
0
0ps (2)
0
0
1
±160ps
0
1
0
±320ps
0
1
1
±480ps
1
0
0
±830ps
1
0
1
±1130ps
1
1
0
±1450ps
1
1
1
±1750ps
If Progr Delay M is set, all Yx outputs are lagging to the Reference Clock according to the value set. If Progr Delay N is set, all Yx
outputs are leading to the Reference Clock according to the value set. Above are typical values at VCC = 3.3 V, TA = 25°C, PECL-output
relate to Div4 mode.
Default
Table 12. Reference Divider M/N 14-Bit (Register 10 RAM Bits [13:0] for M and RAM Bits [27:14] for N)
N6
N5
N4
N3
N2
N1
N0
DIV BY (1)
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
2
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
1
1
4
1
1
1
1
1
128 (2)
N13
N12
N11
N10
N9
N8
N7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
•
•
•
0
0
0
0
0
0
0
1
1
•
•
•
(1)
(2)
52
1
1
1
1
1
1
1
1
1
1
1
1
0
1
16382
1
1
1
1
1
1
1
1
1
1
1
1
1
0
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16384
If the divider value is Q, then the code will be the binary value of (Q - 1).
Default
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CHARGE PUMP
The Charge Pump drives the loop filter that controls the external VCO/VCXO. The Charge pump frequency is
determined by the PFD frequency since the function of the charge pump is to translate the UP DOWN signals of
the PFD into current pulses that drives the external filter. The Charge pump current is set by the control vector
ICP [3:0]. The error amplifier operates from 0.7V to the VDD supply voltage. See the table below for ICP settings.
Table 13. CP, Charge Pump Current (Register 0 RAM Bits [17:14])
(1)
ICP3
ICP2
ICP1
ICP0
TYPICAL CHARGE PUMP
CURRENT
0
0
0
0
0 µA (3-State)
0
0
0
1
200 µA
0
0
1
0
400 µA
0
0
1
1
600 µA
0
1
0
0
800 µA
0
1
0
1
1.0 mA
0
1
1
0
1.2 mA
0
1
1
1
1.4 mA
1
0
0
0
1.6 mA
1
0
0
1
1.8 mA
1
0
1
0
2.0 mA
1
0
1
1
2.2 mA (1)
1
1
0
0
2.4 mA
1
1
0
1
2.6 mA
1
1
1
0
2.8 mA
1
1
1
1
3.0 mA
Default
The ‘Preset Charge-Pump to VCC_CP/2 is a useful feature to quickly set the center frequency of the VC(X)O after
Power-up or Reset. The adequate control voltage for the VC(X)O will be provided to the Charge-Pump output by
an internal voltage divider of 1KΩ/1KΩ to VCC_CP and GND (VCC_CP/2).
This feature helps to get the initial frequency accuracy, i.e. required at CPRI (Common Public Radio Interface) or
OBSAI (Open Base Station Architecture Initiative).
The Preset Charge-Pump to VCC_CP/2 can be set and reset by SPI register.
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Charge-Pump Current Direction
The direction of the charge-pump (CP) current pulse can be changed by the SPI register settings. It determines
in which direction CP current will regulate (Reference Clock leads to Feedback Clock). Most applications use the
positive CP output current (power-up condition) because of the use of a passive loop filter. The negative CP
current is useful when using an active loop filter concept with inverting operational amplifier. The Figure below
shows the internal PFD signal and the corresponding CP current.
Reference Clock After
the M Divider and Delay
Reference Clock After
the N Divider and Delay
V(PFD1) (Internal Signal)
V(PFD2) (Internal Signal)
Charge Pump Output
Current Icp
Charge Pump Output
Current Icp (Inverted)
p
.
PFD pulse width delay improves spurious suppression.
Figure 20. Charge Pump
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PLL LOCK FOR ANALOG AND DIGITAL DETECT
The CDCE72010 supports two PLL Lock indications: the digital lock signal or the analog lock signal. Both signals
indicate logic high-level at PLL_LOCK if the PLL locks according the selected lock condition.
The PLL is locked (set high), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and
Feedback Clock (VCXO_IN clock) at the PFD (Phase Frequency Detect) are inside a predefined lock detect
window for a pre-defined number of successive clock cycles.
The PLL is out-of-lock (set low), if the rising edge of the Reference Clock (PRI_REF or SEC_REF clock) and
Feedback Clock (VCXO_IN clock) at the PFD are outside the predefined lock detect window.
Both, the lock detect window and the number of successive clock cycles are user definable in the SPI register
settings.
Selected REF at PFD
(clock fed through M Divider
and M Delay
t (lockdetect)
VCXO_IN at PFD
(clock fed through N Divider
and N Delay)
Figure 21. PLL Lock
The lock detect window describes the maximum allowed time difference for lock detect between the rising edge
of PRI_REF or SEC_REF and VCXO_IN. The time difference is detected at the phase frequency detector. The
rising edge of PRI_REF or SEC_REF is taken as reference. The rising edge of VCXO_IN is outside the lock
detect window, if there is a phase displacement of more than +0.5*t(lockdetect) or -0.5*t(lockdetect).
Table 14. Lock-Detect Window (Register 7 RAM Bits [1:0] and Register 9 RAM Bits [7:6])
(1)
(2)
LOCKW3
[7]
LOCKW2
[6]
LOCKW1
[1]
LOCKW0
[0]
0
0
0
0
1.5 ns
1
1
0
1
5.8 ns (2)
0
0
1
0
15.1 ns
0
0
1
1
Reserved
0
1
0
0
3.4 ns
0
1
0
1
7.7 ns
0
1
1
0
17.0 ns
0
1
1
1
Reserved
1
0
0
0
5.4 ns
1
0
0
1
9.7 ns
1
0
1
0
19.0 ns
1
0
1
1
Reserved
1
1
0
0
15.0 ns
1
1
0
1
19.3 ns
1
1
1
0
28.6 ns
1
1
1
1
Reserved
PHASE-OFFSET AT PFD-INPUT (1)
Typical values at VCC = 3.3 V, TA = 25°C
Default
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Table 15. Number of Successive Lock Events Inside the Lock Detect Window
(Register 7 RAM Bits [4:3]) the PLL Lock Signal is Delayed for Number of
FB_CLK Events
(1)
LOCKC1
LOCKC0
NO. OF SUCCESSIVE LOCK
EVENTS
0
0
1
0
1
16
1
0
64 (1)
1
1
256
Default
DIGITAL LOCK DETECT
When selecting the digital PLL lock option, PLL_LOCK will possibly jitter several times between lock and out of
lock until a stable lock is detected. A single “low-to-high” step can be reached with a wide lock detect window
and high number of successive clock cycles. PLL_LOCK will return to out of lock if just one cycle is outside the
lock detect window.
VOut
Power_Down
PLL_LOCK
Output
Lock_Out
Digital Lock Detection
Lock
160 kW
5pF
Out-of-Lock
t
Lock_In
Vhigh = 0.6 VCC
Vlow = 0.4 VCC
Figure 22. Digital Lock
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ANALOG LOCK DETECT
When selecting the analog PLL Lock option, the high-pulses load the external capacitor via the internal 110 µA
current source until logic high-level is reached. Therefore, more time is needed to detect logic high level, but
jittering of PLL_LOCK will be suppressed like possible in case of digital lock. The time PLL_LOCK needs to
return to out of lock depends on the level of VOUT, when the current source starts to unload the external
capacitor.
VCC
110 µA
(Lock)
VOut
PLL_LOCK
(Output)
Power_Down
Lock_Out
5pF
VOut = 1/C * I * t
C
110 µA
(Out-of-Lock)
t
Example:
for I = 110 µA, C = 10 n, VCC = 3.3 V and
Vhigh = VOut = 0.55 * VCC = 1.8 V
=> t = 164 µs
160 kW
Lock_In
Vhigh = 0.55 VCC
Vlow = 0.35 VCC
Figure 23. Analog Lock
FREQUENCY HOLD-OVER MODE
The HOLD-Function is a CDCE72010 feature that helps to improve system reliability. The HOLD-Function holds
the output frequency in case the input reference clock fails or is disrupted. During HOLD, the Charge-Pump is
switched off (3-State) freezing the last valid output frequency. The Hold-Function will be released after a valid
reference clock is reapplied to the clock input and detected by the CDCE72010. For proper HOLD function, the
Analog PLL-Lock-Detect mode has to be active. The following settings are involved with the HOLD Function:
• Lock Detect Window: Defines the window in ns inwhich the Lock is valid. The size is 3.5ns, 8.5ns, 18.5ns.
Lock is set if Reference Clock and Feedback Clock are inside this predefined Lock-Detect Window for a
pre-selected number of successive cycles.
• Out-of-Lock: Defines the out-of-lock condition: If the Reference Clock and the Feedback Clock at the PFD are
outside the predefined Lock Detect Window.
• Number of Clock Cycles: Defines the number of successive PFD cycles which have to occur inside the lock
window to set Lock detect. This does not apply for Out-of-Lock condition.
• Hold-Function: Selects HOLD-Function (see more details below).
• Hold-Trigger: Defines whether the HOLD-Function is always activated or whether it is dependent on the state
of the analog PLL Lock detect output. In the latter case, HOLD is activated if Lock is set (high) and
de-activated if Lock is reset (low).
• Analog PLL Lock Detect: Analog Lock output charges or discharges an external capacitor with every valid
Lock cycle. The time constant for Lock detect can be set by the value of the capacitor.
The CDCE72010 supports two types of HOLD functions, one external controllable HOLD mode and one internal
mode, HOLD.
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EXTERNAL/HOLD FUNCTION
The Charge Pump can directly be switched into 3-State. This function is also available via SPI register. If logic
low is applied to HOLD pin the Charge Pump will be switched to 3-State. After HOLD pin is released, the charge
pump is switched back in to normal operation, with the next valid reference clock cycle at PRI_REF or SEC_REF
and the next valid feedback clock cycle at the PFD. During HOLD, all divider and all outputs are at normal
operation.
INTERNAL/HOLD FUNCTION
In Internal HOLD Function or HOLD-Over-Function the PLL has to be in lock to start the HOLD function. It
switches the Charge Pump in to 3-State when an ‘out-of-lock’ event occurs. It leaves the ‘3-State Charge Pump’
state when the Reference Clock is back. Then it starts a locking sequence of 64 cycles before it goes back to the
beginning of the HOLD-Over loop.
PLL has to be in LOCK to start
HOLD-Function.
Frequency Hold-Over Function works in
combination with the Analog Lock -Detect
no
( The Analog Lock output is not reset by the first Out-ofLock event. It stays ‘High’ depending on the analog time
delay ( output C-load). The time delay must be long enough
to guarantee proper HOLD function)
The Charge-Pump remains into 3-State
until the Reference Clock is back. The 1 st
valid Reference Clock at the PFD releases
the Charge-Pump.
Charge-Pump is switched into 3-State.
no
no
Start
PLL
PLL-Lock
Out-of-Lock
Output Set
PLL is out-of-lock if the phase
difference of Reference Clock and
Feedback Clock at PFD are outside the
predefined Lock-Detect-Window or if a
Cycle-Slip occurs.
yes
3-State
Ref. Clock
Charge Pump
is Back
yes
64 PFD
Lock Cycles
no
The PLL acquire 64 lock cycles to phase
align to the input clock.
Figure 24. Frequency Hold Over
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OUTPUT DIVIDERS AND PHASE ADJUST
The CDCE72010 is designed with individual Output Dividers for Outputs 1 to 8. Output Divider 1 drives Output 1
and Output 0 and Output Divider 8 drives Output 8 and Output 9. Each output divider has a bypass function or it
is referred to as divide by “one”. Since divide by one bypasses the divider block it can address higher operating
frequencies.
The output divider is designed to address divide by 1, 2, 3, 4, 5, 6, 8, 10, 12, 16, 18, 20, 24, 28, 30, 32, 36, 40,
42, 48, 50, 56, 60, 64, 70 and 80.The output divider includes a coarse phase adjust that shifts the divided clock
signal. The phase adjust resolution is a function of the divide function. The maximum number of phase steps
equals to the divider setting.
If the output is divide by 2, then two phase adjustment settings (0 and 180 degrees) are available. The resolution
of phase adjustment is related to the output divider setting by the following: Phase adjust resolution = (1/Output
Divider settings) X 360 Degrees.
Example: For a 491.52MHz VCXO where one of the outputs of the device is set to divide by 16 for a 30.72MHz
desired output, this will mean that the 30.72MHz clock will have (1/16) X 360 = 22.5 Degrees of phase
adjustment resolution.
Output Divide Select (OUT#DIVSEL#) and Coarse Phase Adjust Select (PH#ADJC#) registers are located in
Register 1 thought 8 for Output 1 thought 8 respectively.
The Phase difference between 2 divider settings on different output can be calculated using the following formula
and referring to the Phase Lag number in the Output Divider Table ( see Table 7).
Integer Remainder of [(Phase Lag X - Phase Lag Y)/ Divide X ] as an example if we need to calculate the phase
difference between divide by 4 and divide by 8 with respect to divide by 4 clock.
The Integer Remainder [(28.5 - 0.5)/4] = 0. This means there is 0 Cycle phase delay between Divide by 4 and
Divide by 8 with respect to Divide by 4 Clock.
If we need to do the same calculation with respect to Divide by 8 we will have Intger Remainder [(28.5 – 0.5)/8] =
0.5 that means that there is 0.5 Cycles between Divide by 4 and divide by 8 with respect to a divide by 8 clock.
(PH#ADJC#)
Phase Adjust Period
Coarse Phase Adjust Select
Start Divider
D
D
D
D
D
Output Divider
(OUT#DIVSEL#)
Figure 25. Maximum Output Frequency With Phase Alighment
For a complete listing of the coarse phase adjust settings, refer to the "CDCE72010 Coarse Phase Adjust"
document.
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DEVICE LAYOUT
The CDCE72010 is a high performance device packaged in a QFN-64. The die has all the ground pins bounded
to the thermal PAD on the bottom of the package. Therefore it is essential that the connection from the thermal
PAD to the ground layers should be low impedance. In addition, the thermal path in a QFN package is via the
thermal PAD on the bottom of the package. Therefore, the layout of the PAD is very important and it will affect
the thermal performance as well as the overall performance of the device. The illustration shown provides
optimal performance in terms of thermal issues, inductance and power supply bypassing. The 10 X 10 Filled VIA
pattern recommended allows for a low inductance connection between the thermal ground pad and the ground
plane of the board. This pattern forms a low thermal resistive path for the heat generated by the die to get
dissipated through the ground plane and to the exposed bottom side ground pad. It is recommended that solder
mask not be used on this bottom side pad to maximize its effectiveness as a thermal heat sink. The
recommended layout drives the thermal conductivity to 22.8 C/W in still air and 13.8 C/W in a 100LFM air flow if
implemented on a JEDEC compliant test thermal board.
Top Side Thermal PAD Layout
Only two capacitors are illustrated.
Only one side of the pin pads is shown.
Bottom Side Thermal PAD Layout
Only two capacitors are illustrated.
Figure 26. Device Layout
60
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CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
DEVICE POWER
The CDCE72010 is designed as a high performance device, therefore careful attention must be paid to device
configuration with respect to power consumption. Total power consumption of the device can be estimated by
adding up the total power consumed by each block in the device.
The Table below describes the blocks used and power consumed per block. The total power of the device can
be calculated by multiplying the number of blocks used by the power consumption per block.
Table 16. Device Power
INTERNAL BLOCK POWER AT 3.3V (Typ)
POWER DISSIPATED / BLOCK
NUMBER OF BLOCKS / DEVICE
PLL Core and Input and Feedback Circuitries
530mW
1
Output Dividers
180mW
8
Output Buffers ( LVPECL-HISWING)
(1)
150mW
10
Output Buffers (LVDS-HISWING) (1)
75mW
10
Output Buffers (LVCMOS at 122 MHz) (1)
50mW
20
(1)
Output buffers can be a total of 10 LVDS, 10 LVPECL, or 20 LVCMOS.
125
Max Die Temp
100
JEDEC 0 LFM 25 C
Die Temp (C)
JEDEC 100 LFM 25 C
RL 0 LFM 25 C
75
RL 100 LFM 25 C
50
JEDEC 0 LFM 85 C
JEDEC 100 LFM 85 C
RL 0 LFM 85 C
25
RL 100 LFM 85 C
0
0
1
2
3
4
Power (W)
Figure 27. Die Temperature
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CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
LOOP FILTER
The CDCE72010 is designed to control an external Voltage Controlled Oscillator (VCO) or a Voltage Controlled
Crystal Oscillator (VCXO) and to synchronize the controlled oscillators to the input reference. Controlling the
Oscillator happens via a DC voltage that is applied to the Voltage control pin. This DC voltage is generated by
the CDCE72010 in the form of AC pulses that get filtered by the external loop filter.
CDCE72010
VccCP
VccCP
VCO/VCXO
R3
Charge
Pump
Clock Out
C1
R2
C3
C2
Figure 28. Loop Filter
62
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Product Folder Link(s): CDCE72010
CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
UNIVERSAL OUTPUT BUFFERS
The CDCE72010 is designed to drive three types of clock signaling, LVPECL, LVDS, and LVCMOS from each of
the ten outputs. This super buffer that contains all three drivers is refered to as the Universal Output Buffer. Only
one driver can be enabled at one time. Each universal output buffer is made from four independent buffers in
parallel. When LVPECL mode is selected, only the LVPECL Buffer is enabled and the rest of the buffers are
3-stated and in low power mode. When Selecting LVDS, only the LVDS Buffer is enabled and the rest of the
buffers are 3-stated and in low power mode. When LVCMOS mode is selected, both LVCMOS drivers are
enabled. One LVCMOS buffer drives the negative side and the other buffer drives the positive pin.
The LVCMOS drivers are driven from the same output divider but have separate control bits. In SPI Mode, bits
22, 23, 24, and 25 of Registers 0 to 9 are used to put the LVCMOS buffer in active, inverting, low, or 3-state. In
CD Mode, those bits are used for different functions and the LVCMOS buffer can be active when selected or
3-state when their not.
LVCMOS
LVPECL
Register (0 to 9)
RAM Bits::
21
22
23
24
25
26
27
LVDS
LVCMOS
Figure 29. Universal Output Buffer
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CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
Output Dividers Synchronization
The CDCE72010 is a 10 output clock device with 8 output dividers and to insure that all the outputs are
synchronous a synchronization startup circuitry is used. The synchronization circuitry generates a pulse to reset
all the dividers in a way, that a predictable synchronous output is generated. The Synchronization signal can be
generated from different sources and can be synchronized to a specific clock. The Block diagram below
illustrates the signal path of the Output Divider Sync Signal. This function is assured up to 500 MHz.
NOTE:
The minimum frequency required for the output synchronization block to work properly
is 1 MHz.
Any of the Conditions will Produce a Conditional SYNC Start Signal:
1- REG9 <Bit11> INDET_BP is set to “0” & VCXO or AUX_CLK is available
2- REG9<Bit12> PLL_LOCK_BP is set to “0” & we have 1 st Lock State
3- REG11<Bit19> PD_PLL is set to “0”& the PLL is ON
4- REG9<Bit13> LOW_FD_FB_EN is set to “1” N Divider Input Frequency above 600KHz
5- Write Activity to the Output Divider (s)
6- REG12<Bit8> Set to 1 ( /RESET Bit is Set to “1”)
7- REG12<Bit7> Set to 1 ( /Power Down Bit is Set to “1”)
If the value of the bits described as inverted the function associated with it will be ignored
with respect to the sync start signal generation.
/RESET Pin
Feedback Clock
“1”
REG6<Bit2> FB_DETERM_DIV_SEL
“0” Feedback Divider Clock
“1” Divide by 2 Feedback Clock
Reference Clock
“0” REG6<Bit5>
DET_START_BYPASS
“0”
“1”
REG0<Bit4> VCXOSEL
“0”
Synchronizing Output Divider SYNC Signal
OUTPUT DIVIDERS
1” REG9<Bit10>
STARTBYPASS
SYNC SIGNAL
Figure 30. Output Divider Synchronization Block Diagram
64
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CDCE72010
www.ti.com.............................................................................................................................................................. SCAS858A – JUNE 2008 – REVISED JULY 2009
POWER UP RESET, POWER DOWN MODE AND RESET OR HOLD
The CDCE72010 is designed to address various clock synchronization applications. Some functions can be set
to be in automatic and manual mode or some functions can be controlled by software or by the internal circuitry.
Figure 31 below explains the various functionalities of power up reset internal circuitry functionality, power down
functionality and reset functionality. The hold function shares the same block with Reset and one bit in the
EEPROM will select either function.
VCC
Reset SPI Interface and Register 12 to Default
POR
/PD
REG12: 11 12
Power All Clocking Circuitry Down
- Shut Down All Analog Circuitry (/PD = 0 or Sleep = 0)
Sleep
- Shut Down All Digital Circuitry (/PD = 0 or Sleep = 0)
- Disable All Output Buffers (/PD = 0 or Sleep = 0)
- Load EEPROM Into RAM When Released (at Rising Edge of /PD)
PD or
Sleep
Reset
Reset
or
Hold
/Reset_Hold
(Force Sleep/PD and /RESET or /HOLD)
Reset Digital Circuitry
- Disable All Output Buffers (When /RESET = 0)
- Reset PLL (Load With RAM Content Values at Rising Edge)
- Reset Output Dividers and Phase Adjust Circuitry (at Rising Edge)
Hold
REG11: 29
REG4: 04
When Hold Function Is Asserted
- Tri-state the Charge Pump Output When /HOLD = 0
Hold Function Is Deasserted When
- /HOLD = 1 and We Have Valid Reference Clock
Loss of Reference
Figure 31. Powerup, Reset, and Powerdown Block Diagram
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65
CDCE72010
SCAS858A – JUNE 2008 – REVISED JULY 2009.............................................................................................................................................................. www.ti.com
REVISION HISTORY
Changes from Original (June 2008) to Revision A ......................................................................................................... Page
•
•
•
•
•
•
•
•
•
•
•
•
•
66
Changed Frequency equation result from (R*M)/(P*N) to (P*N)/(R*M)................................................................................. 2
Added table note to Table 4................................................................................................................................................. 19
Added table note to Register 0: SPI Mode table description............................................................................................... 21
Changed Register 12: SPI Mode (RAM only Register) Note............................................................................................... 33
Added table note to Register 0:CD Mode table description................................................................................................. 36
Added additional information to INTERFACE, CONFIGURATION, AND CONTROL description....................................... 48
Changed Figure 16 ............................................................................................................................................................. 48
Changed Figure 17 ............................................................................................................................................................. 49
Added “P” to PHASE FREQUENCY DETECTOR feedback divider description ................................................................. 50
Changed Frequency equation from (R*M)/(P*N) to (P*N)/(R*M)......................................................................................... 50
Deleted P is the product of X Divider and FB Divider R and X Divider is set to be divide by 1 or 2................................... 50
Changed Figure 19 by adding maximum frequency = 250 MHz ......................................................................................... 50
Added note to Output Dividers Synchronization description ............................................................................................... 64
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jul-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCE72010RGCR
ACTIVE
VQFN
RGC
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CDCE72010RGCRG4
ACTIVE
VQFN
RGC
64
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CDCE72010RGCT
ACTIVE
VQFN
RGC
64
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CDCE72010RGCTG4
ACTIVE
VQFN
RGC
64
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCE72010RGCR
VQFN
RGC
64
2000
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
CDCE72010RGCT
VQFN
RGC
64
250
330.0
16.4
9.3
9.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Jul-2009
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCE72010RGCR
VQFN
RGC
64
2000
333.2
345.9
28.6
CDCE72010RGCT
VQFN
RGC
64
250
333.2
345.9
28.6
Pack Materials-Page 2
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