CS1088 Vacuum Fluorescent Display Tube Driver The VFD Driver is a microprocessor interface IC that drives a multiplexed VF (Vacuum Fluorescent) display tube. It consists of a 34–bit shift register, a 34–bit transparent data latch, a metal mask ROM, six 20 mA anode output drivers, twenty–five 2 mA anode output drivers, and three 50 mA grid drivers with output enables. The metal mask programmable ROM (at factory request) allows the 31 anode outputs and 3 grid outputs to be assigned to any of the 34 serial data bits. Features Metal Mask ROM Six 20 mA Anode drivers Twenty–five, 2 mA Anode drivers Three, 50 mA Grid drivers Power On Reset Display Dimming Possible http://onsemi.com DIP–40 WIDE BODY N SUFFIX CASE 711 40 • • • • • • 1 ORDERING INFORMATION Device CS1088XN40 Shipping DIP–40 WIDE BODY 9 Units/Rail DEVICE MARKING INFORMATION APPLICATION DIAGRAM VIGN Package See general marking information in the device marking section on page 7 of this data sheet. Chip Select 12 V Regulator Clock SPI Functions 5V GND Anodes 1:31 0.1 µF VBAT VBB CS1088 VCC µP PORT PORT PORT GND PORT GRID1GRID2 GRID3 GND DIN GRID1 CLK GRID2 STB GRID3 GREN GND Semiconductor Components Industries, LLC, 2001 February, 2001 – Rev. 8 FILAMENT VFD 1 Publication Order Number: CS1088/D CS1088 ABSOLUTE MAXIMUM RATINGS* Parameter Value Unit Supply Voltage (VBB) –0.6 to +18 V Input Voltages (DIN, CLK, STB, GREN) –0.6 to +6.0 V Junction Temperature Range –40 to +150 °C Storage Temperature Range –55 to +150 °C ESD Susceptibility (Human Body Model) 2.0 kV ESD Susceptibility (Machine Model) 200 V 260 Peak 230 Peak °C Lead Temperature Soldering: Wave Solder (through hole styles only) Note 1. Reflow (SMD styles only) Note 2. 1. 10 second maximum. 2. 60 second maximum above 183°C. *The maximum package power dissipation must be observed. ELECTRICAL CHARACTERISTICS (8.0 V ≤ VBB ≤ 16.5 V, Gnd = 0 V, –40°C ≤ TJ ≤ 105°C; unless otherwise stated.) Parameter Test Conditions Min Typ Max Unit – 8.0 – 16.5 V VBB Input VBB Input Voltage IBB0 Current No outputs active, VBB = 16.5 V – 2.0 5.0 mA Reset Mode All outputs forced low. – 6.5 7.5 V DIN, CLK, STB Inputs VIL1, Input Low Voltage – – – 1.6 V VIH, Input High Voltage – 3.3 – – V – 7.5 20.0 µA IIL, Input Current VIN = VIH GREN Input VIL, Input Low Voltage – – – 1.6 V VIH, Input High Voltage – 3.3 – – V VIN = 3.325 V – 30 60 µA IOL Sink Current 1.0 – – mA IOH Source Current 50 – – mA VOL IOUT = 1.0 mA – – 0.5 V VOH IOUT = –50 mA, VBB = 12 V VBB – 0.75 – VBB V IIH, Input Pull–down Current GRID1, GRID2, GRID3 Outputs AN24 – AN29 Outputs IOL Sink Current 400 – – µA IOH Source Current 20 – – mA VOL IOUT = 400 µA – – 0.5 V VOH IOUT = –20 mA, VBB = 12 V VBB – 0.5 – VBB V AN1 – AN23 Outputs IOL Sink Current 100 – – µA IOH Source Current 2.0 – – mA VOL IOUT = 100 µA – – 0.5 V VOH IOUT = –2.0 mA, VBB = 12 V VBB – 0.5 – VBB V http://onsemi.com 2 CS1088 ELECTRICAL CHARACTERISTICS (continued) (8.0 V ≤ VBB ≤ 16.5 V, Gnd = 0 V, –40°C ≤ TJ ≤ 105°C; unless otherwise stated.) Parameter Test Conditions Min Typ Max Unit AC Characteristics: Input and Output Timing FC, CLK Frequency – 0 – 1.0 MHz TCL, CLK Low Time – 200 – – ns TCH, CLK High Time – 200 – – ns TCR, CLK Rise Time – – – 100 ns TCF, CLK Fall Time – – – 100 ns TSC, STB Low to CLK High Time – 50 – – ns TST, STB High Time – 500 – – ns TAN, STB High to Anode Output Propagation Delay – – – 5.0 µs TGL, Grid Turn On Propagation Delay VBB = 12 V – – 2.0 µs TG0, Grid Turn Off Propagation Delay VBB = 12 V – – 5.0 µs TGR, Grid Rise Time At rated load. Note 1. 0.50 – 2.00 µs TGF, Grid Fall Time At rated load. Note 1. 0.35 – 2.00 µs TAR, Anode Rise Time At rated load. Note 1. 0.40 – 2.00 µs TAF, Anode Fall Time At rated load. Note 1. 0.40 – 2.50 µs 1. Grid and anode rise / fall times are measured from 10% and 90% points. Output currents are at the maximum rated currents for the respective stages. PACKAGE LEAD DESCRIPTION Package Lead Number 40L DIP Lead Symbol (31 Anode Configuration) Function 1 GRID1 50 mA grid output. 2 GRID2 50 mA grid output. 3 GRID3 50 mA grid output. 4 AN1 2.0 mA anode output. 5 AN2 2.0 mA anode output. 6 AN3 2.0 mA anode output. 7 AN4 2.0 mA anode output. 8 AN5 2.0 mA anode output. 9 AN6 2.0 mA anode output. 10 AN7 2.0 mA anode output. 11 AN8 2.0 mA anode output. 12 AN9 2.0 mA anode output. 13 AN10 2.0 mA anode output. 14 AN11 2.0 mA anode output. 15 AN12 2.0 mA anode output. 16 AN13 2.0 mA anode output. 17 AN14 2.0 mA anode output. 18 AN15 2.0 mA anode output. 19 AN16 2.0 mA anode output. http://onsemi.com 3 CS1088 PACKAGE LEAD DESCRIPTION (continued) Package Lead Number 40L DIP Lead Symbol (31 Anode Configuration) Function 20 GND Ground connection. 21 AN17 2.0 mA anode output. 22 AN18 2.0 mA anode output. 23 AN19 2.0 mA anode output. 24 AN20 2.0 mA anode output. 25 AN21 2.0 mA anode output. 26 AN22 2.0 mA anode output. 27 AN23 2.0 mA anode output. 28 AN24 20 mA anode output. 29 AN25 20 mA anode output. 30 AN26 20 mA anode output. 31 AN27 20 mA anode output. 32 AN28 20 mA anode output. 33 AN29 20 mA anode output. 34 AN30 2.0 mA anode output. 35 DIN Shift register data input. 36 CLK Shift register clock input. 37 STB Transfer contents of shift registers to output stages. 38 GREN Grid outputs enable. 39 AN31 2.0 mA anode output. 40 VBB Supply voltage input. http://onsemi.com 4 CS1088 BLOCK DIAGRAM GRID1 GRID2 GRID3 VBB AN1 AN2 AN3 AN25 AN26 AN27 AN28 AN29 AN30 AN31 VREG POR VREG GND VREG GREN METAL MASK ROM VREG STB D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q LE LE LE LE LE LE LE LE LE LE LE LE LE D Q CLK D Q CLK D Q CLK D Q CLK D Q CLK D Q CLK D Q CLK D Q CLK D Q CLK D Q CLK D Q CLK D Q CLK D Q CLK R R R R R R R R R R R R R VREG DIN VREG CLK Output Drive Capability Grid Outputs: 50 mA AN24 – AN29: 20 mA AN1 – AN23, AN30, AN31: 2.0 mA OPERATION DESCRIPTION cause the corresponding output to turn off. Please note that if the STB is held high, the outputs of the latch reflect the outputs of the corresponding shift register bits and will change if data is shifted in. The three GRID outputs are gated by the GREN input. When GREN is low, the GRID outputs are forced low regardless of the state of the corresponding latch output. When GREN is high, the GRID outputs correspond to the state of their respective latch outputs. The anode outputs, AN1 to AN31 are always enabled. Upon the initial application of power, the power on reset function will cause all of the anode and grid driver outputs to be off and all shift register outputs to be set low. Data is fed into the shift register through the DIN pin at the rising edge of the CLK input. Thirty four bits of data are capable of being stored by the shift register. Once the desired pattern is stored in the shift register, it can be transferred to the latch by setting the STB input high. The output of each latch drives its corresponding output stage. A logic high input to the shift register/latch will cause the corresponding output to turn on. A logic low input to the shift register/latch will http://onsemi.com 5 CS1088 APPLICATION INFORMATION Bit # Pin Name Bit # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 G1 G2 G3 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Table 1: Bit Pattern, G = Grid, A = Anode. TYPICAL OPERATION 1 2 3 BIT 1 BIT 2 BIT 3 4 5 6 7 8 9 32 33 34 1 2 3 CLKIN DIN BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 STB ANODES GREN GRIDS * * Selected grid goes high only if input bit pattern from shift register to grid is high. http://onsemi.com 6 BIT 32 BIT 33 BIT 34 BIT 1 BIT 2 BIT 3 CS1088 PIN CONNECTIONS VBB AN31 GREN STB CLK DIN AN30 AN29 AN28 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17 MARKING DIAGRAMS 40 DIP–40 WIDE BODY N SUFFIX CASE 711 XXXXXXXXXXXX AWLYYWW 1 1 XXX... A WL, L YY, Y WW, W GRID1 GRID2 GRID3 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 GND 40 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week PACKAGE DIMENSIONS DIP–40 WIDE BODY N SUFFIX CASE 711–03 ISSUE C 40 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 21 B 1 20 L A C N J H G F D K M SEATING PLANE DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040 PACKAGE THERMAL DATA Parameter DIP–40 WIDE BODY Unit RΘJC Typical 20 °C/W RΘJA Typical 45 °C/W http://onsemi.com 7 CS1088 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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