CXA3001N RX Gain Control Amplifier For the availability of this product, please contact the sales office. Description CXA3001N is an RX gain control amplifier for CDMA cellular mobile phone. 24 pin SSOP (Plastic) Features • Wide gain control range • Linear gain slope • Noise figure Typ. 6dB at Gain = 45dB • Output IP3 Typ. +2dBm at Gain = 40dB • 2 input ports • Power save function included Absolute Maximum Ratings • Supply voltage • Operating temperature • Storage temperature • Allowable power dissipation • Supply voltage range • Logic input voltage • Signal input voltage • Differential signal input voltage Operating Conditions Supply voltage VCC Topr Tstg PD 6 –40 to +85 –65 to +150 420 –0.3 to 6 –0.3 to VCC +0.3 –0.3 to VCC +0.3 0 to 2.5 3.1 to 3.8 V °C °C mW V V V V V Applications • CDMA cellular mobile phone • CDMA & AMPS cellular phone Structure Bipolar sillicon monolithic IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95711-PP CXA3001N Block Diagram IF Input for CDMA CDMAIN CDMAINX SWITCH OUT OUTX IF Output SWITCH IF Input for FM FMIN FMINX Input Select MODE Gain Control GCTL BP1 to External Capacitor BP2 Supply Voltage Ground Power Save VCC1, 2 Bias Driver GND1, 2 CXA3001N PSV –2– CXA3001N Pin Configuration MODE 1 24 PSV 23 GCTL VCC1 2 GND1 3 22 NC NC 4 21 NC CDMAIN 5 20 NC 19 OUTX NC 6 CXA3001N CDMAINX 18 NC 7 17 OUT NC 8 FMIN 9 16 NC 15 VCC2 NC 10 14 GND2 FMINX 11 13 BP2 BP1 12 –3– CXA3001N Pin Description Pin No. Symbol Pin voltage Typ. (V) Equivalent circuit Description VCC1 30k Input select pin. CDMAIN for High. FMIN for Low. 1 1 MODE GND1 2 VCC1 3.6 3 GND1 0 4 6 8 10 N.C. 5 CDMAIN Positive power supply. Ground. No connection. 1.2 2k 7 CDMAINX 2k 1.2 GND1 5 9 FMIN Differential input pins for received CDMA IF signal. 1.2 7 2k 2k Differential input pins for received FM IF signal. GND1 11 FMINX 1.2 9 12 11 VCC2 BP1 Connected to GND with capacitor 0.01µF. 2.4 13 BP2 14 GND2 0 15 VCC2 3.6 16 N.C. 17 OUT 1.7 19 OUTX 1.7 19 17 20k Ground for output stage. Positive power supply for output stage. 20k 13 12 No connection. Differential output pins for received IF signal. GND2 –4– CXA3001N Pin No. 18 20 21 22 Symbol Pin voltage Typ. (V) Equivalent circuit Description N.C. No connection. VCC1 23 GCTL Gain control pin with a ripple filter. 23 GND1 VCC1 24 Power save function pin. High: Active Low: Power save PSV 24 40k GND1 –5– CXA3001N Electrical Characteristics DC characteristics Parameter (VCC = 3.6V, Ta = 25°C) Symbol Conditions Min. Typ. Max. Current consumption 1 ICC1 VGCTL = 1.5V, Pin 2 10 14 19 Current consumption 2 ICC2 VGCTL = 1.5V, Pin 15 4.7 6.6 9.0 Current consumption 3 ICC3 VPSV = 0.5V, Pin 2 1 Current consumption 4 ICC4 VPSV = 0.5V, Pin 15 1 Input current pin 1H IMODE H VMODE = 3V 10 Input current pin 1L IMODE L VMODE = 0.5V Input current pin 23H IGCTL H VGCTL = 3V Input current pin 23L IGCTL L VGCTL = 0.5V Input current pin 24H IPSV H VPSV = 3V Input current pin 24L IPSV L VPSV = 0.5V MODE high voltage VMH Pin 1 MODE low voltage VML Pin 1 PSV high voltage VPSH Pin 24 PSV low voltage VPSL Pin 24 –20 10 –10 3 0.5 3 (VCC = 3.6V, Ta = 25°C) Symbol Conditions Min. Typ. 10 CDMA2.3 GCDMA2.3 VMODE = "H" VGCTL = 2.3V f = 85.38MHz Level = –50dBm Gain CDMA1.5 GCDMA1.5 VMODE = "H" VGCTL = 1.5V Level = –30dBm Gain CDMA0.7 GCDMA0.7 VMODE = "H" VGCTL = 0.7V Level = –10dBm CDMA Gain slope GCLIN VMODE = "H" Gain FM2.3 GFM2.3 Gain FM1.5 Gain FM0.7 Noise Figure V 0.5 Gain Input level 3rd order intercept point µA 10 Operating frequency range FR FM Gain slope mA –10 AC characteristics Parameter Unit Max. Unit 100 MHz 37 41 46 –7.5 –3 1.5 –55 –49 –44 VGCTL = 1 to 2V 57 60 63 VMODE = "L" VGCTL = 2.3V f = 85.38MHz Level = –50dBm 37 41 46 GFM1.5 VMODE = "L" VGCTL = 1.5V Level = –30dBm –7.5 –3 1.5 GFM0.7 VMODE = "L" VGCTL = 0.7V Level = –10dBm –55 –49 –44 GFMLIN VMODE = "L" VGCTL = 1 to 2V 57 60 63 IIP3 VMODE = "H" GCDMA = 40dB∗ F1 = 86.38MHz F2 = 87.38MHz Measure of 85.38MHz –42 –38 NF VMODE = "H" GCDMA = 40dB∗ Used 1MHz BPF Measure of 85.38MHz ∗ Adjust GCTL voltage, and set the overall gain to 40dB. –6– 6.5 dB dB/V dB dB/V dBm 9.5 dB CXA3001N Measurement Circuit V24 V1 A1 1 MODE PSV 24 V2 A24 1k A2 0.01µ 10k 2 VCC1 GCTL 23 3 GND1 NC 22 4 NC NC 21 5 CDMAIN NC 20 V23 A23 0.01µ V5 1:3 10k 1000p CDMA INPUT V19 220 1.2k 6 NC OUTX 19 3:1 1000p 680n OUTPUT 1000p 7 CDMAINX NC 18 V7 220 10k 8 NC 10k 1000p OUT 17 V17 V9 10k 9 FMIN 1:3 NC 16 1000p FM INPUT 0.01µ V15 1.2k 10 NC VCC2 15 A15 680n 1000p 10k GND2 14 11 FMINX V11 0.01µ 0.01µ 12 BP1 BP2 13 V12 V13 1k 1k –7– CXA3001N Application Circuit 1µ VCC 0.1µ CDMA Active FM Sleep 0.01µ 1 24 2 23 3 22 4 21 5 20 6 19 1k Gain Control Voltage 0.01µ 1000p CDMA RX IF INPUT CDMA RX BPF ∗ ∗ CXA3001 7 18 1000p 1000p FM RX IF INPUT FM RX BPF ∗ ∗ 8 17 9 16 10 15 11 14 12 13 1000p 220 220 RX IF BPF 0.01µ 0.01µ 0.01µ ∗ Must be adjusting values to result a best impedance matching between BPF filter and this IC. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –8– RX IF OUTPUT CXA3001N Design Reference Values Single ended measurement Item (VCC = 3.6V, Ta = 25°C) Symbol Input resistance RIN Input capacitance CIN Output resistance ROUT Conditions f = 85.38MHz, VGCTL = 1.5V Typ. Unit 900 Ω 9 pF 30 Ω Notes on Operation 1) This IC is a wideband amplifier with wide gain control range. Separate Pin 3 (GND1) and Pin 14 (GND2) to prevent interference between input and output. Furthermore, the decoupling capacitors between Pins 2 and 3, Pins 14 and 15 should be as close to the IC as possible. 2) The resistors connected to Pins 17 and 19 should be as close to the IC as possible. 3) This IC assumes the excellent characteristics when the differential input impedance between Pins 5 and 7, Pins 9 and 11 is 500Ω. Refer to the Measurement Circuit for the external element settings, etc. 4) Connect the capacitors, which are connected to Pins 12 and 13, to Pin 14 (GND2). 5) Pay attention to handling this IC because its electrostatic discharge strength is weak. –9– CXA3001N Sensitivity VCC = 3.6V 60 40 Power gain [dB] 20 0 –20 –40 T = –40deg T = 25deg T = 85deg –60 0 0.5 1 1.5 2 2.5 3 3.5 VGCTL [V] IIP3 VCC = 3.6V 0 –10 IIP3 [dBm] –20 –30 –40 Ta = –40deg Ta = 25deg Ta = 85deg –50 –60 –60 –40 –20 0 Power gain [dB] – 10 – 20 40 60 CXA3001N Noise Figure VCC = 3.6V 50 Ta = –40deg Ta = 25deg Ta = 85deg Noise figure [dB] 40 30 20 10 0 –60 –40 –20 0 20 60 40 Power gain [dB] Gain Error from Room Temp. VCC = 3.6V 6 Ta = –40deg Ta = 85deg 4 Gain error [dB] 2 0 –2 –4 –6 –60 –40 –20 0 Power gain [dB] – 11 – 20 40 60 CXA3001N Package Outline Unit: mm 24PIN SSOP (PLASTIC) 275mil + 0.2 1.25 – 0.1 ∗7.8 ± 0.1 0.1 ± 0.1 7.6 ± 0.2 5.6 ± 0.1 A 0.5 ± 0.2 0.10 13 24 0° to 10° 1 12 + 0.1 0.22 – 0.05 + 0.05 0.65 ± 0.12 0.15 – 0.02 DETAIL A NOTE : ∗NOT INCLUDE MOLD FINS. PACKAGE STRUCTURE SONY CODE SSOP-24P-L01 EIAJ CODE A SIMILAR TO SSOP024-P-0300 JEDEC CODE PACKAGE MATERIAL EPOXY / PHENOL RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT – 12 –