CXD1261AR Sync Signal, Timing Signal Generator for CCD Cameras Description The CXD1261AR is an IC which generates the sync signals and timing signals required for a camera system that uses the monochrome CCD image sensor (760H) such as the ICX038/039 and ICX058/059. 64 pin LQFP (PIastic) Features • Compatible with monochrome (EIA/CCIR) systems • Built-in electronic shutter function • Built-in driver for the horizontal (H) clock • Built-in SG and TG functions Applications CCD camera systems Structure Silicon gate CMOS Absolute Maximum Ratings (Ta = 25°C, Vss = 0V) • Supply voltage VDD VSS – 0.5 to +7.0 • Input voltage VI Vss – 0.5 to VDD + 0.5 • Output voltage VO Vss – 0.5 to VDD + 0.5 • Operating temperature Topr –20 to +75 • Storage temperature Tstg –55 to +150 V V V °C °C Recommended Operating Conditions • Supply voltage VDD 5.0 ± 0.25 • Operating temperature Topr –20 to +75 V °C Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95735B7Y-PS CXD1261AR SHP SHD TST4 TST5 TST6 TST7 TST8 VSS CLP1 CLP2 CLP3 PBLK CLP4 TST9 HR VDD Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VR/FLD 49 32 VSS HTSG 50 31 XV4 VDD 30 XSG2 51 29 XV3 EXT 52 VSS 53 28 XSG1 TST10 54 27 XV1 TST11 55 26 XV2 VDD 25 XSUB 56 TST12 57 24 VDD TST13 58 23 RG VSS 59 22 VSS TST14 60 21 TST3 TST15 61 20 H2 TST16 62 19 TST2 PS 10 11 12 13 14 15 16 ED2 9 ED1 TST1 8 ED0 D1 7 ENB 6 CKIN 5 OSCO 4 OSCI 3 VSS 2 TRIG 1 D2 17 CL SYNC 64 VD 18 H1 HD CBLK 63 Pin No. PRESET L H D1 4 L EIA CCIR D2 5 L Field readout Frame readout ∗ ENB 12 H Normal Shutter ∗ ED0 13 H ED1 14 H ED2 15 H PS 16 H Serial input Parallel input EXT 52 L Internal External TST1 6 — Normally High TST13 58 — Normally Low Mode name Shutter speed Note) Normally open for TST except as shown in the above table. ∗ During frame accumulation (readout), low-speed shutter does not operate normally. –2– VDD CXD1261AR Pin Description Pin No. Symbol I/O Description 1 HD O Horizontal drive pulse 2 VD O Vertical drive pulse 3 CL O CKIN 2 frequency divided output (EIA: 14.318MHz, CCIR: 14.1875MHz) 4 D1 I 5 D2 I Mode switching; low: EIA; high: CCIR (with pull-down resistor) Mode switching; low: field readout; high: frame readout∗ (with pull-down resistor) 6 TST1 I Test input, fixed to high 7 TRIG I Shutter speed setting pulse (with pull-up resistor) 8 VSS 9 OSCI I Oscillating cell input 10 OSCO O Oscillating cell output 11 CKIN I Clock input (EIA: 28.636MHz, CCIR: 28.375MHz) 12 ENB I Shutter switching; low: normal; high: shutter (with pull-up resistor) 13 ED0 I Shutter speed control (with pull-up resistor) 14 ED1 I Shutter speed control (with pull-up resistor) 15 ED2 I Shutter speed control (with pull-up resistor) 16 PS I Shutter speed setting method switching; low: serial; high: parallel (with pull-up resistor) 17 VDD — Power supply 18 H1 O Horizontal register drive clock 19 TST2 I Test input, normally open (with pull-down resistor) 20 H2 O Horizontal register drive clock 21 TST3 I Test input, normally open (with pull-down resistor) 22 VSS — GND 23 RG O Reset gate pulse 24 VDD — Power supply 25 XSUB O Discharge pulse 26 XV2 O Vertical register drive clock 27 XV1 O Vertical register drive clock 28 XSG1 O Sensor charge readout pulse 29 XV3 O Vertical register drive clock 30 XSG2 O Sensor charge readout pulse 31 XV4 O Vertical register drive clock 32 VSS — GND — GND ∗ The CCD image sensor characteristics are guaranteed for field accumulation operation. –3– CXD1261AR Pin No. Symbol I/O Description 33 SHP O Precharge level sample-and-hold pulse 34 SHD O Data sample-and-hold pulse 35 TST4 O Test output, normally open 36 TST5 O Test output, normally open 37 TST6 O Test output, normally open 38 TST7 O Test output, normally open 39 TST8 O Test output, normally open 40 VSS — GND 41 CLP1 O Clamp pulse 42 CLP2 O Clamp pulse 43 CLP3 O Clamp pulse 44 CLP4 O Clamp pulse 45 PBLK O Blanking cleaning pulse 46 TST9 O Test output, normally open 47 VDD — Power supply 48 HR I H reset pulse 49 VR/FLD I V reset pulse (FLD output when EXT = low) 50 HTSG I HTSG input; low: XSG1, 2 on; high: off (valid only when EXT = low) Fixed to low when EXT = high 51 VDD — 52 EXT I 53 VSS — 54 TST10 I Test input, normally open (with pull-down resistor) 55 TST11 O Test output, normally open 56 VDD — Power supply 57 TST12 O Test output, normally open 58 TST13 I Test input, fixed to low 59 VSS — GND 60 TST14 O Test output, normally open 61 TST15 O Test output, normally open 62 TST16 O Test output, normally open 63 CBLK O Composite blanking pulse 64 SYNC O Composite sync pulse Power supply Sync mode switching; low: internal; high: external sync (with pull-down resistor) GND –4– CXD1261AR Block Diagram CL H Counter 1/910 or 1/908 Decoder 63 CBLK 64 SYNC 1 HD 2 VD Pulse Generator V Counter 1/525 or 1/625 EXT 52 HR 48 VR/FLD 49 HTSG 50 Decoder Reset Generator 45 PBLK 41 CLP1 42 CLP2 43 CLP3 HTSG FLD ENB 12 XSUB 27 XV1 26 XV2 29 XV3 PS 16 31 XV4 ED0 13 28 XSG1 ED1 14 30 XSG2 ED2 15 25 XSUB TRIG 7 OSCI 9 OSCO 10 CKIN Shutter Control 11 CL High-speed Pulse Generator 1/2 CL 3 D1 4 D2 5 Mode Setting –5– 23 RG 18 H1 20 H2 33 SHP 34 SHD CXD1261AR Electrical Characteristics 1) DC characteristics Item Supply voltage Input voltage (VDD = 5V ± 0.25V, Topr = –20 to +75°C) Symbol Conditions Min. Typ. Max. Unit VDD 4.75 5.0 5.25 V VIH1 0.7VDD V VIL1 0.3VDD VOH1 IOH = –2mA VOL1 IOL = 4mA VOH2 IOH = –4mA VOL2 IOL = 8mA VOH3 IOH = –8mA VOL3 IOL = 8mA VOH4 IOH = –2mA VOL4 IOL = 2mA Feedback resistor RFB VIN = VSS or VDD 500K Pull-up resistor RPU VIL = 0V Pull-down resistor RPD VIH = VDD Output voltage 1 ∗1 Output voltage 2 ∗2 Output voltage 3 ∗3 Output voltage 4 ∗4 2) I/O pin capacitance Item VDD – 0.5 V V 0.4 VDD – 0.5 V V 0.4 VDD – 0.5 V V 0.4 VDD/2 V V VDD/2 V 2M 5M Ω 40K 100K 250K Ω 40K 100K 250K Ω (VDD = V1 = 0V, fM = 1MHz) Symbol Min. Typ. Max. Unit Input pin capacitance CIN 9 pF Output pin capacitance COUT 11 pF Input/output pin capacitance CI/O 11 pF Note) ∗1 CLP1, CLP2, CLP3, CLP4, PBLK, CBLK, SYNC, VR, HD, VD, XSUB, XSG1, XSG2, XV1, XV2, XV3, XV4 ∗2 CL, RG, SHP, SHD ∗3 H1, H2 ∗4 OSCO –6– CXD1261AR External Reset Description H Reset (HR) The reset is performed at the first falling edge of the reset pulse that was input; resets are not performed at subsequent edges as long as they do not deviate by two clock pulses (0.14µs) or more. The minimum reset pulse width is 0.35µs. In addition, HD immediately after a reset can not be guaranteed. The position at which the reset is performed is 2.31µs advanced after the H reset input. H reset input 0.35µs or more HD output 2.31µs V Reset (VR) The falling edge of V reset pulse that was input is field identified by the phase difference with the internal signal (field judge pulse) defined by the falling edge of HD. And VD is reset in phase with V reset pulse. When field judge pulse is low and V reset pulse falls, EIA: VD falling edge after 262.5H is the relation between HD and VD of EVEN field. CCIR: VD falling edge after 313.5H is the relation between HD and VD of ODD field. Also, when field judge pulse is high and V reset pulse falls, EIA: VD falling edge after 262.5H is the relation between HD and VD of ODD field. CCIR: VD falling edge after 313.5H is the relation between HD and VD of EVEN field. The minimum reset pulse width is 64µs. 1 2 3 262 (312) 263 (313) 264 (314) HD output Field judge pulse VR input 64µs or more VD timing is genarated after 262.5H with this VR timing VD output (EIA) VD timing is genarated after 313.5H with this VR timing 1HD 1HD VD output (CCIR) Note: For CCIR, VD output is delayed 1HD in relation to VR input. –7– The value without ( ) is for EIA The value in ( ) is for CCIR CXD1261AR Electronic Shutter Description (During frame accumulation, low-speed shutter does not operate normally.) The XSUB pulse timing changes according to the electronic shutter control described below. In addition, the ENB pin controls whether the XSUB pulse is output or not; this control has priority. 1. Continuously variable shutter (trigger mode) • When using the normal shutter, either leave the TRIG pin open or connect it to the power supply. • When using the continuous variable shutter, input the clock pulse to the TRIG pin. VD HD XSG1 TRIG XSUB Shutter speed The shutter speed is determined by sampling the XSUB pulse during the interval between the falling edge of XSG1 and the falling edge of TRIG, and then stopping the XSUB pulse during the interval between the falling edge of TRIG and the next falling edge of XSG1. When using the TRIG pin to control the shutter speed, in order to broaden the control range it is necessary to use the ED0, 1, and 2 pins (described later) to set the shutter speed to 1/10000. 2. Normal shutter 2-1. Switching between parallel input and serial input Parallel input or serial input can be selected as the method for inputting the data used to determine the shutter speed. • Parallel input (PS = High): Permits selection of eight shutter speeds by using three bits ED0, ED1, and ED2. • Serial input (PS = Low): Shutter speed is determined by inputting the strobe to ED0, CLK to ED1, and the data to ED2. –8– CXD1261AR 2-2. When using parallel input (PS = High) Shutter speed table Only the high-speed shutter is used when using parallel input (During frame accumulation, low-speed shutter does not operate normally.) D1 ENB ED0 ED1 ED2 X L X X X L H H H H 1/60 (s) ∗2 H H H H H 1/50 (s) ∗2 L H L H H 1/100 (s) H H L H H 1/120 (s) X H H L H 1/250 (s) X H L L H 1/500 (s) X H H H L 1/1000 (s) X H L H L 1/2000 (s) X H H L L 1/4000 (s) X H L L L 1/10000 (s) Shutter speed Shutter off ∗1 ∗1 XSUB (shutter pulse) is not generated. ∗2 Accumulation time is as follows regardless of field accumulation/frame accumulation. D1 = Low (EIA), 1/60 (s) D2 = High (CCIR), 1/50 (s) (Pseudo field readout during frame accumulation.) 2-3. When using serial input (PS = Low) The following four modes can be selected according to the combination of serial data SMD1 and SMD2. (During frame accumulation, low-speed shutter does not operate normally.) Shutter mode Mode Flickerless High-speed shutter Low-speed shutter No shutter SMD1 L L H H SMD2 L H L H • Flickerless: Eliminates flicker resulting from the frequency of fluorescent light • High-speed shutter: Higher speed shutter than 1/60 (EIA), 1/50 (CCIR) • Low-speed shutter: Lower speed shutter than 1/60 (EIA), 1/50 (CCIR) (Does not operate normally during frame accumulation.) • No shutter: No shutter operation <Input timing when using serial input> ED1 (CLK) ED2 (DATA) D0 D1 D2 D3 D4 D5 D6 D7 D8 SMD1 SMD2 Dummy ED0 (STB) The data on ED2 is latched in the register at the rising edge of ED1 and is then taken in internally while ED0 is low. –9– CXD1261AR ED2 tS2 th2 ED1 tS1 tS0 ED0 tW0 Symbol Min. Max. tS2 ED2 setup time against the rising edge of ED1 20ns — th2 ED2 hold time against the rising edge of ED1 20ns — tS1 ED1 rising setup time against the rising edge of ED0 20ns — tWO ED0 pulse width 20ns 50µs tSO ED0 rising setup time against the rising edge of ED1 20ns — <Shutter speed calculation> (During frame accumulation, low-speed shutter does not operate normally.) High-speed shutter • For EIA ∗ L16: load value T = [26210 – (1FF16 – L16) ] × 63.56 + 34.78µs • For CCIR T = [31210 – (1FF16 – L16) ] × 64 + 35.6µs CCIR EIA Load value Shutter speed 0FA16 1/10000 1/10169 0FC16 1/4000 10016 Calculated value Load value Shutter speed Calculated value 0C816 1/1000 1/10040 1/4435 0CA16 1/4000 1/4394 1/2000 1/2085 0CE16 1/2000 1/2068 10816 1/1000 1/1012 0D616 1/1000 1/1004 11816 1/500 1/499 0E616 1/500 1/495 13716 1/250 1/252 10516 1/250 1/250 17616 1/125 1/125 14316 1/125 1/125 19616 1/100 1/100 14916 1/100 1/120 Low-speed shutter (Does not operate normally during frame accumulation.) FLD N = 2 × (1FF16 – L16) However, 1FF cannot be used as the load value. Load value Shutter speed (FLD) 1FE16 2 1FD16 4 : : 10116 508 10016 510 – 10 – – 11 – FLD CBLK SYNC VD HD FLD CBLK SYNC VD HD EVEN FIELD ODD FIELD Timing Chart (EIA) ODD FIELD EVEN FIELD CXD1261AR – 12 – FLD CBLK SYNC VD HD FLD CBLK SYNC VD HD EVEN FIELD ODD FIELD Timing Chart (CCIR) ODD FIELD EVEN FIELD CXD1261AR CXD1261AR Timing Chart (EIA) 1/2H 0 1H 910 91 HD 21 HSYNC S Y N C 476 511 56 EQ 861 406 VSYNC 154 CBLK VD FLD Unit: clock pulses Timing Chart (CCIR) 1/2H 0 1H 908 91 HD 21 HSYNC S Y N C 475 510 56 EQ 859 405 VSYNC 167 CBLK VD FLD Unit: clock pulses – 13 – FRAME FIELD – 14 – CLP4 CLP3 CLP2 CLP1 PBLK XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 XSG2 XSG1 HD CBLK/VD FLD Timing Chart (EIA vertical direction) ODD Field CXD1261AR – 15 – FRAME FIELD CLP4 CLP3 CLP2 CLP1 PBLK XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 XSG2 XSG1 HD CBLK/VD FLD Timing Chart (EIA vertical direction) EVEN Field CXD1261AR FRAME FIELD – 16 – CLP4 CLP3 CLP2 CLP1 PBLK XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 XSG2 XSG1 HD CBLK/VD FLD Timing Chart (CCIR vertical direction) ODD Field CXD1261AR FRAME FIELD – 17 – CLP4 CLP3 CLP2 CLP1 PBLK XV4 XV3 XV2 XV1 XV4 XV3 XV2 XV1 XSG2 XSG1 HD CBLK/VD FLD Timing Chart (CCIR vertical direction) EVEN Field CXD1261AR – 18 – PBLK CLP4 CLP3 CLP2 CLP1 XSUB XV4 XV3 XV2 XV1 SHD SHP RG H2 H1 CL CK HD The black-pointed sections of the H1 clock indicate the optical black. Timing Chart (EIA horizontal direction) CXD1261AR – 19 – PBLK CLP4 CLP3 CLP2 CLP1 XSUB XV4 XV3 XV2 XV1 SHD SHP RG H2 H1 CL CK HD The black-pointed sections of the H1 clock indicate the optical black. Timing Chart (CCIR horizontal direction) CXD1261AR FRAME READOUT FIELD READOUT – 20 – XV4 XV3 XV2 EVEN XV1 XV4 XV3 XV2 ODD XV1 XSG2 XSG1 XV4 XV3 XV2 EVEN XV1 XV4 XV3 XV2 ODD XV1 HD Readout Timing Chart (EIA) 578 22 3 3 36 36 33 36 3 36 36 36 Unit: clock pulses (1ck = 69.84ns) CXD1261AR FRAME READOUT FIELD READOUT – 21 – XV4 XV3 XV2 EVEN XV1 XV4 XV3 XV2 ODD XV1 XSG2 XSG1 XV4 XV3 XV2 EVEN XV1 XV4 XV3 XV2 ODD XV1 HD Readout Timing Chart (CCIR) 589 22 3 3 36 36 33 36 3 36 36 36 Unit: clock pulses (1ck = 70.48ns) CXD1261AR CXD1261AR Timing Chart (High-speed phase) CKIN CL H1 H2 RG SHP SHD Application Circuit Signal processing 33 32 CCD image sensor V Driver 48 49 CXD1261AR 64 1 17 16 Shutter control OSC EIA : 28.6363MHz CCIR : 28.375MHz ∗ Use a crystal that operates with a fundamental wave. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 22 – CXD1261AR Package Outline Unit: mm 64PIN LQFP (PLASTIC) 12.0 ± 0.2 ∗ 10.0 ± 0.1 48 33 32 64 17 (0.22) 0.5 ± 0.2 (11.0) 49 A 1 0.5 + 0.08 0.18 – 0.03 16 0.13 M + 0.2 1.5 – 0.1 + 0.05 0.127 – 0.02 0.1 0° to 10° 0.5 ± 0.2 0.1 ± 0.1 NOTE: Dimension “∗” does not include mold protrusion. DETAIL A PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE LQFP-64P-L01 LEAD TREATMENT SOLDER/PALLADIUM PLATING EIAJ CODE LQFP064-P-1010 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.3g JEDEC CODE – 23 –