SONY CXD2306

CXD2306Q
10-bit 80MSPS 1ch D/A Converter
For the availability of this product, please contact the sales office.
Description
The CXD2306Q is a 1-ch 10-bit 80MSPS D/A
converter for fine monitor and video, and is ideal for
high definition TVs and high resolution displays.
Features
• 10-bit resolution
• Maximum conversion rate
80MSPS
• Differential linearity error
±0.5 LSB
• Low power consumption
150 mW(max.)
(When 80MSPS 200 Ω load, 2 Vp-p is output)
• Single 5 V power supply
• Built-in independent constant-voltage source
• Stand-by function
Structure
Silicon gate CMOS IC
32 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
AVDD, DVDD
7
V
• Input voltage (All pins)
VIN
VDD + 0.5 to VSS – 0.5 V
• Output voltage
IOUT
0 to 15
mA
• Storage temperature
Tstg
–55 to +150
Recommended Operating Conditions
• Supply voltage
AVDD, AVSS 5.0 ± 0.25
DVDD, DVSS 5.0 ± 0.25
• Reference input voltage
VREF
0.5 to 2.0
• Clock pulse width
tPW1, tPW0
5.6 (min.)
• Operating temperature
topr
–20 to +85
°C
V
V
V
ns
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E92X12D01
CXD2306Q
Block Diagram and Pin Configuration
(LSB) D0 30
4LSB'S
CURRENT
CELLS
D1 31
D2 32
D3
1
D4
2
D5 3
25 AVSS
LACHES
DECODER
23 IO
6MSB'S
CURRENT
CELLS
D6 4
D7
5
D8 6
(MSB) D9
24 IO
22 VG
DECODER
7
19 VREF
DVDD 28
CURRENT CELLS
(FOR FULL SCALE)
BLK 10
17 IREF
DVDD 13
DVSS 15
DVSS 27
CLK
21 AVDD
CLOCK
GENERATOR
BIAS VOLTAGE
GENERATOR
9
BAND GAP
REFERENCE
20 AVDD
VB 14
18 SREF
CE 11
IO
IO
VG
AVDD
AVDD
VREF
SREF
IREF
Pin Configuration
24
23
22
21
20
19
18
17
16 NC
AVss 25
15 DVss
NC 26
DVss 27
14 VB
DVDD 28
13 DVDD
NC 29
12 NC
D0 (LSB) 30
11 CE
2
3
4
5
6
7
8
D8
D9 (MSB)
NC
D3
1
D7
9 CLK
D6
D2 32
D5
10 BLK
D4
D1 31
27 to
15
Digital section
17 to
25
Analog section
—2—
CXD2306Q
Pin Description and Equivalent Circuit
Pin No.
Symbol
I/O
Equivalent circuit
Description
DVDD
30 to 32
1 to 7
30
D0 to D9
I
Digital input.
30 pin D0 (LSB) to 7 pin D9 (MSB)
to
7
DVSS
8, 12,16, 26, 29
NC
9
CLK
—
NC pin
Clock input
Blanking input.
This is synchronized with the clock
input signal.
No signal (0 V output) at high and
output state at low.
Chip enable input.
This is not synchronized with the clock
input signal.
No signal (0 V output) at high makes
power consumption minimum.
Digital power supply
DVDD
10
BLK
I
9
10
11
DVSS
11
CE
13, 28
DVDD
—
DVDD
DVDD
14
VB
Connect a capacitor of approximately
0.1 µF.
O
14
DVSS
15, 27
17
DVSS
IREF
—
Digital ground
AVDD
O
AVDD
AVDD
17
AVDD
AVSS
19
VREF
I
22
VG
Reference voltage input.
Sets output full scale value.
19
AVSS
Reference current output.
Connect resistance “RIR” which is 16
times output resistance “R”.
22
O
AVSS
—3—
Connect a capacitor of approximately
0.1 µF.
CXD2306Q
Pin No.
Symbol
I/O
Equivalent circuit
Description
AVDD
Independent constant-voltage source
output pin using band gap reference.
Stable voltage independent of the
fluctuation for supply voltage can be
get by connecting to VREF. See
Application Circuit 2 for details.
18
18
SREF
O
AVSS
AVSS
20, 21
AVDD
—
Analog power supply
AVDD
23
IO
AVSS
AVDD
O
24
Inverted current output.
Connect to GND normally.
24
Current output. Output can be
retrieved by connecting resistance.
The standard is 200 Ω.
23
IO
AVSS
25
AVSS
—
Analog ground
Description of Operation
Timing Chart
I/O Correspondence Table
(When 2.00 V output full-scale voltage)
tPW1 tPW0
1.5V
CLK
ts th
ts th
MSB
LSB
1 1 1 1 1 1 1 1 1 1
:
1 0 0 0 0 0 0 0 0 0
:
0 0 0 0 0 0 0 0 0 0
ts th
DATA
tPD
100%
50%
D/A OUT
tPD
Input code
tPD
0%
—4—
Output
voltage
2.0 V
1.0 V
0V
CXD2306Q
(FCLK=80 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, VREF=2.0 V, RIR=3.3 kΩ, Ta=25 °C)
Electrical Characteristics
Resolution
Item
Symbol
n
Conversion speed
FCLK
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to +85 °C
Integral non-linearity error
Differential non-linearity error
Precision guaranteed
output voltage range
Output full-scale voltage
Output full-scale current
Output offset voltage
Glitch energy
Differential gain
Differential phase
EL
ED
Endpoint
Supply current
Analog input resistance
Input capacitance
Output capacitance
Digital input voltage
Digital input current
SREF output voltage
Setup time
Hold time
Propagation delay time
CE enable time ∗1
CE disable time ∗1
Measurement conditions
Max.
Unit
bit
0
80
MSPS
–2.0
–0.5
2.0
0.5
LSB
LSB
1.8
1.92
2.0
V
VFS
IFS
VOS
GE
DG
DP
IDD
ISTB
RIN
CI
Co
VIH
VIL
IIH
IIL
VSR
ts
th
tPD
tE
tD
1.8
9.0
1.92
9.6
2.0
10
1
V
mA
mV
pV•s
%
deg
When D0 to D9= “0000000000” input
ROUT=100 Ω, 1 Vp-p output
CE=L
CE=H
VREF
50
2.5
1.3
30
1
mA
9
MΩ
pF
pF
1
IO
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to +75 °C
AVDD=DVDD=4.75 to 5.25 V
Ta=–20 to +75 °C
50
2.15
0.85
CE=H→L
CE=L→H
Measurement Circuit
+5.25V
AVDD, DVDD
A
CXD2306Q
V
AVSS, DVSS
—5—
V
–5
5
µA
1.0
5.0
1.0
1.3
V
ns
ns
ns
ms
ms
10
1
1
Electrical Characteristics Measurement Circuit
}
Typ.
10
VOC
∗1 When the external capacitor for the VG pin is 0.1 µF.
Analog Input Resistance
Digital Input Current
Min.
2
2
CXD2306Q
Maximum Conversion Rate Measurement Circuit
10bit
COUNTER
with
LATCH
30 D0 (LSB)
•
31 •
•
•
•
•
IO 24
OSCILLOSCOPE
0.1µ
7 D9 (MSB)
AVDD
200
VG 22
2V
9 CLK
5k
VREF 19
10 BLK
CLK
80MHz (max)
SQUARE
WAVE
AVss
11 CE
IREF 17
14 VB
3.3k
0.1µ
DC Characteristics Measurement Circuit
CONTROLLER
30 D0 (LSB)
•
31 •
•
•
•
•
IO 24
0.1µ
7 D9 (MSB)
AVDD
VG 22
2V
9 CLK
5k
VREF 19
10 BLK
CLK
80MHz
SQUARE
WAVE
DVM
200
AVss
11 CE
IREF 17
14 VB
3.3k
0.1µ
Propagation Delay Time Measurement Circuit
30 D0 (LSB)
•
31 •
•
•
•
•
9 CLK
10 BLK
CLK
10MHz
SQUARE
WAVE
Setup Time
Hold Time
Glitch Energy
VG 22
VREF 19
2V
5k
IREF 17
14 VB
3.3k
0.1µ
}
AVDD
200
AVss
11 CE
Measurement Circuit
10bit
COUNTER
with
LATCH
•
•
•
30 D0 (LSB)
•
31 •
•
IO 24
7 D9 (MSB)
VG 22
9 CLK
DELAY
CONTROLLER
CLK
1MHz
SQUARE
WAVE
0.1µ
7 D9 (MSB)
FREQUENCY
DEMULTIPLIER
OSCILLOSCOPE
IO 24
10 BLK
11 CE
DELAY
CONTROLLER
14 VB
0.1µ
VREF 19
2V
AVDD
5k
AVss
IREF 17
3.3k
0.1µ
—6—
200
OSCILLOSCOPE
CXD2306Q
Application Circuit 1
R3
AVDD
DVDD
AVSS
DVSS
R4
C
R1
R2
C
24
23
22
21
IO
IO
VG
AVDD
20
19
18
AVDD VREF SREF
17
IREF
25 AVss
NC 16
26 NC
DVss 15
27 DVss
VB 14
C
28 DVDD
DVDD 13
C
29 NC
NC 12
30 D0
CE 11
31 D1
BLK 10
D3
D4
D5
D6
D7
D8
D9
CLK 9
NC
1
2
3
4
5
6
7
8
32 D2
Clock input
• When 5.0V supply voltage (DVDD and AVDD)
• Digital input from Pins 30 to 32 and Pins 1 to 7
• Pin 18 is left open when using normally
• R1 = 200Ω
• R2 = 3.3kΩ (RIR)
• R3 = 3.0kΩ
• R4 = 2.0kΩ
• C = 0.1µF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—7—
CXD2306Q
Application Circuit 2
C
R1
AVDD
DVDD
AVSS
DVSS
R2
C
24
23
22
21
20
IO
IO
VG
AVDD
AVDD
19
18
VREF SREF
17
IREF
25 AVss
NC 16
26 NC
DVss 15
27 DVss
VB 14
C
28 DVDD
DVDD 13
C
29 NC
NC 12
30 D0
CE 11
31 D1
BLK 10
32 D2
D3
D4
D5
D6
D7
D8
D9
1
2
3
4
5
6
7
CLK 9
NC
Clock input
8
• When 5.0V supply voltage (DVDD and AVDD)
• Digital input from Pins 30 to 32 and Pins 1 to 7
• R1 = 200Ω
• R2 = 2.0kΩ
• C = 0.1µF
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
—8—
CXD2306Q
Notes on Operation
• Selecting the Output Resistance
CXD2306Q is a current output type D/A converter. To create the output voltage, connect the resistor to the
current output pin IO.
Specifications:
Output full-scale voltage VFS = 1.8 to 2.0 [V]
Output full-scale current IFS = 10 or less [mA]
Calculate the output resistance from V FS = IFS × ROUT. Connect a resistance sixteen times the output
resistance to the reference current pin IREF. In some cases, as this value may not exist, a similar value can
be used instead.
Note that the VFS will be the following.
VFS = VREF × 16 ROUT/RIR
VREF is the voltage set at the VREF pin, ROUT is the resistor to be connected to the current output pin IO and
RIR is the resistor to be connected to the IREF. Power consumption can be reduced by increasing the
resistance, but this will on the contrary increase the glitch energy and data settling time. Set the best values
according to the purpose of use.
• Correlation between Data and Clock
For CXD2306Q to display the desired performance as a D/A converter, the data transmitted from outside and
the clock must be synchronized properly. Adjust the setup time (ts) and hold time (th) as specified in
“Electrical Characteristics”.
• Power supply and ground
Separate the analog and digital signals around the device to reduce noise effects. Bypass the power supply
pin to each ground with a 0.1 µF ceramics capacitor as near as possible to the pin for both the digital and
analog signals.
• Latch up
Analog and digital power supply must be able to share the same power supply of the board. This is to
prevent latch up caused by potential difference between the two pins when the power is turned on.
• SREF
The SREF is an independent regulated voltage source. By connecting it to the VREF, stable output
amplitudes that do not depend on fluctuations in the power supply can be obtained.
In this case, as VFS = VSR × 16ROUT/RIR, set the VFS according to RIR. Where VSR is the output voltage of
SREF. Do not use this pin as the reference power supply for other IC because this pin is for the exclusive
use of the CXD2306Q.
• IO pin
The IO pin is the inverted current output pin described in the Pin Description. The sum of the currents output
from the IO pin and the IO pin becomes the constant value for any input data.
However, the performances such as the linearity error of the IO pin output current is not guaranteed.
—9—
CXD2306Q
Latch Up Prevention
The CXD2306Q is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in
the voltage rising time of AVDD (Pin 20 and 21) and DVDD (Pin 11 and 28), when power supply is ON.
1. Correct usage
a. When analog and digital supplies are from different sources
DVDD
AVDD
+5V
+5V
20 21
13 28
AVDD
DVDD
C
C
DIGITAL IC
CXD2306Q
AVSS
DVSS
15
25
27
AVSS
DVSS
b. When analog and digital supplies are from a common source
(i)
DVDD
20 21
13 28
AVDD
DVDD
C
+5V
C
DIGITAL IC
CXD2306Q
AVSS
25
DVSS
15 27
AVSS
DVSS
(ii)
DVDD
20
21
13
AVDD
28
DVDD
C
+5V
C
DIGITAL IC
CXD2306Q
AVSS
AVSS
25
DVSS
15
27
DVSS
—10—
CXD2306Q
2. Example when latch up easily occurs
a. When analog and digital supplies are from different sources
DVDD
AVDD
+5V
+5V
20 21
13 28
AVDD
DVDD
C
C
CXD2306Q
AVSS
DVSS
15
25
AVSS
DIGITAL IC
27
DVSS
b. When analog and digital supplies are from common source
(i)
DVDD
AVDD
20
21
13
AVDD
28
DVDD
+5V
C
CXD2306Q
C
AVSS
DVSS
15
25
AVSS
DIGITAL IC
27
DVSS
(ii)
DVDD
AVDD
20 21
13
AVDD
28
DVDD
+5V
C
CXD2306Q
AVSS
AVSS
25
DVSS
15
27
DVSS
—11—
DIGITAL IC
2.0
Glitch energy GE [pV•s]
Output full-scale voltage VFS [V]
CXD2306Q
1.0
100
50
RIR ≈16ROUT
0
1.0
0
2.0
100
200
Output resistance ROUT [Ω]
Fig. 2. Glitch energy vs. Output resistance
1.90
30
Supply current IDD [mA]
Output full-scale voltage [V]
Reference voltage VREF [V]
Fig. 1. Reference voltage vs. Output full-scale voltage
1.85
20
∆V = 0.26mV/°C
0
–25
0
25
50
0
75
SREF output voltage VSR [V]
Ambient temperature Ta [°C]
Fig. 3. Ambient temperature vs. Output full-scale voltage
1
10
20
30
40
Output frequency FO [MHz]
Fig. 4. Output frequency vs. Supply current
Standard masurement conditions and description
• AVDD=DVDD=5V
• VREF=2.0V
• ROUT=200Ω
• RIR=3.3kΩ
• Ta=25°C
• Input data in Fig. 4=all 0, rectangular wave
of all 1, clock freq.=80MHz.
1.14
1.10
∆V = 0.34mV/°C
0
–25
0
25
50
75
Ambient temperature Ta [°C]
Fig. 5. Ambient temperature vs. SREF output voltage
—12—
CXD2306Q
Package Outline
Unit : mm
32PIN QFP (PLASTIC)
9.0 ± 0.2
24
0.1
+ 0.35
1.5 – 0.15
+ 0.3
7.0 – 0.1
17
16
32
9
(8.0)
25
1
+ 0.2
0.1 – 0.1
0.8
+ 0.15
0.3 – 0.1
0.24
M
+ 0.1
0.127 – 0.05
0° to 10°
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-32P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
QFP032-P-0707
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
—13—
0.50
8