CXL1008M/P CMOS-CCD Signal Processor for Skew Compensation Description CXL1008M/P are CMOS-CCD signal processors developed for the variable-speed video signal processor for home-use 8mm VCRs. CXL1008M 28 pin SOP (Plastic) CXL1008P 28 pin DIP (Plastic) Features • Low power consumption 105mW (Typ.) • Built-in peripheral circuit • Adjustment is necessary for one part. Structure CMOS-CCD Functions • 1/2H 359-bit, direct 20-bit CCD register • Clock driver • Timing oscillation circuit • Automatic bias circuit • Sync tip clamp circuit • Dummy VD insert circuit • Sample/hold circuit Absolute Maximum Ratings (Ta = 25°C) • Supply voltage VDD 11 V VCL 6 V • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipaiton PD CXL1008M 500 mW CXL1008P 1000 mW Recommended Operating Conditions Supply voltage VDD 9V ± 5 VCL 5V ± 5 % % Recommended Clock Conditions • Clock input amplitude VCLK 0.15 to 1.0 (0.3 Typ.) • Clock frequency fCLK 10.738635 Vp-p MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E60248-PS FEED OUT FEED IN 13 24 25 23 AUTOBIAS CIRCUIT SIG IN2 SIG OUT CCD OUT AUTO Block Diagram SIG DELAY CXL1008M/P 21 12 19 1/2H OUTPUT CIRCUIT SIG IN1 11 D 50mV T10 28 50mV REFERENCE T9 27 SKEW IN 26 φ1 φ2 DRIVER 2 DUTY CONTROL TIMING GENERATOR 20 VSS VDD 7 22 8 T6 18 14 REC/PB 1 VCL 6 VSS 5 T5 4 T4 3 T3 T2 10 MUTE IN OUTPUT CONTROL CLK IN T1 SKEW Pin Configuration (Top View) T8 15 14 VCL EXT VD 16 13 AUTO JOG IN 17 12 SIG IN2 VSS 18 11 SIG IN1 SIG OUT 19 10 MUTE IN 9 T7 SIG DELAY 21 8 T6 REC/PB 22 7 CLK IN VDD 20 CCD OUT 23 6 T5 FEED OUT 24 5 T4 FEED IN 25 4 T3 SKEW IN 26 3 T2 T9 27 2 T1 T10 28 1 VSS –2– 17 JOG IN 16 EXT VD 15 T8 9 T7 CXL1008M/P Pin Description Pin No. Symbol I/O Supply voltage Description Impedance (Ω) 1 VSS GND 7 CLK IN I 0.3Vp-p 10 MUTE IN I The video signal mute is generated at High level. 5V when See the Logic Table of Signal Output Selection muting, normally 0V State (Table 1). > 100k 11 SIG IN1 I 1.1Vp-p or less Signal input pin of CCD DL. Input composite video signal. > 100k 12 SIG IN2 I 2.2Vp-p or less Signal input pin of the through side. Input composite video signal. > 100k 13 AUTO O The DC level of automatic bias is output. 10k 14 VCL 16 EXT VD +5V Input the sine wave of 3fsc (10.738635MHz) > 50k Power supply 1 I 5V when VD Use this pin when VD is inserted to the video signal is inserted with the extrenal dummy VD signal input. > 100k I JOG mode 5V PB/REC mode 0V > 100k JOG/NORMAL PB selection pin. See the Logic Table of Signal Output Selection State (Table 1). 17 JOG IN 18 VSS 19 SIG OUT 20 VDD 21 SIG DELAY I 22 REC/PB I 23 CCD OUT O Direct output from CCD DL 0.6 to 1.5k 24 FEED OUT O Feedback DC output 10k 25 FEED IN I Smoothing capacitor connection pin of the bias commutation loop on the output circuit > 100k I Select Direct DL and 1/2H DL signals when High and Low, respectively. See the Logic Table of CCD DL Mode Selection (Table 2). > 100k 26 SKEW IN GND O Final output +9V 0.6 to 1.5k Power supply 2 After the output from Pin 23 CCD OUT passes through LPF, input it to the same pin and insert clamp and VD. 5V when PB Operate the clock at High when PB. 0V when REC Stop the clock at Low when REC. > 100k > 100k Note) T1 through T10 test pins must be connected as shown in the application circuit because of the IC internal circuit. Notes on Handling Countermeasures for electrostatics are necessary because some pins have low electrostatic strength (particularly Pin 26: SKEW IN). –3– –4– a a a a c b Vdi3 Vdo1 Vdo2 Differential gain g g L H L c b b a 2.2Vp-p input DGDL L c b b 0 0 0 b 2.2Vp-p input DGIn2 g H 1.1Vp-p input DGCCD c –0.5 a L H –0.5 b L L L c L L H H← → L –0.2 b b b← →d b a L –3 b b b b← →d b b H b b← →c a b b b← →c a c H H← → L –1.3 –1.2 –1.2 –3.0 –55 1.5 1.7 4.0 4.0 4.0 0.15 Min. Direct ← → 1/2H at 3.58MHz c 10MHz/100kHz fDL Frequency characteristics ∆fab difference 10MHz/100kHz 3.58MHz/100kHz fCCD a H L a b L L a b a a f H a a L L H H← →L L L P5 a L H H H H H 5 P1 P2 P3 P4 Control Pin Conditions ∗1, ∗2 a 4 b b a IGDL f a e e e e e e a a 3 c b b IGIn2 Direct ← → 1/2H b c IGCCD ∆Gab a c ∆Dab a b a c Vdi2 a c a 2 1 Switch Conditions c Direct ← → 1/2H PB, JOG Test Conditions 2 2 3 0 0 0 –2 0 –0.8 –0.8 0 0 2.0 2.0 4.2 4.2 5.0 0.3 8 7 Typ. 4 4 10 0.2 — — 0 1.3 0 0 3.0 55 2.5 2.4 4.4 4.4 6.0 1.0 10 12 Max. % % % dB dB dB dB % dB dB dB mV V V V V V V mA mA Unit 10 10 10 9 8 8 7 6 5 5 5 4 3 3 2 2 2 1 1 Note (Ta = 25°C, VDD = 9.0V, VCL = 5.0V, fCLK = 10.7MHz, VCLK = 0.3Vp-p sine wave) Vdi1 CLK ICL IDD Symbol Frequency characteristics fIn2 CCD output signal gain difference Signal insert gain CCD signal output voltage difference Signal output pin voltage Signal input pin voltage Clock input level Power current Items Electrical Characteristics (See the Electrical Characteristics Test Circuit) CXL1008M/P –5– a S/NDL c a L H 0 50 — b H VIN L g L 4.0 a L d b f← →e b 50 d b f← →e b H — 0 50 L H 0 0 d L L P5 b a← →e a L L L b L c b L c a H 5 P1 P2 P3 P4 4 — g g g g 3 Min. g b b b 2 Control Pin Conditions ∗1, ∗2 VIN H a b S/NIn2 2Vp-p video signal from sync tip c S/NCCD VVD a/b a VIN2–AC 2.2Vp-p input DPDL b c 2.2Vp-p input DPIn2 c 1 Switch Conditions VIN1–AC 1.1Vp-p input Test Conditions DPCCD Symbol ∗1 Control pins correspond to P1 through P5 of the Electrical Characteristics Test Circuit. ∗2 Symbols "H" and "L" in control pin conditions represent "VIN H" and "VIN L" of logical input. Logical input VD insert depth S/N rate Allowable input amplitude Differential phase Items 50 65 65 55 — — 3 3 3 Typ. 1.0 — 100 — — — 2.2 1.1 5 5 5 Max. V V mV dB dB dB Vp-p Vp-p deg deg deg Unit 12 11 11 11 10 10 10 Note CXL1008M/P 5V 1 28 [dB] –6– 3 26 4 25 22µ 5 6 10k 23 5V 100k 24 220k CLK 7 22 P4 0 –50 0 –3 5.8 Frequency [MHz] 10.7 0.1µ 9 20 A2 V2 P1 10 19 9V 11 18 12 17 P3 2SA1175 2k a b 9V 10µ 13 16 4.1M 10.7M Frequency [Hz] 0 50 200 –50 0 –3 A1 14 5V 5V SW5 15 390k P2 SW4 Note 2) BPF Frequency Response 8 21 2SA1175 Note 1) LPF Frequency Response (Delay Time to 140ns) 2 27 P5 10µ V3 2k [dB] Electrical Characteristics Test Circuit a b c 0.1µ 0.1µ a 1M SW2 SW1 d c b a SW3 Note 2) BPF LPF 0.1µ VBIAS b 20k V1 ×1 ×1 Note 1) 100kHz 300mVp-p SINE WAVE 100kHz 1.1Vp-p SINE WAVE NOISE METER VECTOR SCOPE 100kHz 2.2Vp-p SINE WAVE 5-STAIR CASE WAVE g GROUND 10MHz 300mVp-p SINE WAVE f e d c 3.58MHz 300mVp-p SINE WAVE b a ×1 ×1 SPECTRUM ANALYZER OSCILLOSCOPE CXL1008M/P CXL1008M/P Notes) 1) Current value when the clock is in operation in the PB or JOG mode. In the REC mode, the clock is stopped (Pin 22 is at low) to save power. 2) With the signal input pin voltage value, the video signal sync tip is clamped. 3) Vdo1 is a CCD OUT output voltage when the SIG IN1 input voltage is Vdi1. Vdo2 is a SIG OUT output voltage when the SIG IN2 input voltage is Vdi2. Vdo1 and Vdo2 represent outputs for the sync tip clamp level when a white level signal is input as shown in the diagram. Output signal Vdo 40% 100% 1.0Vp-p Vdi Input signal 4) ∆Dab denotes an output voltage difference of CCD OUT when the direct DL and 1/2H DL are switched. 5) IGCCD is a CCD OUT gain when a 1.1Vp-p 100kHz sine wave is input to SIG IN1. IGCCD = 20 log Output amplitude (Vp-p) 1.1Vp-p It is measured by giving a Vdi1 + 0.6 bias with VBias. IGin2 and IGDL are SIG OUT gains when 2.2Vp-p 100kHz sine wave is input to each of SIG IN2 and SIG DELAY pins. IGin2 = 20 log Output amplitude (Vp-p) 2.2Vp-p It is measured by giving a Vdi2 + 1.1V bias with VBias. –7– CXL1008M/P 6) ∆Gab is a gain difference between the direct DL and 1/2H DL. 7) It represents a loss at 3.58MHz compared with 100kHz. It is measured by raising the SIG IN1 input pin by 0.6V higher than the sync tip clamp level (Vdi1) with VBias. 3.85MHz 300mVp-p sine wave 100kHz 300mVp-p sine wave VBias = Vdi1 + 0.6V SIG IN1 DC FCCD = 20 log V3.58MHz output V100kHz output 8) It represents a loss at 10MHz compared with 100kHz. It is measured by raising the SIG IN2 or SIG DELAY input pin by 1.1V higher than the sync tip clamp level (Vdi2 or Vdi3) with VBias. 9) ∆Fab is a frequency response difference between the direct DL and 1/2H DL. 10) Chroma 40 IRE 140 IRE 1.1Vp-p at DGCCD 2.2Vp-p at DGin2 or DGDL 40 IRE 1H 63.5µs DG is measured with a vectorscope in each mode of the 5-stage waves. 11) Measure S/N of the BPF 100kHz to 4.2MHz in the subcarrier trap mode with a video noise meter. 12) SIG DELAY Input waveform EXT VD input SIG OUT Output waveform 2Vp-p VVD Set a voltage value at VVD when inserting EXT VD to the 2Vp-p signal output waveform sync tip of SIG OUT. –8– CXL1008M/P CLOCK 3fsc (10.738635MHz) Sine wave 0.15 to 1.0Vp-p Function Outline Output signal selection SIG IN2 (PB) SIG DELAY (JOG) SIG OUT 50mV REF The video output signal is selected by selecting the output switch for three signals: Pin 10 (MUTE IN), Pin 17 (JOG IN) and Pin 16 (EXT VD). Table 1. Logic Table of Signal Output Selection State Input control signal state Video signal output selection state JOG IN MUTE IN EXT VD PB JOG VD insert MUTE 0 0 0 O × × × 0 0 1 O × × × 0 1 0 × × × O 0 1 1 × × × O 1 0 0 × O × × 1 0 1 × × O × 1 1 0 × × × O 1 1 1 × × O O Note 1) Figures "0" and "1" of the input control signal state are equivalent to "Low" and "High" of logic. Note 2) Items marked with the symbol "O" in the video signal output selection state are selected. Note 3) PB = JOG IN · MUTE IN JOG = JOG IN · MUTE IN · EXT VD VD insert = JOG IN · EXT VD MUTE = MUTE IN –9– CXL1008M/P CCD selection Table 2. Logic Table of CCD DL Mode Selection 1/2H (359bit) SIG IN1 Control signal CCD OUT D (20bit) CCD DL mode SKEW IN D 1/2H 0 × O 1 O × SKEW IN Application Circuit 390 2.2k 4.7k 390 8.2k 9V 1.8k 1k 1.5k 120 10µH 560 220 10µ 10k 220k SIGNAL OUTPUT 10µ 18k 220p 270p 2k 0.022µ REC/PB 10µ SKEW IN 22µ 1000p 47µ JOG EXT IN VD 1M 10k 220k 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 2M 100k 2M 16 15 13 14 10µ 47µ 1000p 5V 0.01µF 3fsc 0.3Vp-p SINE WAVE MUTE IN 0.047µ 0.047µ Transistor to be used PNP: 2SA1175 510 510 SIGNAL INPUT Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Frequency characteristics (Ta = 25°C) Gain [dB] 0 –1 –2 10k 100k f – Frequency [Hz] – 10 – 1M CXL1008M/P Supply voltage (VCL) vs. Insert gain (IGCCD) Supply voltage (VCL) vs. Frequency characteristics (fCCD) 1 fCCD – Frequency characteristics [dB] 2 IGCCD – Insert gain [dB] 1 0 –1 –2 –3 4.75 5.00 VCL – Supply voltage [V] 0 –1 –2 –3 –4 4.75 5.25 Supply voltage (VCL) vs. Differential gain (DGCCD) Vdo1 – Output pin voltage [V] DGCCD – Differential gain [%] 2.5 4 3 2 1 5.00 VCL – Supply voltage [V] 2.0 1.5 4.75 5.25 Supply voltage (VDD) vs. Insert gain (IGCCD) 5.25 fCCD – Frequency characteristics [dB] 1 1 IGCCD – Insert gain [dB] 5.00 VCL – Supply voltage [V] Supply voltage (VDD) vs. Frequency characteristics (fCCD) 2 0 –1 –2 –3 8.5 5.25 Supply voltage (VCL) vs. Output pin voltage (Vdo1) 5 0 4.75 5.00 VCL – Supply voltage [V] 9.0 VDD – Supply voltage [V] 0 –1 –2 –3 –4 8.5 9.5 – 11 – 9.0 VDD – Supply voltage [V] 9.5 CXL1008M/P Supply voltage (VDD) vs. Differential gain (DGCCD) Supply voltage (VDD) vs. Output pin voltage (Vdo1) 2.5 Vdo1 – Output pin voltage [V] DGCCD – Differential gain [%] 5 4 3 2 1 0 8.5 9.0 VDD – Supply voltage [V] 2.0 1.5 8.5 9.5 Ambient temperature (Ta) vs. Insert gain (IGCCD) Ambient temperature (Ta) vs. Frequency characteristics (fCCD) 1 fCCD – Frequency characteristics [dB] IGCCD – Insert gain [dB] 2 1 0 –1 –2 –3 0 –1 –2 –3 –4 0 20 40 60 Ta – Ambient temperature [°C] Ambient temperature (Ta) vs. Differential gain (DGCCD) 2.5 Vdo1 – Output pin voltage [V] DGCCD – Differential gain [%] 0 20 40 60 Ta – Ambient temperature [°C] Ambient temperature (Ta) vs. Output pin voltage (Vdo1) 5 4 3 2 1 0 9.0 VDD – Supply voltage [V] 2.0 1.5 0 20 40 60 Ta – Ambient temperature [°C] – 12 – 0 20 40 60 Ta – Ambient temperature [°C] 9.5 CXL1008M/P Package Outline Unit: mm CXL1008M 28PIN SOP (PLASTIC) + 0.4 18.8 – 0.1 + 0.4 2.3 – 0.15 28 15 1 14 0.45 ± 0.1 0.5 ± 0.2 9.3 10.3 ± 0.4 + 0.3 7.6 – 0.1 0.15 + 0.2 0.1 – 0.05 + 0.1 0.15 – 0.05 1.27 M 0.24 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SOP-28P-L02 LEAD TREATMENT SOLDER PLATING EIAJ CODE SOP028-P-0375 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.6g JEDEC CODE CXL1008P + 0.1 0.05 0.25 – 28PIN DIP (PLASTIC) + 0.4 37.8 – 0.1 15.24 15 1 + 0.3 13.0 – 0.1 28 0° to 15° 14 0.5 ± 0.1 1.2 ± 0.15 Two kinds of package surface: 1.All mat surface type. 2.Center part is mirror surface. + 0.4 4.6 – 0.1 3.0 MIN 0.5 MIN 2.54 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-28P-03 LEAD TREATMENT SOLDER PLATING EIAJ CODE DIP028-P-0600 LEAD MATERIAL COPPER ALLOY PACKAGE MASS 4.2g JEDEC CODE – 13 –