CXP861P16 CMOS 8-bit Single-chip Microcomputer For the availability of this product, please contact the sales office. Description The CXP861P16 is a highly integrated CMOS 8-bit single-chip microcomputer which is mainly composed of an 8-bit CPU, PROM, RAM and I/O ports. This microcomputer features many other highperformance circuits in a single-chip CMOS design, including an A/D converter, clock synchronized serial interface, UART, stepping motor controller, PWM generator, 16-bit timer/counter, and watchdog timer. Also, the CXP861P16 provides the power-on reset function as well as the sleep/stop function which enables to lower power consumption. This IC is the PROM-incorporated version of the CXP86116 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for smallquantity production. 80 pin QFP (PIastic) Structure Silicon gate CMOS IC Features • Instruction set which supports a wide array of data types 213 types — 16-bit arithmetic instruction/multiplication and division instructions/boolean bit operation • Minimum instruction cycle During operation 400ns/instruction 10MHz • Incorporated PROM capacity 16K bytes • Incorporated RAM capacity 576 bytes • Peripheral functions — A/D converter 8-bit, 8-channel, successive comparison type (conversion time: 32µs at 10MHz) — Serial interface Universal Asynchronous Receiver Transmitter (baud-rate generator incorporated) 8-bit clock synchronized type — Stepping motor controller 2-channel stepping motor excitation output — PWM output 2-channel 12-bit output — Timer 2-channel 16-bit capture timer/counter 2-channel 16-bit timer/counter (step rate generation function incorporated) 19-bit time-base timer — Watchdog timer • Interrupts 17 factors, 15 vectors, multiple interrupt processing • Standby mode SLEEP/STOP • Package 80-pin plastic QFP Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E95308-ST AVSS AVREF AVDD 16BIT TIMER/COUNTER 0 16BIT TIMER/COUNTER 1 16BIT TIMER/COUNTER 2 16BIT TIMER/COUNTER 3 12BIT PWM GENERATOR 0 12BIT PWM GENERATOR 1 PI2/EC1 PI3/CINT1 PG5/TO1 PG2/EC2 PG3/EC3 PH2/PWM0 PH3/PWM1 SERIAL INTERFACE UNIT PI0/EC0 PI1/CINT0 PG4/TO0 PH5/S0 PH6/S1 PH4/SCK UART BAUD RATE GENERATOR PG2/INT2 WATCHDOG TIMER PROM 16K BYTES SPC700 CPU CORE STEPPING STEPPING MOTOR MOTOR CONTROLLER CONTROLLER CH-Y CH-X PE0/Xa UART TRANSMITTER PG3/INT3 INTERRUPT CONTROLLER PE1/Xb PH1/TxD NMI PE2/Xc UART RECEIVER PE3/Xd 2 4 2 PORT G 8 PORT H 4 PORT I PRESCALER/ TIME BASE TIMER RAM 576 BYTES CLOCK GENERATOR/ SYSTEM CONTROL EXTAL PI0 to PI3 PH0/RxD PE4/Ya XTAL RST MP PH0 to PH7 A/D CONVERTER PE6/Yc 8 PE5/Yb VDD Vss PG6, PG7 PF0/AN0 to PF7/AN7 PE7/Yd Vpp PG0, PG1 PG2 to PG5 PB0 to PB7 8 8 PF0 to PF3 PF4 to PF7 4 PE0 to PE7 8 4 PD0 to PD7 8 PC0 to PC7 PA0 to PA7 8 PORT A PORT B PORT C PORT D PORT E –2– PORT F Block Diagram CXP861P16 PI3/INT1 PI1/INT0 CXP861P16 PE5/Yb PE4/Ya PE3/Xd PE2/Xc PE1/Xb PE0/Xa NMI VDD Vss Vpp PA7 PA6 PA5 PA4 PA3 PA2 Pin Configuration (Top View) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PA1 1 64 PE6/Yc PA0 2 63 PE7/Yd PB7 3 62 PG0 PB6 4 61 PG1 PB5 5 60 PG2/EC2/INT2 PB4 6 59 PG3/EC3/INT3 PB3 7 58 PG4/TO0 PB2 8 57 PG5/TO1 PB1 9 56 PG6 PB0 10 55 PG7 PC7 11 54 PI0/EC0 PC6 12 53 PI1/CINT0/INT0 PC5 13 52 PI2/EC1 PC4 14 51 PI3/CINT1/INT1 PC3 15 50 PF0/AN0 PC2 16 49 PF1/AN1 PC1 17 48 PF2/AN2 PC0 18 47 PF3/AN3 PD7 19 46 PF4/AN4 PD6 20 45 PF5/AN5 PD5 21 44 PF6/AN6 PD4 22 43 PF7/AN7 PD3 23 42 AVDD PD2 24 41 AVREF AVSS PH0/RxD PH1/TxD PH2/PWM0 EXTAL PH3/PWM1 XTAL VSS MP RST PH4/SCK PH5/SO PH7 PH6/SI PD0 PD1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Note) 1. Vpp (Pin 74) is always connected to VDD. 2. Vss (Pins 33 and 73) are both connected to GND. 3. MP (Pin 31) is always connected to VSS. –3– CXP861P16 Pin Description Symbol I/O Description PA0 to PA7 Output (Port A) 8-bit output port. 12mA sink current can be driven. (8 pins) PB0 to PB7 Output (Port B) 8-bit output port. (8 pins) PC0 to PC7 I/O (Port C) 8-bit I/O port. Enable to specify input/output by 4-bit unit. (8 pins) PD0 to PD7 I/O (Port D) 8-bit I/O port. Enable to specify input/output by 4-bit unit. (8 pins) PE0/Xa to PE3/Xd I/O/output PE4/Ya to PE7/Yd I/O/output PF0/AN0 to PF3/AN3 Input/input PF4/AN4 to PF7/AN7 Output/input PG0 PG1 I/O PG2/EC2/INT2 PG3/EC3/INT3 I/O/input/input PG4/TO0 PG5/TO1 I/O/output PG6 PG7 Output PH0/RxD I/O/input Input for UART reception data. PH1/TxD I/O/output Output for UART transmission data. PH2/PWM0 I/O/output PH3/PWM1 I/O/output PH4/SCK I/O/I/O PH5/SO I/O/output PH6/SI I/O/input PH7 I/O (Port E) 8-bit I/O port. I/O can be selected in a unit of 4 bits. (8 pins) (Port F) Input port for the lower 4 bits; output port for the upper 4 bits. (8 pins) (Port G) I/O port for the lower 6 bits; output port for the upper 2 bits. Enable to specify input/output by bit unit. (8 pins) (Port H) 8-bit I/O port. Enable to specify input/output by bit unit. (8 pins) Output for stepping motor control circuit CH-X. (4 pins) Output for stepping motor control circuit CH-Y. (4 pins) Analog input to A/D converter. (8 pins) External event input for timer/counter 2 and 3. Output for capture and timer/counter. (2 pins) PWM output. (2 pins) I/O for serial clock. Output for serial data. Input for serial data. –4– Input for external interrupt request. CXP861P16 Symbol I/O Description PI0/EC0 PI1/CINT0 / INT0 External event input for timer/counter 0. Input/input/input PI2/EC1 Capture input for timer/counter 0. (Port I) 4-bit input port. (4 pins) Input for external interruption request. External event input for timer/counter 1. Capture input for timer/counter 1. PI3/CINT1/ INT1 Input for external interruption request. NMI Input Non-maskable interruption request for active at falling edge. EXTAL Input XTAL Output Crystal connection for system clock oscillation. Input the clock to EXTAL pin and at the same time input the clock with reversed phase to XTAL pin when clock is input externally. RST I/O System reset for active at low level. RST pin becomes I/O pin, and outputs low level at the power on with power-on reset function executed. (mask option) MP Input Always connect to VSS. Positive power supply for A/D converter. AVDD AVREF Input Reference supply voltage input for A/D converter. AVss GND for A/D converter. VDD Positive power supply. Vpp Positive power supply for built-in PROM writing. Connect to VDD for normal operation. Vss GND. Connect both of Vss to GND. –5– CXP861P16 I/O Circuit Formats for Pins Pin Circuit format Port A PA0 to PA7 Port B AAAA AAAA AA AA Port A or Port B data PB0 to PB7 Hi-Z control 16 pins AAAAA AAAAA AAAAA AAAAA Port C data Port C I/O direction IP Data bus RD (Port C) Data bus Input protection circuit Hi-Z TTL level input 8 pins RD AAAAA AAAAA AAAAA AAAAA Port D Port D data PD0 to PD5 Hi-Z High current 12mA (only for port A) AA AA AA Port C PC0 to PC7 When reset Port D I/O direction Data bus AA AA AA Hi-Z IP RD (Port D) 6 pins Port D AAAA AAAA AAAA Port D data PD6 PD7 Port D I/O direction Data bus RD (Port D) 2 pins –6– AA AA AA IP Hi-Z CXP861P16 Pin Circuit format When reset Port E PE0/Xa PE1/Xb PE2/Xc PE3/Xd PE4/Ya PE5/Yb PE6/Yc PE7/Yd AA AAAAA AA AAAAA AA AAAAA AA AA AA AA Port E/ excitation output selection Stepping motor excitation output MPX Port E data Port E I/O direction IP Data bus 8 pins Hi-Z RD (Port E) Port F AAAA AA Input multiplexer A/D converter IP PF0/AN0 to PF3/AN3 Hi-Z Data bus RD (Port F) 4 pins AAAA AAAA AAAA AAAA Port F Port F data PF4/AN4 to PF7/AN7 Data bus RD (Port F) Port F selection A/D converter 4 pins Hi-Z IP Input multiplexer Port G AAAA AAAA AAAA Port G data PG0 PG1 Port G I/O direction Data bus 2 pins AA AA AA RD (Port G) –7– AA AA AA IP Hi-Z CXP861P16 Pin Circuit format When reset AAAAA AAAAA AAAAA Port G AA AA AA Port G data PG2/EC2/INT2 PG3/EC3/INT3 Port G I/O direction IP Data bus 2 pins RD (Port G) To timer/counter 2, 3 To interruption circuit Port G Schmitt input AA AAAAA AA AAAAA AA AAAAA AA AA AA AA Port G/ timer output selection From timer/counter 0, 1 PG4/TO0 PG5/TO1 MPX Port G data Port G I/O direction H level IP Data bus AAAA AA AAAA AA 2 pins Hi-Z RD (Port G) Port G Port G data PG6 PG7 Hi-Z Data bus 2 pins RD (Port G) AAAAA AAAAA AAAAA Port H Port H data PH0/RxD PH6/SI Port H I/O direction IP Data bus 2 pins AA AA AA RD (Port H) To UART To serial interface Schmitt input –8– Hi-Z CXP861P16 Pin Circuit format Port H When reset AA AAAAA AA AAAAA AA AAAAA AA AA AA AA Port H/ each output selection From UART, PWM serial interface PH1/TxD PH2/PWM0 PH3/PWM1 PH5/SO MPX Port H data Port H I/O direction IP Data bus RD (Port H) 4 pins Port H AA AAAAA AA AAAAA AA AAAAA AA AA AA AA SCK output enable From serial interface PH4/SCK Hi-Z MPX Port H data Port H I/O direction Hi-Z IP Data bus RD (Port H) Schmitt input To serial interface 1 pin Port H AAAA AAAA AAAA Port H data PH7 Port H I/O direction Data bus RD (Port H) 1 pin –9– AA AA AA IP Hi-Z CXP861P16 Pin Circuit format Port I PI0/EC0 PI1/CINT0/INT0 PI2/EC1 PI3/CINT1/INT1 Schmitt input 2 pins To timer/counter 0, 1 To interruption circuit IP 4 pins EXTAL XTAL AAAA AA When reset RD (Port I) AA A AA AA AA AA AA AA AA AA A AAA EXTAL Hi-Z Data bus • Diagram shows the circuit configuration during oscillation. IP • Feedback resistor is removed during stop. Oscillation XTAL Pull-up resistor RST Mask option Schmitt input OP L level IP 1 pin MP IP 1 pin – 10 – From power-on reset circuit (mask option) CPU mode Hi-Z CXP861P16 Absolute Maximum Ratings Item Power supply voltage (Vss = 0V) Symbol Rating Unit VDD –0.3 to +7.0 V Vpp –0.3 to +13.0 AVSS to +7.0∗1 V V AVDD AVSS Remarks Incorporated PROM V Input voltage VIN –0.3 to +0.3 –0.3 to +7.0∗2 Output voltage VOUT –0.3 to +7.0∗2 V High level output current IOH –5 mA High level total output current ∑IOH –50 mA Total output pins IOL 15 mA IOLC 20 mA Other than high current output pins: per pin High current port pin∗3: per pin Low level total output current ∑IOL 130 mA Total output pins Operating temperature Topr –10 to +75 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD 600 mW Low level output current V Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI. ∗1 AVDD and VDD should be set to a same voltage. ∗2 VIN and VOUT should not exceed VDD + 0.3V. ∗3 The high current operation transistors are the N-CH transistors of the PA port. – 11 – CXP861P16 Recommended Operating Conditions Item Power supply voltage Symbol VDD Min. Max. 4.5 5.5 3.5 5.5 2.5 5.5 Vpp Analog power supply High level input voltage Low level input voltage Operating temperature (Vss = 0V) Vpp = VDD Unit Remarks Guaranteed range during high speed mode (1/2 dividing clock) operation V Guaranteed range during low speed mode (1/16 dividing clock) operation V Guaranteed data hold operation range during STOP ∗6 4.5 5.5 V ∗1 VIH 0.7VDD VDD V ∗2 VIHS 0.8VDD VDD V VIHT 2.0 VDD V VIHEX VDD – 0.4 VDD + 0.3 V VIL 0 0.3VDD V VILS 0 0.2VDD V VILT 0 0.8 V CMOS schmitt input∗3 TTL input∗4 VILEX –0.3 0.4 V EXTAL pin∗5 Topr –10 +75 °C AVDD CMOS schmitt input∗3 TTL input∗4 EXTAL pin∗5 ∗2 ∗1 AVDD and VDD should be set to a same voltage. ∗2 Normal input port (each pin of PD, PE, PF0 to PF3, PG0, PG1, PG4, PG5, PH1 to PH3, PH5, PH7), MP pin. ∗3 Each pin of NMI, PH6/SI, PH4/SCK, PH0/RxD, RST, PI0/EC0, PI1/CINT0/INT0, PI2/EC1, PI3/CINT1/INT1, PG2/EC2/INT2, PG3/EC3/INT3. ∗4 Each pin of PC. ∗5 It specifies only when the external clock is input. ∗6 Vpp and VDD should be set to the same voltage. – 12 – CXP861P16 Electrical Characteristics DC Characteristics Item High level output voltage Low level output voltage (Ta = –10 to +75°C, Vss = 0V) Symbol Pin VOH PA to PE, PF4 to PH7 PG, PH RST (VOL only) VOL PA IIHE Input current I/O leakage current EXTAL IILE Min. VDD = 4.5V, IOH = –0.5mA 4.0 V VDD = 4.5V, IOH = –1.2mA 3.5 V Unit V VDD = 4.5V, IOL = 3.6mA 0.6 V VDD = 4.5V, IOL = 12.0mA 1.5 V VDD = 5.5V, VIH = 5.5V 0.5 40 µA VDD = 5.5V, VIL = 0.4V –0.5 –40 µA –1.5 –400 µA ±10 µA 20 45 mA 0.8 5 mA 30 µA 20 pF VDD = 5.5V, VIL = 0.4V IIZ PA to PI, MP VDD = 5.5V V1 = 0, 5.5V Crystal oscillation (C1 = C2 = 12pF) of 12MHz VDD = 5V ± 0.5V∗2 VDD Max. 0.4 RST IDDS1 Typ. VDD = 4.5V, IOL = 1.8mA IILR IDD Supply current∗1 Condition SLEEP mode VDD = 5V ± 0.5V STOP mode IDDS2 VDD = 5V ± 0.5V Input capacity CIN Other than VDD, VSS, AVDD, AVSS pins Clock 1MHz 0V other than the measured pins 10 ∗1 When entire output pins are open. ∗2 When setting upper 2 bits (CPU clock selection) of clock control register CLC (address: 00FEH) to "00" and operating in high speed mode (1/2 dividing clock). – 13 – CXP861P16 AC Characteristics (1) Clock timing (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Symbol System clock frequency fC System clock input pulse width tXL, tXH tCR, tCF tEH, tEL tER, tEF System clock input rising and falling times Event clock input pulse width Event count clock input rising and falling times Pin Condition Min. Max. Unit 10 MHz XTAL EXTAL Fig. 1, Fig. 2 1 EXTAL Fig. 1, Fig. 2 (External clock drive) 40 EXTAL Fig. 1, Fig. 2 (External clock drive) ns 200 2tsys∗ EC0, EC1 Fig. 3 EC2, EC3 EC0, EC1 Fig. 3 EC2, EC3 ns ns 20 ms ∗ tsys indicates three values according to the contents of the clock control register (address; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2-bit = "00"), 4000/fc (Upper 2-bit = "01"), 16000/fc (Upper 2-bit = "11") Fig. 1. Clock timing 1/fc VDD – 0.4V EXTAL 0.4V tXH tCF Fig. 2. Clock applying condition AAAA AAAA AAAA C1 tCR AAAA AAAA AAAA Crystal oscillation Ceramic oscillation EXTAL tXL External clock EXTAL XTAL C2 XTAL 74HC04 Fig. 3. Event count clock timing EC0 EC1 EC2 EC3 0.8VDD 0.2VDD tEH tEF – 14 – tEL tER CXP861P16 (2) Serial transfer Item SCK cycle time (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol tKCY Pin Condition Min. ns 16000/fc ns 400 ns 8000/fc – 50 ns SCK1 input mode 100 ns SCK1 output mode 200 ns SCK1 input mode 200 ns SCK1 output mode 100 ns Output mode SCK high and low level widths tKH tKL SCK SI input setup time (against SCK ↑) tSIK SI SI input hold time (against SCK ↑) tKSI SCK ↓ → SO delay time tKSO Input mode Output mode SI SO SCK1 input mode 200 ns SCK1 output mode 100 ns Note) The load of SCK1 outptut mode and SO1 output delay time is 50pF + 1TTL. Fig. 4. Serial transfer timing tKCY tKL tKH 0.8VDD SCK1 0.2VDD tKSI tSIK 0.8VDD Input data SI1 Unit 1000 Input mode SCK Max. 0.2VDD tKSO 0.8VDD SO1 Output data 0.2VDD – 15 – CXP861P16 (3) A/D converter characteristics (Ta = –10 to +75°C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVSS = 0V) Item Symbol Pin Condition Min. Typ. Resolution Ta = 25°C VDD = AVDD = 5.0V VSS = AVSS = 0V Absolute error Conversion time Sampling time Reference input voltage VREF AVREF Analog input voltage AN0 to AN7 IREF AVREF current IREFS Unit 8 Bits ±3 160/fADC∗ 12/fADC∗ tCONV tSAMP VIAN Max. Operating mode AVREF µs µs AVDD – 0.5 AVDD V 0 AVREF V 1.0 mA 10 µA 0.6 SLEEP mode STOP mode ∗ The value of fADC is as follows by selecting ADC operation clock (MSC: Address 01FFH bit 0). When PS2 is selected, fADC = fc/2 When PS1 is selected, fADC = fc – 16 – LSB CXP861P16 (4) Interruption, reset input Item (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Symbol Pin External interruption high and low level widths tIH tIL INT0 INT1 INT2 INT3 NMI Reset input low level width tRSL RST Min. Typ. Max. Unit 1 µs 8/fc µs Fig. 5. Interruption input timing INT0 INT1 INT2 INT3 NMI (Falling edge) tIH tIL 0.8VDD 0.2VDD Fig. 6. Reset input timing tRSL RST 0.2VDD (5) Power on reset (Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V) Item Power supply rising time Power supply cut-off time Symbol Pin tR tOFF VDD Condition Power on reset Repetitive power on reset Min. Max. Unit 0.05 50 ms 1 ms Fig. 7. Power on reset 4.5V VDD 0.2V 0.2V tR tOFF The power supply should be rise smoothly. – 17 – CXP861P16 Supplement Fig. 8. Recommended oscillation circuit AAAA AAAA AAAA EXTAL EXTAL XTAL Rd C1 AAAA AAAA AAAA (ii) (i) XTAL Rd C2 C1 C2 Manufacturer Model CSA8.00MTZ CST8.00MTW∗ MURATA MFG CO., LTD. CSA10.0MTZ CST10.0MTW∗ C1 (pF) C2 (pF) Rd (Ω) 8.00 30 30 0 Circuit example 10.00 30 30 0 (i) (ii) 12 12 470 (i) 22 22 0 (i) 10.00 HC-49/U (-S) 8.00 10.00 Those marked with an asterisk (∗) signify types with built-in ground capacitance. (C1, C2) Mask option table Item (i) (ii) 8.00 RIVER ELETEC HC-49/U03 CO., LTD. KINSEKI LTD. fc (MHz) Mask product CXP861P16Q-1- Reset pin pull-up resistor Non-existent/Existent Existent Power on reset circuit Non-existent/Existent Existent – 18 – CXP861P16 Package Outline Unit: mm 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 20.0 – 0.1 64 0.15 41 65 16.3 17.9 ± 0.4 + 0.4 14.0 – 0.1 40 A + 0.2 0.1 – 0.05 25 1 24 0.8 0.12 M + 0.15 0.35 – 0.1 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE SONY CODE QFP-80P-L01 EIAJ CODE ∗QFP080-P-1420-A JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.6g – 19 – 0.8 ± 0.2 80