CY244/45ZXC Factory Programmable Quad PLL Clock Generator with VCXO Features Benefits • Fully integrated phase-locked loops (PLLs) • Meets most Digital Set Top Box, DVD Recorder and DTV application requirements • Selectable Output Frequency • Multiple high-performance PLLs allow synthesis of unrelated frequencies • Programmable Output Frequencies • Output Frequency Range of 5–166 MHz • Integration eliminates the need for external loop filter components • Input Frequency Range — Crystal: 10–30 MHz • Meets critical timing requirements in complex system designs — External Reference: 1–100 MHz • Analog VCXO • Enables application compatibility • 16-/20-pin TSSOP packages • Complete VCXO solution with ±120 ppm (minimum pull range) • 3.3V operation Block Diagram CLKA CLKB PLL1 CLKC XIN XOUT VCXO PLL2 CLKD Divider & Multiplexer VIN CLKE PLL3 CLKF PLL4 CLKG FS0/1/2 OE Select Logic Pin Configuration 20-Pin TSSOP 16-Pin TSSOP XIN 1 20 XOUT FS2 2 19 VDD AVDD 3 18 CLKG CLKG VIN 4 17 CLKF CLKF AVSS 5 VSS OE/PD XIN 1 16 XOUT AVDD 2 15 VDD VIN AVSS CLKA/OE VSS CLKB FS1 3 14 4 13 CY244ZXC 5 12 6 7 8 11 10 9 VDD FS0 CLKC Cypress Semiconductor Corporation Document #: 38-07748 Rev. ** • 3901 North First Street • 16 CY245ZXC 6 15 VSS CLKE CLKA 7 14 VSS 8 13 VDD CLKB 9 12 FS0 FS1 10 11 CLKC CLKD San Jose, CA 95134 • 408-943-2600 Revised March 7, 2005 CY244/45ZXC Pin Description Pin Number Pin Name 16-pin TSSOP 20-pin TSSOP 1 1 XOUT 16 20 Crystal Output (No connect if external clock is used) CLKA 5[1] 7 Clock Output XIN Pin Description Crystal Input or Reference Clock Input CLKB 7 9 Clock Output CLKC 9 11 Clock Output CLKD N/A 14 Clock Output CLKE N/A 15 Clock Output CLKF 13 17 Clock Output CLKG 14 18 Clock Output FS0 10 12 Frequency Select 0 FS1 8 10 Frequency Select 1 FS2 N/A 2 Frequency Select 2 OE/PD 5[1] 6 Output Enable Control/Power Down VIN 3 4 VDD 11,15 13,19 VSS Analog Control Input for VCXO Voltage Supply 6,12 8,16 AVDD 2 3 Analog Voltage Supply Ground AVSS 4 5 Analog Ground General Description The CY24xZXC family of devices has an Analog VCXO (Voltage Controlled Crystal Oscillator), 4 PLLs, up to 7 clock outputs, and frequency selection capabilities. The frequency selects do not modify any PLL frequency. Instead, they allow the user to choose between up to 8 different output divider selections depending on the clock and package configuration. This is illustrated in Frequency Selection tables 1 and 2. There is one programmable OE/PDWN. The OE/PDWN pin can be programmed as either an output enable pin or a power down pin. The OE function can be programmed to disable a selected set of outputs when low, leaving the remaining outputs running. Full chip power-down will disable all outputs as well as the PLLs and most of the active circuitry when low. Factory-Programmable CY24xZXC Factory programming is available for high or low volume manufacturing by Cypress. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. Please refer to the CY223388/89/91 data sheet for up to 8 clock outputs and compatibility with most SMD type crystals. PLLs The advantage of having 4 PLLs is that a single device can generate up to 4 independent frequencies from a single crystal. Generally a design may require up to 4 oscillators to accomplish what could be done with a single CY24xZXC. Each PLL is independent and can be configured to generate a VCO (Voltage Controlled Oscillator) frequency between 62.5 MHz and 250 MHz. Each PLL can then in turn be divided down with post dividers to generate the clock output frequency of the user’s choice. The output divider allows each clock output to be divided by 1,2,3,4,6,8,9,10,12,15. The PLL maximum is reduced to 166 MHz in divide by 1 mode due to output buffer limitations. Outputs that allow frequency switching perform the transition free of glitches. A glitch is defined as a high or low time shorter than half the smaller of the two periods being switched between. Extended low time (even many cycles in duration) is acceptable. Please refer to Figure 5. In order to minimize PPM (Parts Per Million) error on the clock outputs, a user should try and choose a crystal reference frequency that is a common multiple of the desired PLL frequencies. While this would be the ideal situation, this is not always the case and the PLLs have high resolution counters internally to help minimize frequency deviation from the desired frequency. PLL VCO frequencies are generated by the following equation: FVCO = FREF * (P / Q) Where FREF is the reference input frequency, P is the PLL feedback divider and Q is the reference input divider. A PLL is a feedback system where the VCO frequency divided by P and reference frequency divided by Q are constantly being compared and the VCO frequency is adjusted to achieve a locked state. Figure 1 is a simplified drawing of a PLL. Note: 1. Pin 5 16-pin TSSOP (choice between clock output or OE/PD) Document #: 38-07748 Rev. ** Page 2 of 9 CY244/45ZXC FR E F /Q F V CO V C O a nd O t her c o m pon ent s /P Figure 1. Simplified PLL Frequency Select Pin Operation Table 1. CY244ZXC 16-pin TSSOP Frequency Selection Lines Output Signal CLOCK B & CLOCK C FS1 FS0 CLOCK A & CLOCK F FS0 CLOCK G FIXED One of the key components to the CY24xZXC family of devices is the analog VCXO. The VCXO is used to “pull” the reference crystal higher or lower in order to lock the system frequency to an external source. This is ideal for applications where the output frequency needs to track along with an external reference frequency that is constantly shifting. The VCXO is completely analog, so there is infinite resolution on the VCXO pull curve. The Analog to Digital Converter steps that are normally associated with a digital VCXO input are not present in this device. A special pullable crystal must be used in order to have adequate VCXO pull range. Pullable Crystal specifications are included in this data sheet. Please contact the local Cypress Field Application Engineer (FAE) or sales representative for pullable crystal recommendations outside of the standard industry frequencies given in the Pullable Crystal Specifications. VCXO Profile Table 2. CY245ZXC 20-pin TSSOP Output Signal The third mode disables the VCXO input control and sets the internal oscillator to a fixed frequency operation. The load capacitance seen by the external crystal when connected to pins XIN and XOUT is typically equal to 10pF. Frequency Selection Lines CLOCK C FS2 FS1 FS0 CLOCK B & CLOCK D FS1 FS0 Figure 2 shows an example of what a VCXO profile looks like. The analog voltage input is on the X-axis and the PPM range is on the Y-axis. An increase in the VCXO input voltage results in a corresponding increase in the output frequency. This has the effect of moving the PPM from a negative to positive offset. CLOCK A, CLOCK E, & CLOCK F FS0 CLOCK G 200 FIXED 150 There are three programmable reference operating modes for the CY24xZXC family of devices. The first mode utilizes an external pullable crystal and incorporates an internal Analog VCXO. The second mode configures the internal crystal oscillator to accept an external driven reference source from 1 to 100 MHz. The input capacitance on the XIN pin when driven in this mode is typically 15pF. Document #: 38-07748 Rev. ** 100 Tuning [ppm Analog VCXO 50 0 -50 0 0.5 1 1.5 2 2.5 3 3.5 -100 -150 -200 VCXO input [V] Figure 2. VCXO Profile Page 3 of 9 CY244/45ZXC Absolute Maximum Conditions Parameter Description Condition Min. VDD/AVDD/VDDL Core Supply Voltage Max. Unit –0.5 4.6 V –0.5 VDD + 0.5 VDC Non-Functional –65 +125 °C MIL-STD-883, Method 3015 2000 – Volts – 10 ppm VIN Input Voltage Relative to VSS TS Temperature, Storage ESDHBM ESD Protection (Human Body Model) UL-94 Flammability Rating V-0 @1/8 in. MSL Moisture Sensitivity Level 16 and 20 pin TSSOP 1 Pullable Crystal Specifications[2, 4] Parameter Description Comments Min. Typ. Max. Unit FNOM 10 to 30 MHz Crystal AT-Cut CLNOM Nominal load capacitance CLNOM =14 pF (0 ppm) 13.5 14 14.5 pF R1 Equivalent series resistance (ESR) Fundamental mode (CL = Series) – – 25 Ω DL Crystal drive level No external series resistor assumed – – 500 µW C0[3] Crystal shunt capacitance – – 7 pF C1[3] Crystal motional capacitance 14.4 18 21.6 fF F3SEPHI[4] Third overtone separation from 3*FNOM Mechanical Third (High side of 3*FNOM) 380 – – ppm F3SEPLO[4] Third overtone separation from 3*FNOM Mechanical Third (Low side of 3*FNOM) – – –170 ppm C0/C1 Ratio of shunt to motional capacitance – – 250 Parallel resonance, Fundamental mode See Note 4 Recommended Operating Conditions Parameter Description VDD/AVDD/VDDL Operating Voltage TA Ambient Temperature CLOAD Maximum Load Capacitance tPU Power-up time for all VDDs reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. Unit 3.0 3.3 3.6 V 0 – 70 °C – – 15 pF 0.05 – 500 ms Typ. Max. Unit DC Parameters Parameter Description Conditions Min. [5] Output High Current VOH = VDD – 0.5, VDD = 3.3V – 12 – mA IOL[5] Output Low Current VOL = 0.5, VDD = 3.3V – 12 – mA IOH IIH Input High Current VIH = VDD, excluding Vin, Xin – 5 10 µA IIL Input Low Current VIL = 0V, excluding Vin, Xin – 5 10 µA VIH Input High Voltage FS0/1/2 OE input CMOS levels 0.7xAVDD – – V VIL Input Low Voltage FS0/1/2 OE input CMOS levels – – 0.3xAVDD V VVCXO VIN Input Range 0 – AVDD V CIN Input Capacitance – – 7 pF IVDD Supply Current VDD/AVDD/VDDL Current – 85 – mA CINXIN Input Capacitance at XIN VCXO Disabled External Reference – 15 – pF Crystal Load Crystal Load Capacitance VCXO Disabled Fixed Freq. Crystal – 10 – pF FS0/1/2 and OE Pins only Notes: 2. Device operates to the following specs, which are guaranteed by design. 3. Increased tolerance available from pull range less than ±120 ppm. 4. ECX-5953 Series crystal orderable from Ecliptek Corporation. Please refer to the CY22388/89/91 data sheet for compatibility with most SMD type crystals. 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs. Document #: 38-07748 Rev. ** Page 4 of 9 CY244/45ZXC AC Parameters Parameter[4] Description Conditions Min. Typ. Max. Units 1/t1 Output Frequency PLL minmax/Dividermaximum 4.2 – 166 MHz DC1[6] Output Duty Cycle Duty Cycle is defined in Figure 3; t2/t1, 50% of VDD 45 50 55 % Duty Cycle is defined in Figure 3; t2/t1, 50% of VDD 40 50 60 % External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is ≤ 125MHz) DC2 Output Duty Cycle External reference duty cycle between 40% and 60% measured at VDD/2 (Clock output is > 125MHz) DCREFOUT Reference Output Duty Cycle Duty Cycle is defined in Figure 3; t2/t1, 50% of VDD (XIN Duty Cycle = 45/55%) 40 50 60 % ER Rising Edge Rate Output Clock Edge Rate. Measured from 20% to 80% of VDD. CLOAD = 15 pF. See Figure 4. 0.8 1.2 – V/ns EF Falling Edge Rate Output Clock Edge Rate. Measured from 80% to 20% of VDD. CLOAD = 15pF See Figure 4. 0.8 1.2 – V/ns T9[7] Clock Jitter Period Jitter – ±250 – ps T10 PLL Lock Time – 1 5 ms f∆XO VCXO Crystal Pull Range – – ppm Using Crystal specified in “Pullable Crystal Specifications” table. ±120 Nominal Crystal Frequency Input assumed (0ppm)@25°C and 3.3V Test and Measurement Set-up V DDs Outputs DUT 0.1µF C LOAD GND Voltage and Timing Definitions t1 t2 V DD 50% of V DD Clock Output 0V Figure 3. Duty Cycle Definition Note: 6. Excluding any output configured as a reference. 7. Jitter measurement will vary. Actually jitter is dependent on XIN jitter and edge rate, number of active outputs, output frequencies, and device programming. Document #: 38-07748 Rev. ** Page 5 of 9 CY244/45ZXC t3 t4 V DD 80% of V DD 20% of V DD Clock Output 0V Figure 4. ER = (0.6 × VDD)/t3, EF = (0.6 × VDD)/t4 Finish Cycle Start at Full Cycle FS Figure 5. FS Controlled Clock Output Ordering Information Part Number[8] Type Production Flow Lead-free CY244ZXC-XXX 16-pin TSSOP Commercial, 0°C to +70°C CY244ZXC-XXXT 16-pin TSSOP - Tape and Reel Commercial, 0°C to +70°C CY245ZXC-XXX 20-pin TSSOP Commercial, 0°C to +70°C CY245ZXC-XXXT 20-pin TSSOP - Tape and Reel Commercial, 0°C to +70°C Note: 8. The CY244ZXC-xxx, CY245ZXC-xxx are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document #: 38-07748 Rev. ** Page 6 of 9 CY244/45ZXC Package Drawing and Dimensions 16-lead TSSOP 4.40 mm Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A Document #: 38-07748 Rev. ** Page 7 of 9 CY244/45ZXC Package Drawing and Dimensions (continued) 20-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z20 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. 1 MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PART # 4.30[0.169] 4.50[0.177] Z20.173 STANDARD PKG. ZZ20.173 LEAD FREE PKG. 20 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.25[0.010] BSC 1.10[0.043] MAX. GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] 6.40[0.252] 6.60[0.260] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85118-*A All product and company names mentioned in this document are trademarks of their respective holder. Document #: 38-07748 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY244/45ZXC Document History Page Document Title: CY244/45ZXC Factory Programmable Quad PLL Clock Generator with VCXO Document Number: 38-07748 REV. ECN NO. Issue Date Orig. of Change ** 330814 See ECN RGL Document #: 38-07748 Rev. ** Description of Change New data sheet Page 9 of 9