CY241V08A-05,06 MPEG Clock Generator with VCXO Features Benefits • Integrated phase-locked loop (PLL) • Digital VCXO control • Low-jitter, high-accuracy outputs • Electromagnetic interference (EMI) reduction for standards compliance • VCXO with analog adjust • Second source for existing designs • 3.3V operation • Compatible with MK3727 (–5, –6) • Application compatibility for a wide variety of designs • Enables design compatibility • Highest-performance PLL tailored for multimedia applications • Meets critical timing requirements in complex system designs • Lower drive strength settings (CY241V08A–06) CY241V08A–05,–06 Logic Block Diagram 13.5 XIN OSC Q XOUT OUTPUT DIVIDERS Φ VCO 27 MHz P VCXO PLL VDD VSS Pin Configurations CY241V08A–05,–06 8-pin SOIC XIN 1 8 XOUT VDD VCXO 2 7 NC or VSS 3 6 NC or VDD 4 5 27 MHz VSS Part Number Outputs CY241V08A–05 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz non-linear Cypress specification Compatible with MK3727A non linear VCXO control CY241V08A–06 1 13.5-MHz pullable crystal input per 1 copy of 27 MHz non-linear Cypress specification Same as CY241V08A–05 except lower drive strength Input Frequency Range Cypress Semiconductor Corporation Document #: 38-07670 Rev. ** • Output Frequencies 3901 North First Street • VCXO Control Curve Other Features San Jose, CA 95134 • 408-943-2600 Revised April 09, 2004 CY241V08A-05,06 Pin Description Name Pin Number Description XIN 1 Reference crystal input VDD 2 Voltage supply VCXO 3 Input analog control for VCXO VSS 4 Ground 27 MHz 5 27-MHz clock output NC/VDD 6 No connect or voltage supply NC/VSS 7 No connect or ground XOUT 8 Reference crystal output Document #: 38-07670 Rev. ** Page 2 of 6 CY241V08A-05,06 Absolute Maximum Conditions Data Retention @ Tj = 125°C................................> 10 years Package Power Dissipation...................................... 350 mW Supply Voltage (VDD) ........................................–0.5 to +7.0V ESD (Human Body Model) MIL-STD-883................. > 2000V DC Input Voltage...................................... –0.5V to VDD + 0.5 (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature (Non-condensing)..... –55°C to +125°C Junction Temperature ................................ –40°C to +125°C Pullable Crystal Specifications[1] Parameter Description Comments Min. Typ. Max. Unit Parallel resonance, fundamental mode, AT cut – 13.5 – MHz Nominal load capacitance – 14 – pF FNOM Nominal crystal frequency CLNOM R1 Equivalent series resistance (ESR) Fundamental mode – – 25 Ω R3/R1 Ratio of third overtone mode ESR Ratio used because typical R1 values to fundamental mode ESR are much less than the maximum spec 3 – – – DL Crystal drive level No external series resistor assumed 150 – – µW F3SEPHI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 – C1 Crystal motional capacitance 14.4 18 21.6 fF Min. Typ. Max. Unit 3.135 3.3 3.465 V 0 – 70 °C Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance tPU Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) – – 15 pF 0.05 – 500 ms DC Electrical Specifications Parameter Name Description Min. Typ. Max. Unit IOH Output HIGH Current VOH = VDD – 0.5V, VDD = 3.3V 12 24 – mA IOL Output LOW Current VOL = 0.5V, VDD = 3.3V 12 24 – mA CIN Input Capacitance Except XIN, XOUT pins VVCXO VCXO Input Range f∆XO [2] IVDD VCXO Pullability Range Supply Current – – 7 pF 0 – VDD V Low Side – – –75 ppm High Side 75 – – ppm – 30 35 mA Notes: 1. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC. 2. –75/+75 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board capacitance. Document #: 38-07670 Rev. ** Page 3 of 6 CY241V08A-05,06 AC Electrical Specifications (VDD = 3.3V) [3] Parameter[3] Name Description Min. Typ. Max. Unit DC Output Duty Cycle Duty Cycle is defined in Figure 1, 50% of VDD 45 50 55 % EROR Rising Edge Rate –05 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 – V/ns EROF Falling Edge Rate –05 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. 0.8 1.4 – V/ns EROR Rising Edge Rate –06 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. 0.7 1.1 – V/ns EROF Falling Edge Rate –06 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. 0.7 1.1 – V/ns t9 Clock Jitter Peak-to-peak period jitter – – 100 ps t10 PLL Lock Time – – 3 ms Test and Measurement Set-up VDD 0.1 µF Outputs CLOAD DUT GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Note: 3. Not 100% tested. Document #: 38-07670 Rev. ** Page 4 of 6 CY241V08A-05,06 Ordering Information Package Name Ordering Code Operating Range Package Type Operating Voltage Features CY241V08ASC–05,06 S8 8-pin SOIC Commercial 3.3V Linear VCXO control curve CY241V08ASC–05,06T S8 8-pin SOIC - Tape and Reel Commercial 3.3V Linear VCXO control curve Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07670 Rev. ** Page 5 of 6 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY241V08A-05,06 Document History Page Document Title: CY241V08A-05,06 MPEG Clock Generator with VCXO Document Number: 38-07670 REV. ECN NO. Issue Date Orig. of Change ** 214066 See ECN RGL Document #: 38-07670 Rev. ** Description of Change New Data Sheet Page 6 of 6