CY29352 2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer Features • • • • • • • • • • • • • • Description Output frequency range: 16.67 MHz to 200 MHz Input frequency range: 16.67 MHz to 200 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs ±2% max Output duty cycle variation 11 Clock outputs: Drive up to 22 clock lines LVCMOS reference clock input 125-ps max output-output skew PLL bypass mode Spread Aware™ Output enable/disable Pin compatible with MPC9352 and MPC952 Industrial temperature range: –40°C to +85°C 32-pin 1.0-mm TQFP package The CY29352 is a low-voltage high-performance 200 MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29352 features an LVCMOS reference clock input and provides 11 outputs partitioned in 3 banks of 5, 4, and 2 outputs. Bank A divides the VCO output by 4 or 6 while Bank B divides by 4 and 2 and Bank C divides by 2 and 4 per SEL(A:C) settings, see Table 2, “Function Table,” on page 2. These dividers allow output to input ratios of 3:1, 2:1, 3:2, 1:1, 2:3, 1:2, and 1:3. Each LVCMOS compatible output drives 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output drives one or two traces giving the device an effective fanout of 1:22. The PLL is ensured stable if the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 16.67 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to one of the outputs. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1, “Frequency Table,” on page 2. When PLL_EN# is HIGH, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Block Diagram Pin Configuration Phase Detector VCO 200-500MHz ÷2 ÷4 / ÷6 FB_IN QA0 QA1 32 31 30 29 28 27 26 25 REFCLK VDDQC QC1 QC0 VSS VSS QB3 QB2 VDDQB PLL_EN# QA2 QA3 QA4 LPF VCO_SEL SELA ÷4 / ÷2 VCO_SEL SELC SELB SELA MR/OE# REFCLK AVSS FB_IN QB0 QB1 SELB CY29352 24 23 22 21 20 19 18 17 VSS QB1 QB0 VDDQB VDDQA QA4 QA3 VSS 9 10 11 12 13 14 15 16 QB2 1 2 3 4 5 6 7 8 ÷2 / ÷4 PLL_EN# AVDD VDD QA0 VSS QA1 QA2 VDDQA QB3 QC0 QC1 SELC MR/OE# Cypress Semiconductor Corporation Document #: 38-07476 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 26, 2007 [+] Feedback CY29352 Pin Description[1] Pin 6 Name REFCLK I/O Type Description I, PD LVCMOS Reference clock input. 12, 14, 15, 18, 19 QA(0:4) O LVCMOS Clock output bank A. 22, 23, 26, 27 QB(0:3) O LVCMOS Clock output bank B. 30, 31 QC(0,1) O LVCMOS Clock output bank C. 8 FB_IN I, PD LVCMOS Feedback clock input. Connect to an output for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. 1 VCO_SEL I, PD LVCMOS VCO divider select input. See Table 2. 5 MR/OE# I, PD LVCMOS Master reset/output enable/disable input. See Table 2. 9 PLL_EN# I, PD LVCMOS PLL enable/disable input. See Table 2. 2, 3, 4 SEL(A:C) I, PD LVCMOS Frequency select input, Bank (A:C). See Table 2. 16, 20 VDDQA Supply VDD 2.5V or 3.3V power supply for bank A output clocks.[2,3] 21, 25 VDDQB Supply VDD 2.5V or 3.3V power supply for bank B output clocks.[2,3] 32 VDDQC Supply VDD 2.5V or 3.3V power supply for bank C output clocks.[2,3] 10 AVDD Supply VDD 2.5V or 3.3V power supply for PLL.[2,3] 11 VDD Supply VDD 2.5V or 3.3V power supply for core and inputs.[2,3] 7 AVSS Supply Ground Analog ground. Supply Ground Common ground. 13, 17, 24, 28, 29 VSS Table 1. Frequency Table VCO_SEL Feedback Output Divider Input Frequency Range (AVDD = 3.3V) 0 ÷2 Input Clock * 2 100 MHz to 200 MHz 0 ÷4 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 100 MHz 0 ÷6 Input Clock * 6 33.33 MHz to 83.33 MHz 33.33 MHz to 66.67 MHz 1 ÷2 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 100 MHz 1 ÷4 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 50 MHz 1 ÷6 Input Clock * 12 16.67 MHz to 41.67 MHz 16.67 MHz to 33.33 MHz VCO Input Frequency Range (AVDD = 2.5V) 100 MHz to 200 MHz Table 2. Function Table Control Default 0 1 VCO ÷ 2 VCO_SEL 0 VCO PLL_EN# 0 PLL enabled. The VCO output connects Bypass mode, PLL disabled. The input clock to the output dividers connects to the output dividers MR/OE# 0 Outputs enabled Outputs disabled (three-state), VCO running at its minimum frequency SELA 0 QA = VCO ÷ 4 QA = VCO ÷ 6 SELB 0 QB = VCO ÷ 4 QB = VCO ÷ 2 SELC 0 QC = VCO ÷ 2 QC = VCO ÷ 4 Notes 1. PD = Internal pull down. 2. A 0.1-μF bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, and VDDQC power supply pins. Document #: 38-07476 Rev. *A Page 2 of 9 [+] Feedback CY29352 Absolute Maximum Conditions Parameter Description Min Max Unit –0.3 5.5 V Functional 2.375 3.465 V DC Input Voltage Relative to VSS –0.3 VDD + 0.3 V VOUT DC Output Voltage Relative to VSS –0.3 VDD + 0.3 V VTT Output Termination Voltage VDD ÷ 2 V LU Latch Up Immunity Functional RPS Power Supply Ripple Ripple Frequency < 100 kHz TS Temperature, Storage Non Functional TA Temperature, Operating Ambient Functional TJ Temperature, Junction ØJC VDD DC Supply Voltage VDD DC Operating Voltage VIN Condition 200 mA 150 mVp-p –65 +150 °C –40 +85 °C Functional 155 °C Dissipation, Junction to Case Functional 42 °C/W ØJA Dissipation, Junction to Ambient Functional 105 °C/W ESDH ESD Protection (Human Body Model) FIT Failure in Time 2000 Volts Manufacturing test 10 ppm DC Parameters (VDD= 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description Condition VIL Input Voltage, Low LVCMOS VIH Input Voltage, High LVCMOS Output Voltage, Low[4] IOL = 15 mA VOH Output Voltage, High[4] IOH = –15 mA VOL Min Typ 1.7 Max Unit 0.7 V VDD + 0.3 V 0.6 V 1.8 V IIL Input Current, Low VIL = VSS –10 μA IIH Input Current, High[5] VIL = VDD 100 μA IDDA PLL Supply Current AVDD only 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD 3 5 mA IDD Dynamic Supply Current CIN Input Pin Capacitance ZOUT Output Impedance 170 mA 4 pF 17–20 Ω Notes 4. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission lines. 5. Inputs have pull-down resistors that affect the input current. Document #: 38-07476 Rev. *A Page 3 of 9 [+] Feedback CY29352 DC Parameters (VDD= 3.3V ± 5%, TA = –40°C to +85°C) Parameter Description Condition Max Unit 0.8 V VDD + 0.3 V IOL = 24 mA 0.55 V IOL = 12 mA 0.30 VIL Input Voltage, Low LVCMOS VIH Input Voltage, High LVCMOS VOL Output Voltage, Low[4] Min Typ 2.0 VOH Output Voltage, High[4] IOH = –24 mA IIL Input Current, Low VIL = VSS 2.4 V –10 μA IIH Input Current, 100 μA IDDA PLL Supply Current AVDD only 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD 3 5 mA IDD Dynamic Supply Current CIN Input Pin Capacitance ZOUT Output Impedance High[5] VIL = VDD 240 mA 4 pF 14–17 Ω AC Parameters[6] (VDD= 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description fVCO VCO Frequency fin Input Frequency Condition ÷2 Feedback Max Unit 200 400 MHz 100 200 MHz 50 100 ÷6 Feedback 33.33 66.67 ÷8 Feedback 25 50 ÷12 Feedback 16.67 33.33 0 200 25 75 % 1.0 ns 200 MHz Bypass mode (PLL_EN# = 1) Input Duty Cycle tr , tf TCLK Input Rise/FallTime 0.7V to 1.7V fMAX Maximum Output Frequency ÷2 Output Output Duty Cycle Typ ÷4 Feedback frefDC DC Min 100 ÷4 Output 50 100 ÷6 Output 33.33 66.67 ÷8 Output 25 50 ÷12 Output 16.67 33.33 fMAX < 100 MHz 47 53 fMAX > 100 MHz 44 56 0.1 1.0 ns -100 100 ps 125 ps tr , tf Output Rise/Fall times 0.6V to 1.8V t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, same VDD, does not include jitter tsk(O) Output-to-Output Skew Skew within Bank % Note 6. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at the same supply voltage unless otherwise stated. Parameters are guaranteed by characterization and are not 100% tested. Document #: 38-07476 Rev. *A Page 4 of 9 [+] Feedback CY29352 AC Parameters[6] (VDD= 2.5V ± 5%, TA = –40°C to +85°C) Parameter tsk(B) Description Bank-to-Bank Skew Condition Min Typ Max Unit Banks at same voltage, same frequency 175 ps Banks at same voltage, different frequency 225 tPLZ, HZ Output Disable Time 8 ns tPZL, ZH Output Enable Time 10 ns BW PLL Closed Loop Bandwidth (–3 dB) tJIT(CC) tJIT(PER) tJIT(φ) tLOCK Cycle-to-Cycle Jitter Period Jitter I/O Phase Jitter ÷2 Feedback 2 ÷4 Feedback 1 - 1.5 ÷6 Feedback 0.6 ÷8 Feedback 0.75 ÷12 Feedback 0.5 MHz Same frequency 100 Multiple frequencies 300 Same frequency 100 Multiple frequencies 150 VCO < 300 MHz 150 VCO > 300 MHz 100 Maximum PLL Lock Time ps ps ps 1 ms Max Unit 500 MHz MHz AC Parameters[6] (VDD = 3.3V ± 5%, TA = –40°C to +85°C) Parameter Description fVCO VCO Frequency fin Input Frequency Condition Min 200 Typ ÷2 Feedback 100 200 ÷4 Feedback 50 125 ÷6 Feedback 33.33 83.33 ÷8 Feedback 25 62.5 ÷12 Feedback 16.67 41.67 0 200 25 75 % 1.0 ns MHz Bypass mode (PLL_EN# = 1) frefDC Input Duty Cycle tr , tf TCLK Input Rise/FallTime 0.8V to 2.0V fMAX Maximum Output Frequency ÷2 Output 100 200 ÷4 Output 50 125 ÷6 Output 33.33 83.33 ÷8 Output 25 62.5 ÷12 Output DC Output Duty Cycle 16.67 41.67 fMAX < 100 MHz 48 52 fMAX > 100 MHz 44 56 0.1 1.0 ns –100 200 ps 125 ps tr , tf Output Rise/Fall times 0.55V to 2.4V t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, same VDD, does not include jitter tsk(O) Output-to-Output Skew Skew within each Bank Document #: 38-07476 Rev. *A % Page 5 of 9 [+] Feedback CY29352 AC Parameters[6] (VDD = 3.3V ± 5%, TA = –40°C to +85°C) Parameter tsk(B) Description Condition Bank-to-Bank Skew Min Typ Max Unit Banks at same voltage, same frequency 175 ps Banks at same voltage, different frequency 235 Banks at different voltage 425 tPLZ, HZ Output Disable Time 8 ns tPZL, ZH Output Enable Time 10 ns BW PLL Closed Loop Bandwidth (–3 dB) tJIT(CC) Cycle-to-Cycle Jitter ÷2 Feedback 2 ÷4 Feedback 1 – 1.5 ÷6 Feedback 0.6 ÷8 Feedback 0.75 ÷12 Feedback 0.5 Same frequency 100 Multiple frequencies 275 100 tJIT(PER) Period Jitter Same frequency tJIT(φ) I/O Phase Jitter VCO < 300 MHz 150 VCO > 300 MHz 100 Multiple frequencies tLOCK MHz ps ps 150 Maximum PLL Lock Time ps 1 ms Figure 1. AC Test Reference for VDD = 3.3V / 2.5V Zo = 50 ohm Pulse Generator Z = 50 ohm Zo = 50 ohm R T = 50 ohm R T = 50 ohm VTT VTT Figure 2. Propagation Delay t(φ), static phase offset VDD LVCMOS_CLK V DD /2 GND V DD FB_IN V DD /2 t(φ) Document #: 38-07476 Rev. *A GND Page 6 of 9 [+] Feedback CY29352 Figure 3. Output Duty Cycle (DC) V DD V DD/2 tP GND T0 DC = tP / T0 x 100% Figure 4. Output-to-Output Skew, tsk(O) VDD VDD/2 GND VDD VDD/2 tSK(O) GND Ordering Information Part Number Package Type Product Flow Lead-free CY29352AXI 32-pin TQFP Industrial, –40°C to +85°C CY29352AXIT 32-pin TQFP – Tape and Reel Industrial, –40°C to 85°C Document #: 38-07476 Rev. *A Page 7 of 9 [+] Feedback CY29352 Package Drawing and Dimension Figure 5. 32-lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32 51-85063-*B Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are trademarks of their respective holders. Document #: 38-07476 Rev. *A Page 8 of 9 © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY29352 Document History Page Document Title:CY29352 2.5V or 3.3V, 200-MHz, 11-Output Zero Delay Buffer Document Number: 38-07476 REV. ECN No. Issue Date Orig. of Change Description of Change ** 124654 03/21/03 RGL New Data Sheet *A 739798 See ECN RGL Removed the leaded parts and replaced by lead-free parts Document #: 38-07476 Rev. *A Page 9 of 9 [+] Feedback