CY2SSTV16857 14-Bit Registered Buffer PC2700-/PC3200-Compliant Features When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock, and REF voltage inputs are allowed. In addition, when RESET is LOW, all registers are reset and all outputs force to the LOW state. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. • Differential Clock Inputs up to 280 MHz • Supports LVTTL switching levels on the RESET pin • Output drivers have controlled edge rates, so no external resistors are required • Two KV ESD protection • Latch-up performance exceeds 100 mA: JESD78, Class II • Conforms to JEDEC STD (JESD82-3) for buffered DDR DIMMs • 48-pin TSSOP Description This 14-bit registered buffer is designed specifically for 2.3V to 2.7V VDD operation and is characterized for operation from 0°C to + 85°C. All inputs are compatible with the JEDEC Standard for SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II-compatible. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR registered DIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. The SSTV16857 operates from a differential clock (CLK and CLK). Data is measured at the crossing of CLK going HIGH, and CLK going LOW. Q1 Q2 VSS VDDQ Q3 Q4 Q5 VSS VDDQ Q6 Q7 VDDQ VSS Q8 Q9 VDDQ VSS Q10 Q11 Q12 VDDQ VSS Q13 Q14 RESET CLK CLK VREF D1 1D C1 Q1 R To 13 Other Channels Cypress Semiconductor Corporation Document #: 38-07443 Rev. *D • 3901 North First Street • 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CY2SSTV16857 Pin Configuration Block Diagram 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 D1 D2 VSS VDD D3 D4 D5 D6 D7 CLK CLK VDD VSS VREF RESET D8 D9 D10 D11 D12 VDD VSS D13 D14 San Jose, CA 95134 • 408-943-2600 Revised January 12, 2005 CY2SSTV16857 Pin Description Pin 34 3,8,13,17,22,27,36,46 28, 37, 45 Name I/O RESET I VSS Ground Type Description Ground. VDD Power 1, 2, 5, 6, 7, 10, 11, 14, 15, 18, 19, 20, 23, 24 Q(1:14) O Data outputs, SSTL_2, Class II output. 25, 26, 29, 30, 31, 32, 33, 40, 41, 42, 43, 44, 47, 48 D(1:14) I Data input clocked on the crossing of the rising edge of CLK, and the falling edge of CLK. Differential clock input. 39, 38 CLK, CLK I/I 4, 8, 12, 16, 21 VDDQ Power 35 VREF I Document #: 38-07443 Rev. *D 2.5V nominal supply voltage. Power supply voltage quiet, 2.5V nominal. Input reference voltage, 1.25V nominal. Page 2 of 8 CY2SSTV16857 Absolute Maximum Conditions[1, 2, 3] VSS < (Vin or Vout) < VDD. This device contains circuitry designed to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Parameter Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Description Min. Max. Unit Non-functional 2.3 2.7 VDC Operating Voltage[4] Functional 2.3 2.7 VDC Vin Input Voltage Relative to VSS 0 VDD VDC Vout Output Voltage Relative to VSS VDDQ VDC IOUT DC Output Current ±50 mA VDD Supply Voltage[4] VDD Condition IIK Continuous Clamp Current VI < 0 or VI > VSS ±50 mA IOK Continuous Clamp Current VO < 0 –50 mA IDD/ISS Continuous current through each VDD or VSS ±100 mA LUI Latch Up Immunity Exceeds spec of RPS Power Supply Ripple Ripple Frequency < 100 kHz Ts Temperature, Storage Non-functional Ta Temperature, Operating Ambient Functional Tj Temperature, Junction Functional ØJc Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 22.23 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) 74.52 °C/W ULFL Flammability By design and verification V–0 Grade MSL Moisture Sensitivity By design and verification MSL – 1 Grade ESDh ESD Protection (Human Body Model) 100 mA 150 mVp-p –65 +150 °C 0 +70 °C 165 °C 2000 V Table 1. DC Electrical Specifications (VDD = Temperature = 0°C to +85 °C) Parameter Description Condition Min. Typ. Max. Unit VDD Supply Voltage PC1600,2100,2700 PC3200 2.5 2.6 2.7 V VDDQ Output Supply Voltage PC1600,2100,2700 PC3200 2.5 2.6 2.7 V VREF Reference voltage (VREF = VDDQ/2) 1.25 1.3 1.35 V VTT Termination voltage VIH Input Voltage, High RESET VIL Input Voltage, Low RESET 0.7 V VOL Output Voltage, Low VDD/VDDQ = 2.3V to 2.7V, IOL = 100 µA, VDD = 2.3 to 2.7V 0.2 V VDD/VDDQ = 2.3V, IOL = 16 mA, VDD = 2.3V 0.35 PC1600,2100,2700 PC3200 VREF – 40 mV VREF VREF+4 0 mV 1.7 V V Notes: 1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 2. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 3. All terminals except VDD. 4. VDD/VDDQ terminals. Document #: 38-07443 Rev. *D Page 3 of 8 CY2SSTV16857 Table 1. DC Electrical Specifications (VDD = Temperature = 0°C to +85 °C) (continued) Parameter Description VOH Output Voltage, High IIL Input Current Condition Min. VDD/VDDQ = 2.3V to 2.7V, IOH = –100 µA, VDD=2.3 to 2.7V VDD – 0.2 VDD/VDDQ = 2.3V, IOH = –16 mA 1.95 Typ. Max. Unit V VI = 1.7V or 0.8V, VREF = 1.15V or 1.35V, VDD = 2.7V ±5 µA VI = 2.7V or 0,VREF = 1.15V or 1.35V, VDD = 2.7V ±5 µA VI = 1.7V or 0.8V, VREF = 1.15V or 1.35V, VDD = 3.6V ±5 µA VI = 2.7V or 0 ±5 µA VI = 1.7V or 0.8V, VREF = 1.15V or 1.35V ±1 µA VI = 2.7V or 0, VREF = 1.15V or 1.35V, Vdd = 2.7V ±1 µA RESET VI = VDD or VSS, VDD = 2.7V ±5 µA VREF VI = 1.5V or 1.35V, VDD = 2.7 ±5 µA IIH Input Current, High Data inputs only IDD Dynamic Supply Current VI = 1.7V or 0.8V, IO = 0, VDD = 2.7V 90 mA VI = 2.7V or 0, IO = 0, VDD = 2.7V 90 mA Data Inputs CLK, CLK Cin Input pin capacitance RESET VI = 1.7V or 0.8V, IO = 0, VDD = 2.7V Clock and Data Inputs Lpin mA. 3 2.5 Pin Inductance All 2.7 2.1 pF 3.5 pF 4.5 nH Table 2. AC Input Electrical Specifications (VDD = 2.5 VDC ± 5%, Temperature = 0°C to +85°C) VDD = 2.5V ± 0.2V Parameter Description Condition Min. Max. Unit 200 MHz FIN Input Clock Frequency CLK, CLK PW Pulse Duration CLK, CLK HIGH or LOW 3.3 ns TACT Differential Inputs Active Time Data inputs must be LOW after RESET HIGH 22 ns TINACT Differential Inputs Inactive Time Data and clock inputs must be held at valid levels (not floating) after RESET LOW 22 ns TSET Set-up Time Fast slew rate, (see notes 5 and 7), Data before CLK, CLK 0.75 ns Slow slew rate, (see notes 6 and 7), Data before CLK, CLK 0.9 ns Fast slew rate, (see notes 5 and 7), Data after CLK, CLK 0.75 ns Slow slew rate (see notes 6 and 7), Data after CLK, CLK 0.9 ns 360 mV THOLD IVpp Hold Time Input Voltage, Pk–Pk Notes: 5. For data signal input slew rate > 1 V/ns. 6. For data signal input slew rate > 0.5 V/ns and < 1 V/ns. 7. CLK, CLK signals input slew rates are > 1 V/ns. Document #: 38-07443 Rev. *D Page 4 of 8 CY2SSTV16857 Table 3. AC Output Electrical Specifications (VDD = 2.5V VDC ± 5%, Temperature = 0°C to +85°C) VDD = 2.5V ± 0.2V Parameter Description Condition Min. FMAX Max. Unit 280 TDEL Propagation Delay from CLK/CLK Q to Q 1.1 2.8 ns TPHL RESET Q 4.3 ns TR Rise Time Any Q 0.85 4 V/ns TF Fall time Any Q 1.0 4 V/ns Output Buffer Characteristics Table 4. Output Buffer Voltage vs. Current (V/I) Characteristics Pull-Down Voltage (V) Min I (mA) Pull-Up Max I (mA) Min I (mA) Max I (mA) 0 0 0 0 0 0.1 6 13 –5 –15 0.2 10 25 –10 –27 0.3 15 38 –15 –38 0.4 19 49 –19 –49 0.5 23 60 –23 –60 0.6 27 71 –28 –72 0.7 30 81 –31 –83 0.8 34 91 –35 –96 0.9 36 100 –38 –104 1.0 38 108 –40 –112 1.1 40 115 –44 –120 1.2 42 123 –46 –125 1.3 43 130 –48 –130 1.4 44 137 –50 –134 1.5 44 144 –51 –137 1.6 45 150 –52 –140 1.7 45 158 –52 –143 1.8 45 165 –52 –146 1.9 45 172 –53 –149 2.0 45 179 –53 –152 2.1 46 185 –53 –154 2.2 46 191 –54 –156 2.3 46 196 –54 –157 2.4 46 201 –54 –159 2.5 46 206 –54 –160 2.6 46 211 –55 –161 2.7 46 216 –55 –162 Document #: 38-07443 Rev. *D Page 5 of 8 CY2SSTV16857 Slew Rate The following table describes output-buffer slew-rate characteristics that are sufficient to meet the requirements of registered DDR DIMM performance and timings. These characteristics are not necessarily production tested but can be guaranteed by design or characterization. Compliance with these rates is not mandatory if it can be adequately demonstrated that alternate characteristics meet the requirements of the registered DDR DIMM application. This information does not necessarily have to appear in the device data sheet. Obtain rise and fall time measurements by using the same procedure for obtaining “Ramp” data according to the current WIA IBIS specification. In particular it is very important to note that the following slew rates are specified at the output of the die, without package parasitics in the power, ground or output paths. The measurement points are at 20% and 80%. The slew-rate test load shall be a 50-ohm resistor to GND for Rise and a 50-ohm resistor to VDDQ for fall. The dV/dt ratio is reduced to V/ns. LVCMOS RESET Input tinact IDD Min. Max. Rise 0.85 V/ns 4 V/ns Fall 1.00 V/ns 4 V/ns Test Configurations[9, 10] Timing Diagrams VI(PP) VICR Input VICR tPHL tPLH Output VTT tsu Data Input VREF* th VTT VOH VOL Figure 3. Voltage Waveforms Propagation Delay Times[12] VIH VDD/2 VIL tPHL Output VICR IDDL Figure 2. Voltage Waveforms Enable and Disable Times Low- and High-level Enabling[11] VI(PP) Timing Input IDDH 90% LVCMOS RESET Input VDD = 2.5V ±0.2V 0V tact 10% Table 5. Output Buffer Slew-Rate Characteristics dV/dt VDD VDD/2 VDD/2 VTT VOH VOL Figure 4. Voltage Waveforms Propagation Delay Times[11 VREF* VTT VIH** VIL*** Figure 1. Voltage Waveforms Set-up and Hold Times[11, 13, 14] R L = 50 O hm F ro m O u tp u t U nder Test T e s t P o in t C L = 30 pF Figure 5. Load Circuit[8] tw Input VREF* VREF* VIH** VIL*** Figure 6. Voltage Waveforms Pulse Duration[13, 14] Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or VSS, and IO = 0 mA. 10. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, ZO = 50 ohm input slew rate = 1 V/ns ±20% (unless otherwise specified). 11. the outputs are measured one at a time with one transition per measurement. 12. *VTT = VREF = VDDQ/2. 13. **VIH = VREF + 350 mV (AC voltage levels). 14. ***VIL = VREF – 350 mV (AC voltage levels). Document #: 38-07443 Rev. *D Page 6 of 8 CY2SSTV16857 Ordering Information Part Number Package Type Product Flow CY2SSTV16857ZC 48-pin TSSOP Commercial, 0° to 70°C CY2SSTV16857ZCT 48-pin TSSOP –Tape and Reel Commercial, 0° to 70°C CY2SSTV16857ZI 48-pin TSSOP Industrial, –40° to 85°C CY2SSTV16857ZIT 48-pin TSSOP –Tape and Reel Industrial, –40° to 85°C Lead-Free CY2SSTV16857ZXC 48-pin TSSOP Commercial, 0° to 70°C CY2SSTV16857ZXCT 48-pin TSSOP –Tape and Reel Commercial, 0° to 70°C CY2SSTV16857ZXI 48-pin TSSOP Industrial, –40° to 85°C CY2SSTV16857ZXIT 48-pin TSSOP –Tape and Reel Industrial, –40° to 85°C Package Diagram 48-lead (240-mil) TSSOP II Z4824 0.500[0.019] 24 1 DIMENSIONS IN MM[INCHES] MIN. MAX. 7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244] REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG. 25 48 12.395[0.488] 12.598[0.496] 1.100[0.043] MAX. GAUGE PLANE 0.25[0.010] 0.20[0.008] 0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] 0°-8° 0.508[0.020] 0.762[0.030] SEATING PLANE 0.100[0.003] 0.200[0.008] 51-85059-*C All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07443 Rev. *D Page 7 of 8 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2SSTV16857 Document History Page Document Title: CY2SSTV16857 14-Bit Registered Buffer PC2700-/PC3200-Compliant Document Number: 38-07443 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 116562 08/21/02 HWT *A 122930 12/18/02 RBI Add power-up requirements to maximum ratings information Changed the Supply voltage (VDD) and Output supply voltage (VDDQ) values from 2.3/2.5/2.7 to 2.5/2.6/2.7Volts in the DC Electrical Specs. table Changed the Reference voltage (VREF) values from 1.15/1.25/1.35 to 1.25/1.3/1.35V in the DC Electrical Specs. table Moved the FMAX value from Min to Max in the AC Output Electrical Spec. table Changed the TR/TF max values from 15.9 to 4V/ns Added Industrial Temp. range in the ordering information Added “PC2700-/PC3200-Compliant” to the title *B 125621 05/20/03 RGL *C 130366 11/03/03 IJA *D 308314 See ECN RGL Document #: 38-07443 Rev. *D New Data Sheet Removed last Features bullet and second-to-last TVSOP package availability Kept only 48-pin TSSOP Added Lead Free Devices Page 8 of 8