SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
D Member of the Texas Instruments
D
D
D
D
D
D
D
D
DGG PACKAGE
(TOP VIEW)
Widebus Family
Supports SSTL_2 Data Inputs
Outputs Meet SSTL_2 Class II
Specifications
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the
RESET Input
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
description
This 14-bit registered buffer is designed for 2.3-V
to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset
(RESET) input. All outputs are SSTL_2, Class II
compatible.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
D1
D2
GND
VCC
D3
D4
D5
D6
D7
CLK
CLK
VCC
GND
VREF
RESET
D8
D9
D10
D11
D12
VCC
GND
D13
D14
The SN74SSTV16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
0°C to 70°C
TSSOP – DGG Tape and reel SN74SSTV16857DGGR
SSTV16857
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '! !"# %! &*)' '$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
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1
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
FUNCTION TABLE
INPUTS
RESET
CLK
CLK
D
OUTPUT
Q
H
↑
↓
H
H
H
↑
↓
L
L
H
L or H
L or H
X
Q0
L
X, or floating
X, or floating
X, or floating
L
logic diagram (positive logic)
RESET
CLK
CLK
VREF
D1
34
38
39
35
One of 14 Channels
48
1D
C1
1
Q1
R
To 13 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDDQ + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0 or VO > VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each VCC, VDDQ, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
recommended operating conditions (see Note 4)
MIN
NOM
MAX
VCC
VDDQ
Supply voltage
VDDQ
2.3
VREF
VTT
Reference voltage (VREF = VDDQ/2)
VI
VIH
Input voltage
AC high-level input voltage
Data inputs
VIL
VIH
AC low-level input voltage
Data inputs
DC high-level input voltage
Data inputs
VIL
VIH
DC low-level input voltage
Data inputs
High-level input voltage
RESET
VIL
VICR
Low-level input voltage
RESET
Common-mode input voltage range
CLK, CLK
0.97
VI(PP)
Peak-to-peak input voltage
CLK, CLK
360
IOH
IOL
High-level output current
–20
Low-level output current
20
Output supply voltage
1.15
Termination voltage
VREF–40mV
0
2.7
V
2.7
V
1.35
V
VREF+40mV
VCC
V
1.25
VREF
UNIT
VREF+310mV
V
V
VREF–310mV
VREF+150mV
V
V
VREF–150mV
1.7
V
V
0.7
V
1.53
V
mV
mA
TA
Operating free-air temperature
0
70
_C
NOTE 4: The RESET input of the device must be held at a valid logic level (not floating) to ensure proper device operation. The differential inputs
must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature
number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
II = –18 mA
IOH = –100 µA
VOH
ICC
All inputs
IOL = 16 mA
VI = VCC or GND
Static standby
RESET = GND
MIN
TYP†
2.3 V
2.3 V to 2.7 V
IOH = –16 mA
IOL = 100 µA
VOL
II
VCC AND
VDDQ
TEST CONDITIONS
2.3 V
MAX
UNIT
–1.2
V
VDDQ–0.2
1.95
V
2.3 V to 2.7 V
0.2
2.3 V
0.35
2.7 V
IO = 0
27V
2.7
±5
µA
10
µA
Static operating
RESET = VCC, VI = VIH(AC) or VIL(AC)
Dynamic operating –
clock only
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle
Dynamic operating –
per each data input
RESET = VCC, VI = VIH(AC) or VIL(AC),
CLK and CLK switching 50% duty cycle,
One data input switching at
one-half clock frequency, 50% duty cycle
rOH
Output high
IOH = –20 mA
2.3 V to 2.7 V
7
20
Ω
rOL
Output low
IOL = 20 mA
2.3 V to 2.7 V
7
20
Ω
rO(∆)
rOH – rOL
IO = 20 mA, TA = 25°C
6
Ω
Data inputs
VI = VREF ± 310 mV
VICR = 1.25 V, VI(PP) = 360 mV
ICCD
Ci
CLK, CLK
IO = 0
56
28
9
µA/
clock
MHz/
D input
2.5 V
2.5 V
VI = VCC or GND
† All typical values are at VCC = 2.5 V, TA = 25°C.
• DALLAS, TEXAS 75265
mA
µA/
MHz
2.5 V
RESET
POST OFFICE BOX 655303
8
V
2.5
3
3.5
2.5
3
3.5
2.5
3
3.5
pF
F
3
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V†
MIN
UNIT
MAX
fclock
tw
Clock frequency
200
tact
tinact
Differential inputs active time (see Note 5)
22
ns
Differential inputs inactive time (see Note 6)
22
ns
tsu
Set p time
Setup
th
Hold time
Pulse duration
CLK, CLK high or low
D t before
Data
b f
CLK↑,
CLK↑ CLK↓
ns
0.9
0.75
Fast slew rate (see Notes 7 and 9)
Slow slew rate (see Notes 8 and 9)
ns
0.75
Fast slew rate (see Notes 7 and 9)
Slow slew rate (see Notes 8 and 9)
2.5
MHz
D t after
Data
ft CLK↑,
CLK↑ CLK↓
ns
0.9
† For this test condition, VDDQ always is equal to VCC.
NOTES: 5. Data inputs must be held low for a minimum time of tact min, after RESET is taken high.
6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tinact min, after RESET is taken low.
7. Data signal input slew rate ≥1 V/ns
8. Data signal input slew rate ≥0.5 V/ns and <1 V/ns
9. CLK, CLK input slew rates are ≥1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
fmax
tpd
FROM
(INPUT)
TO
(OUTPUT)
MIN
CLK and CLK
Q
POST OFFICE BOX 655303
Q
• DALLAS, TEXAS 75265
1.1
UNIT
MAX
200
tPHL
RESET
† For this test condition, VDDQ always is equal to VCC.
4
VCC = 2.5 V
± 0.2 V†
MHz
2.8
ns
5
ns
SCES344E – DECEMBER 2000 – REVISED NOVEMBER 2002
PARAMETER MEASUREMENT INFORMATION
VTT
50 Ω
From Output
Under Test
Test Point
CL = 30 pF
(see Note A)
LOAD CIRCUIT
tw
VIH
VREF
Input
VIL
VCC
LVCMOS
RESET
Input
VCC/2
VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tinact
ICC
(see
Note B)
VREF
VI(PP)
tact
90%
10%
ICCH
Timing
Input
ICCL
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
VICR
VICR
tPLH
tPHL
VOH
Output
VTT
VTT
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VI(PP)
Timing
Input
tsu
VIH
LVCMOS
RESET
Input
VICR
VCC/2
VIL
tPHL
th
VOH
VIH
Input
VREF
Output
VREF
VTT
VOL
VIL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A. CL includes probe and jig capacitance.
B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω,
input slew rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time with one transition per measurement.
E. VTT = VREF = VDDQ/2
F. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input.
G. VIL = VREF – 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
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5
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
HPA00021DGGR
ACTIVE
TSSOP
DGG
48
None
CU NIPDAU
Level-1-220C-UNLIM
SN74SSTV16857DGGR
ACTIVE
TSSOP
DGG
48
2000
None
CU NIPDAU
Level-1-220C-UNLIM
SN74SSTV16857DGVR
ACTIVE
TVSOP
DGV
48
2000
None
CU NIPDAU
Level-1-250C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
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