SN74SSTV32867-EP 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS www.ti.com SCES664 – SEPTEMBER 2006 FEATURES • • • • • • (1) Controlled Baseline – One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of –40°C to 85°C Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product Change Notification Qualification Pedigree (1) Member of the Texas Instruments Widebus+™ Family Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. • • • • • • • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated DIMM Load Supports SSTL_2 Data Inputs Differential Clock (CLK and CLK) Inputs Supports LVCMOS Switching Levels on the RESET Input RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DESCRIPTION/ORDERING INFORMATION This 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads. The SN74SSTV32867-EP operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. ORDERING INFORMATION PACKAGE (1) TA –40°C to 85°C (1) LFBGA – GKE Tape and reel ORDERABLE PART NUMBER CSSTV32867SGKEREP TOP-SIDE MARKING S867EP Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus+ is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2006, Texas Instruments Incorporated SN74SSTV32867-EP 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS www.ti.com SCES664 – SEPTEMBER 2006 GKE PACKAGE (TOP VIEW) 1 2 3 4 5 TERMINAL ASSIGNMENTS 6 A B C D E 1 2 3 4 5 6 A D1 VCC GND VDDQ Q1 Q2 B D3 D2 VREF GND Q3 Q4 C D5 D4 NC GND Q5 Q6 D D7 D6 GND VDDQ Q7 Q8 E D9 D8 VCC GND Q9 VDDQ F D11 D10 GND VDDQ Q10 GND G D13 D12 VCC VDDQ Q12 Q11 F H D15 D14 GND GND GND Q13 G J CLK NC GND GND GND Q14 H K CLK RESET VCC VDDQ Q15 Q16 J L D16 D17 GND VDDQ Q17 GND K M D18 D19 VCC GND Q18 VDDQ L N D20 D21 GND VDDQ Q20 Q19 P D22 D23 NC GND Q22 Q21 R D24 D25 NC GND Q24 Q23 T D26 VCC GND VDDQ Q26 Q25 M N P R T FUNCTION TABLE INPUTS RESET CLK CLK D OUTPUT Q H ↑ ↓ H H H ↑ ↓ L L H L or H L or H X Q0 L X or floating X or floating X or floating L LOGIC DIAGRAM (POSITIVE LOGIC) RESET CLK CLK VREF D1 K2 J1 K1 B3 A1 1D C1 R To 25 Other Channels 2 Submit Documentation Feedback A5 Q1 SN74SSTV32867-EP 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS www.ti.com SCES664 – SEPTEMBER 2006 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC or VDDQ Supply voltage range –0.5 3.6 V VI Input voltage range (2) –0.5 VCC + 0.5 V –0.5 VDDQ + 0.5 range (2) (3) UNIT VO Output voltage IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 or VO > VDDQ ±50 mA IO Continuous output current VO = 0 to VDDQ ±50 mA ±100 Continuous current through each VCC, VDDQ, or GND θJA Package thermal impedance (4) Tstg Storage temperature range (1) (2) (3) (4) V –65 mA 40 °C/W 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 3.6 V maximum. The package thermal impedance is calculated in accordance with JESD 51-7. Recommended Operating Conditions (1) MIN NOM MAX UNIT VCC Supply voltage VDDQ Output supply voltage VREF Reference voltage (VREF = VDDQ/2) VTT Termination voltage VI Input voltage VIH AC high-level input voltage Data input VIL AC low-level input voltage Data input VIH DC high-level input voltage Data input VIL DC low-level input voltage Data input VIH High-level input voltage RESET VIL Low-level input voltage RESET VICR Common-mode input voltage range CLK, CLK 0.97 VI(PP) Peak-to-peak input voltage CLK, CLK 360 IOH High-level output current –8 mA IOL Low-level output current 8 mA TA Operating free-air temperature 85 °C (1) VDDQ 2.7 V 2.3 2.7 V 1.15 1.25 1.35 V VREF – 40 mV VREF VREF + 40 mV V VCC V 0 VREF + 310 mV V VREF – 310 mV V VREF + 150 mV V VREF – 150 mV V 1.7 V 0.7 –40 V 1.53 V mV The RESET input of the device must be held at VCC or GND to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback 3 SN74SSTV32867-EP 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS www.ti.com SCES664 – SEPTEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II = –18 mA IOH = –100 µA VOH ICC ICCD CI (2) (1) (2) MIN TYP (1) MAX 2.3 V –1.5 2.3 V to 2.7 V IOH = –8 mA 2.3 V IOL = 100 µA VDDQ – 0.2 2.3 V to 2.7 V 0.2 2.3 V 0.45 All inputs VI = VCC or GND 2.7 V Static standby RESET = GND Static operating RESET = VCC, VI = VIH(AC) or VIL(AC) Dynamic operating – clock only RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching, 50% duty cycle Dynamic operating – per each data input RESET = VCC, VI = VIH(AC) or VIL(AC), CLK and CLK switching, 50% duty cycle, One data input switching at one-half clock frequency, 50% duty cycle Data inputs VI = VREF ± 310 mV CLK, CLK VICR = 1.25 V, RESET VI = VCC or GND IO = 0 IO = 0 UNIT V V 1.7 IOL = 8 mA VOL II VCC TEST CONDITIONS 2.7 V V ±5 µA 40 µA 95 mA 44 µA/MHZ 5 µA/clock MHz/ D input 2.5 V 3.5 VI(PP) = 360 mV 2.5 V 4.5 pF 5 All typical values are at VCC = 2.5 V, TA = 25°C. Measured with 50-MHz input frequency Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 2.5 ± 0.2 V MIN MAX fclock Clock frequency tw Pulse duration tact Differential inputs active time (1) 22 ns tinact Differential inputs inactive time (2) 22 ns tsu Setup time th Hold time (1) (2) (3) (4) (5) 4 UNIT TYP 200 CLK, CLK high or low Fast slew rate (3) (4) Slow slew rate (4) (5) Fast slew rate (3) (4) Slow slew rate (4) (5) Data before CLK↑, CLK↓ Data after CLK↑, CLK↓ 2.5 ns 1.0 1.5 1.0 1.5 Data inputs must be low a minimum time of tact min, after RESET is taken high. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact min, after RESET is taken low. Data signal input slew rate ≥ 1 V/ns CLK, CLK input slew rates are ≥ 1 V/ns. Data signal input slew rate ≥ 0.5 V/ns and < 1 V/ns Submit Documentation Feedback MHz ns ns SN74SSTV32867-EP 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS www.ti.com SCES664 – SEPTEMBER 2006 Switching Characteristics over recommended operating free-air temperature range, VREF = VDDQ/2 and CL = 30 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax VCC = 2.5 V ± 0.2 V MIN UNIT MAX 200 MHz tpd CLK and CLK Q 5.5 ns tPHL RESET Q 5.2 ns Submit Documentation Feedback 5 SN74SSTV32867-EP 26-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS www.ti.com SCES664 – SEPTEMBER 2006 PARAMETER MEASUREMENT INFORMATION From Output Under Test Test Point CL = 30 pF (see Note A) tw VIH VREF Input LOAD CIRCUIT VREF VIL VOLTAGE WAVEFORMS PULSE DURATION LVCMOS RESET Input VCC VI(PP) VCC/2 VCC/2 0V tinact Timing Input tact ICC (see Note B) 90% 10% ICCH ICCL VICR VICR tPLH tPHL VOH Output VCC/2 VCC/2 VOL VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VI(PP) Timing Input VICR tsu VIH LVCMOS Input VCC/2 VIL tPHL th VIH Input VREF VREF VOH Output VCC/2 VIL VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES A. CL includes probe and jig capacitance. B. ICC tested with clock and data inputs held at VCC or GND, and IO = 0 mA. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, input slew rate = 1 V/ns ±20% (unless otherwise noted). D. The outputs are measured one at a time, with one transition per measurement. E. VREF = VDDQ/2 F. VIH = VREF + 310 mV (ac voltage levels) for differential inputs. VIH = VCC for LVCMOS input. G. VIL = VREF – 310 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty CSSTV32867SGKEREP ACTIVE LFBGA GKE 96 1000 TBD SNPB N / A for Pkg Type V62/06676-01XE ACTIVE LFBGA GKE 96 1000 TBD SNPB N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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OTHER QUALIFIED VERSIONS OF SN74SSTV32867-EP : • Catalog: SN74SSTV32867 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CSSTV32867SGKEREP Package Package Pins Type Drawing LFBGA GKE 96 SPQ Reel Reel Diameter Width (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 5.7 13.7 2.0 8.0 W Pin1 (mm) Quadrant 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSSTV32867SGKEREP LFBGA GKE 96 1000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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