CYPRESS CY62256NLL-70ZC

CY62256N
256K (32K x 8) Static RAM
Functional Description[1]
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• High speed: 55 ns
• Voltage range: 4.5V–5.5V operation
• Low active power
— 275 mW (max.)
• Low standby power (LL version)
— 82.5 µW (max.)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
The CY62256N is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and tri-state drivers. This device has an
automatic power-down feature, reducing the power
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
• CMOS for optimum speed/power
• Available in pb-free and non Pb-free 28-lead (600-mil)
PDIP, 28-lead (300-mil) narrow SOIC, 28-lead TSOP-I
and 28-lead Reverse TSOP-I packages
Logic Block Diagram
I/O0
INPUTBUFFER
I/O1
32K x 8
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
I/O3
I/O4
I/O5
CE
WE
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A12
A11
A1
A0
A13
A14
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 001-06511 Rev. *A
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY62256N
Product Portfolio
Power Dissipation
VCC Range (V)
Product
CY62256NL
Com’l / Ind’l
Min.
Typ.[2]
Max.
Speed
(ns)
4.5
5.0
5.5
70
Operating, ICC
(mA)
Standby, ISB2
(µA)
Typ.[2]
Max.
Typ.[2]
Max.
25
50
2
50
CY62256NLL
Commercial
70
25
50
0.1
5
CY62256NLL
Industrial
55/70
25
50
0.1
10
CY62256NLL
Automotive-A
55/70
25
50
0.1
10
CY62256NLL
Automotive-E
55
25
50
0.1
15
Pin Configurations
Narrow SOIC
Top View
DIP
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
22
23
A11
A10
A9
A8
A7
A6
A5
VCC
WE
A4
A3
A2
A1
OE
7
24
25
26
27
28
1
2
3
4
5
6
7
21
TSOP I
Top View
(not to scale)
8
9
6
5
4
3
2
1
28
27
26
25
24
23
22
20
19
18
17
16
15
14
13
12
11
10
9
8
TSOP I
Reverse Pinout
Top View
(not to scale)
10
11
12
13
14
15
16
17
18
19
20
21
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A14
A13
A12
A12
A13
A14
I/O0
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A0
Pin Definitions
Pin Number
Type
Description
1–10, 21, 23–26
Input
A0–A14. Address Inputs
11–13, 15–19,
Input/Output
I/O0–I/O7. Data lines. Used as input or output lines depending on operation
27
Input/Control
WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is
conducted
20
Input/Control
CE. When LOW, selects the chip. When HIGH, deselects the chip
22
Input/Control
OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins
behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input
data pins
14
Ground
GND. Ground for the device
28
Power Supply VCC. Power supply for the device
Note:
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document #: 001-06511 Rev. *A
Page 2 of 13
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CY62256N
Maximum Ratings
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guidelines, not tested.)
Latch-up Current.................................................... > 200 mA
Storage Temperature ................................. –65°C to +150°C
Operating Range
Ambient Temperature with
Power Applied..............................................-55°C to +125°C
Ambient Temperature (TA)[7]
VCC
0°C to +70°C
5V ± 10%
Industrial
–40°C to +85°C
5V ± 10%
Automotive-A
–40°C to +85°C
5V ± 10%
–40°C to +125°C
5V ± 10%
Range
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
Commercial
DC Voltage Applied to Outputs
in High-Z State[3] ....................................–0.5V to VCC + 0.5V
Automotive-E
[3]
DC Input Voltage .................................–0.5V to VCC + 0.5V
Electrical Characteristics Over the Operating Range
-55
Parameter
Description
Test Conditions
Min. Typ.
[2]
-70
Max.
VOH
Output HIGH Voltage
VCC = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
VIH
Input HIGH Voltage
2.2
VCC
+0.5V
VIL
Input LOW Voltage
–0.5
IIX
Input Leakage Current
IOZ
Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
ISB1
ISB2
2.4
Automatic CE
Power-down Current—
TTL Inputs
Automatic CE
Power-down Current—
CMOS Inputs
Max. VCC, CE > VIH,
VIN > VIH or VIN < VIL,
f = fMAX
Max. VCC,
CE > VCC − 0.3V
VIN > VCC − 0.3V, or
VIN < 0.3V, f = 0
Max.
2.4
Unit
V
0.4
GND < VI < VCC
VCC = Max.,
IOUT = 0 mA,
f = fMAX = 1/tRC
Min. Typ.[2]
0.4
V
2.2
VCC
+0.5V
V
0.8
–0.5
0.8
V
–0.5
+0.5
–0.5
+0.5
µA
–0.5
+0.5
–0.5
+0.5
µA
L-Comm’l/
Ind’l
25
50
mA
LL-Comm’l
25
50
mA
LL - Ind’l
25
50
25
50
mA
LL - Auto-A
25
50
25
50
mA
LL - Auto-E
25
50
mA
L
LL-Comm’l
0.4
0.6
mA
0.3
0.5
mA
LL - Ind’l
0.3
0.5
0.3
0.5
mA
LL - Auto-A
0.3
0.5
0.3
0.5
mA
LL - Auto-E
0.3
0.5
mA
L
LL-Comm’l
2
50
µA
0.1
5
µA
LL - Ind’l
0.1
10
0.1
10
µA
LL - Auto-A
0.1
10
0.1
10
µA
LL - Auto-E
0.1
15
µA
Capacitance[8]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
6
pF
8
pF
Notes:
3. VIL (min.) = −2.0V for pulse durations of less than 20 ns.
4. TA is the “Instant-On” case temperature.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06511 Rev. *A
Page 3 of 13
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CY62256N
Thermal Resistance[5]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
DIP
SOIC
TSOP
RTSOP
Unit
Still Air, soldered on a 4.25 x 1.125
inch, 4-layer printed circuit board
75.61
76.56
93.89
93.89
°C/W
43.12
36.07
24.64
24.64
°C/W
AC Test Loads and Waveforms
R1 1800Ω
R1 1800Ω
5V
5V
OUTPUT
OUTPUT
R2
990Ω
100 pF
INCLUDING
JIG AND
SCOPE
ALL INPUT PULSES
3.0V
INCLUDING
JIG AND
SCOPE
(a)
R2
990Ω
5 pF
90%
10%
90%
10%
GND
< 5 ns
< 5 ns
(b)
Equivalent to:
THÉVENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Data Retention Characteristics
Parameter
Conditions[6]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Min.
Typ.[2]
Max.
Unit
2
50
µA
2.0
L
LL-Comm’l
V
VCC = 2.0V, CE > VCC − 0.3V,
VIN > VCC − 0.3V, or VIN < 0.3V
LL - Ind’l/Auto-A
LL - Auto-E
tCDR[8]
Chip Deselect to Data Retention Time
tR[8]
Operation Recovery Time
0.1
5
µA
0.1
10
µA
0.1
10
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
tCDR
VDR > 2V
3.0V
tR
CE
Note:
6. No input may exceed VCC + 0.5V.
Document #: 001-06511 Rev. *A
Page 4 of 13
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CY62256N
Switching Characteristics Over the Operating Range[7]
CY62256N-55
Parameter
Description
Min.
Max.
CY62256N-70
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
25
ns
55
OE LOW to Low-Z
tHZOE
OE HIGH to High-Z[8, 9]
tLZCE
CE LOW to Low-Z[8]
70
5
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
ns
5
High-Z[8, 9]
20
0
ns
25
0
55
ns
ns
5
20
CE HIGH to
ns
5
5
tHZCE
Write Cycle
5
[8]
tLZOE
70
ns
ns
70
ns
[10, 11]
tWC
Write Cycle Time
tSCE
CE LOW to Write End
45
60
ns
tAW
Address Set-up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
50
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
tLZWE
WE LOW to
High-Z[8, 9]
WE HIGH to
Low-Z[8]
55
70
20
5
ns
25
5
ns
ns
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Notes:
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can
terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
12. Device is continuously selected. OE, CE = VIL.
13. WE is HIGH for Read cycle.
Document #: 001-06511 Rev. *A
Page 5 of 13
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CY62256N
Switching Waveforms (continued)
Read Cycle No. 2[13, 14]
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
DATA I/O
NOTE 17
tHD
DATAIN VALID
tHZOE
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATAIN VALID
Notes:
14. Address valid prior to or coincident with CE transition LOW.
15. Data I/O is high impedance if OE = VIH.
16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
17. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 001-06511 Rev. *A
Page 6 of 13
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CY62256N
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tSD
DATA I/O
NOTE 17
tHZWE
Document #: 001-06511 Rev. *A
tHD
DATAIN VALID
tLZWE
Page 7 of 13
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CY62256N
Typical DC and AC Characteristics
1.4
1.0
0.8
0.6
VIN = 5.0V
TA = 25°C
0.4
2.5
1.0
2.0
0.8
0.6
VCC = 5.0V
VIN = 5.0V
0.4
4.5
5.0
5.5
25
SUPPLY VOLTAGE (V)
1.3
1.4
NORMALIZED tAA
NORMALIZED tAA
1.6
1.2
1.1
TA = 25°C
1.0
0.9
5.5
6.0
1.2
1.0
VCC = 5.0V
0.6
−55
25
125
OUTPUT SOURCE CURRENT (mA)
105
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
60
VCC = 5.0V
TA = 25°C
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
25
AMBIENT TEMPERATURE (°C)
0.8
5.0
–0.5
−55
125
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
4.5
VCC = 5.0V
VIN = 5.0V
AMBIENT TEMPERATURE (°C)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
0.8
4.0
1.0
0.0
0.0
−55
6.0
ISB
1.5
0.5
0.2
ISB
0.0
4.0
1.2
OUTPUT SINK CURRENT (mA)
0.2
3.0
ICC
ISB2 µA
1.2
NORMALIZED ICC
NORMALIZED ICC, ISB
1.4
ICC
STANDBY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
VCC = 5.0V
TA = 25°C
60
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Document #: 001-06511 Rev. *A
Page 8 of 13
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CY62256N
Typical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5
25.0
2.0
1.5
1.0
0.5
0.0
0.0
20.0
15.0
VCC = 4.5V
TA = 25°C
10.0
5.0
1.0
2.0
3.0
4.0
5.0
0.0
NORMALIZED ICC vs. CYCLE TIME
1.25
0
SUPPLY VOLTAGE (V)
200
400
600
800 1000
CAPACITANCE (pF)
NORMALIZED ICC
3.0
DELTA tAA (ns)
NORMALIZED IPO
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
1.00
VCC = 5.0V
TA = 25°C
VIN = 5.0V
0.75
0.50
10
20
30
40
CYCLE FREQUENCY (MHz)
Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High-Z
Deselect/Power-down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High-Z
Output Disabled
Active (ICC)
Document #: 001-06511 Rev. *A
Page 9 of 13
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CY62256N
Ordering Information
Speed
(ns)
55
Ordering Code
Package
Diagram
CY62256NLL−55SNI
51-85092
CY62256NLL−55SNXI
CY62256NLL−55ZI
28-lead (300-Mil) Narrow SOIC
Operating
Range
Industrial
28-lead (300-Mil) Narrow SOIC (Pb-Free)
51-85071
CY62256NLL−55ZXI
70
Package Type
28-lead TSOP I
28-lead TSOP I (Pb-Free)
CY62256NLL−55ZXA
51-85071
28-lead TSOP I (Pb-Free)
Automotive-A
CY62256NLL−55SNXE
51-85092
28-lead (300-Mil) Narrow SOIC (Pb-Free)
Automotive-E
CY62256NLL−55ZXE
51-85071
28-lead TSOP I (Pb-Free)
CY62256NLL−55ZRXE
51-85074
28-lead Reverse TSOP I (Pb-Free)
CY62256NL−70PC
51-85017
CY62256NL−70PXC
28-lead (600-Mil) Molded DIP
CY62256NLL−70PC
28-lead (600-Mil) Molded DIP
CY62256NLL−70PXC
28-lead (600-Mil) Molded DIP (Pb-Free)
CY62256NL−70SNC
51-85092
CY62256NL−70SNXC
28-lead (300-Mil) Narrow SOIC
28-lead (300-Mil) Narrow SOIC (Pb-Free)
CY62256NLL−70SNC
28-lead (300-Mil) Narrow SOIC
CY62256NLL−70SNXC
28-lead (300-Mil) Narrow SOIC (Pb-Free)
CY62256NLL−70ZC
51-85071
CY62256NLL−70ZXC
CY62256NL–70SNI
28-lead TSOP I
28-lead TSOP I (Pb-Free)
51-85092
CY62256NL–70SNXI
28-lead (300-Mil) Narrow SOIC
28-lead (300-Mil) Narrow SOIC
CY62256NLL−70SNXI
28-lead (300-Mil) Narrow SOIC (Pb-Free)
51-85071
CY62256NLL−70ZXI
CY62256NLL−70ZRI
28-lead TSOP I
28-lead TSOP I (Pb-Free)
51-85074
CY62256NLL−70ZRXI
CY62256NLL−70SNXA
Industrial
28-lead (300-Mil) Narrow SOIC (Pb-Free)
CY62256NLL−70SNI
CY62256NLL−70ZI
Commercial
28-lead (600-Mil) Molded DIP (Pb-Free)
28-lead Reverse TSOP I
28-lead Reverse TSOP I (Pb-Free)
51-85092
28-lead (300-Mil) Narrow SOIC (Pb-Free)
Automotive-A
Please contact your local Cypress sales representative for availability of these parts
Document #: 001-06511 Rev. *A
Page 10 of 13
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CY62256N
Package Diagrams
28-lead (600-Mil) Molded DIP (51-85017)
14
MIN.
MAX.
DIMENSIONS IN INCHES
REFERENCE JEDEC Ms-020
1
0.530
0.550
15
28
0.070
0.090
SEATING PLANE
1.380
1.480
0.140
0.195
0.155
0.200
0.115
0.160
0.009
0.012
0.015
0.060
0.090
0.110
0.055
0.065
0.600
0.625
0.014
0.022
3° MIN.
0.610
0.700
51-85017-*B
28-lead (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
Document #: 001-06511 Rev. *A
Page 11 of 13
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CY62256N
Package Diagrams (continued)
28-lead TSOP I (8 x 13.4 mm) (51-85071)
51-85071-*G
28-Lead RTSOP I (8 x 13.4 mm) (51-85074)
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 001-06511 Rev. *A
Page 12 of 13
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62256N
Document History Page
Document Title: CY62256N 256K (32K x 8) Static RAM
Document Number: 001- 06511
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
426504
See ECN
NXR
New Data Sheet
*A
488954
See ECN
NXR
Added Automotive product
Updated ordering Information table
Document #: 001-06511 Rev. *A
Description of Change
Page 13 of 13
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