CY7C1046BN 1M x 4 Static RAM Features You write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four IO pins (IO0 through IO3) is then written into the location specified on the address pins (A0 through A19). • Low active power — 825 mW (max) • Low CMOS standby power • • • • • — 44 mW (max) 2.0V data retention (400 μW at 2.0V retention) Automatic power down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in non Pb-free 400 mil wide 32-pin SOJ package Functional Description The CY7C1046BN is a high performance CMOS static RAM organized as 1,048,576 words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. You read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the IO pins. The four input and output pins (IO0 through IO3) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or when the write operation is active (CE LOW, and WE LOW). The CY7C1046BN is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolutionary) pinout. Logic Block Diagram Pin Configuration SOJ TOP VIEW INPUT BUFFER ROW DECODER IO 0 1M x 4 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A0 A1 A2 A3 A4 CE IO0 VCC GND IO1 WE A5 A6 A7 A8 A9 IO 1 IO 2 IO 3 COLUMN DECODER CE POWER DOWN 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A19 A18 A17 A16 A15 OE IO3 GND VCC IO2 A14 A13 A12 A11 A10 NC WE 1046B–1 A 11 A 12 A 13 A14 A15 A16 A17 A18 A19 OE 1046B–2 Selection Guide 7C1046BN-15 Maximum Access Time (ns) 15 Maximum Operating Current (mA) 150 Maximum CMOS Standby Current (mA) Cypress Semiconductor Corporation Document #: 001-11924 Rev. ** 8 • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 30, 2006 [+] Feedback CY7C1046BN Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (in accordance with MIL-STD-883, Method 3015) Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Latch-Up Current ..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC Relative to GND[1] .... –0.5V to +7.0V Range DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V Commercial DC Input Voltage[1] Ambient Temperature[2] VCC 0°C to +70°C 4.5V–5.5V .................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C1046BN-15 Min VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage Voltage[1] Max Unit 2.4 V 0.4 V 2.2 VCC + 0.3 V –0.3 0.8 V VIL Input LOW IIX Input Load Current GND < VI < VCC –1 +1 mA IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 mA ICC VCC Operating Supply Current VCC = Max, f = fMAX = 1/tRC 150 mA ISB1 Automatic CE Power Down Current – TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX 20 mA ISB2 Automatic CE Power Down Current – CMOS Inputs Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 8 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT IO Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max Unit 6 pF 6 pF Notes 1. VIL (min) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-11924 Rev. ** Page 2 of 9 [+] Feedback CY7C1046BN AC Test Loads and Waveforms R1 481Ω 5V 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) Vcc 90% OUTPUT R2 255 Ω ALL INPUT PULSES R1 481 Ω GND R2 255 Ω 5 pF INCLUDING JIG AND SCOPE (b) 90%VCC 10% 10%VCC Fall Time:1 V/ns Rise Time:1 V/ns 1046B–4 1046B–3 THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Equivalent to: Switching Characteristics (over the operating range)[4] 7C1046BN-15 Parameter Description Min Max Unit READ CYCLE tpower VCC(typ) to the First Access[5] 1 μs tRC Read Cycle Time 15 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 15 ns tDOE OE LOW to Data Valid 7 ns tLZOE tHZOE OE LOW to Low-Z[7] OE HIGH to High-Z[6, 7] Low-Z[7] tLZCE CE LOW to tHZCE CE HIGH to High-Z[6, 7] tPU CE LOW to Power Up tPD CE HIGH to Power Down 15 3 ns ns 0 ns 7 3 ns ns 7 0 ns ns 15 ns Notes 4. Test conditions are based on signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tPOWER is the time that the power needs to be supplied above VCC (typ) initially before a Read or Write operation can be initiated. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. Document #: 001-11924 Rev. ** Page 3 of 9 [+] Feedback CY7C1046BN Switching Characteristics (over the operating range)[4] (continued) 7C1046BN-15 Parameter Description Min Max Unit [8, 9] WRITE CYCLE tWC Write Cycle Time 15 ns tSCE CE LOW to Write End 10 ns tAW Address Setup to Write End 10 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 10 ns tSD Data Setup to Write End 8 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE WE HIGH to Low-Z[7] WE LOW to High-Z[6, 7] 7 ns Data Retention Characteristics (over the operating range) Parameter Conditions[10] Description Min VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time CE > VCC – 0.3V tR Operation Recovery Time VIN > VCC – 0.3V or VIN < 0.3V Max Unit 2.0 Com’l VCC = VDR = 2.0V, V 200 μA 0 ns 200 μs Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR VDR > 2V 3.0V tR CE 1046B–5 Notes 8. The internal memory write time is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data setup and hold timing must be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for write cycle 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 10. No input may exceed VCC + 0.5V. Document #: 001-11924 Rev. ** Page 4 of 9 [+] Feedback CY7C1046BN Switching Waveforms Read Cycle 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT DATA VALID PREVIOUS DATA VALID 1046B–6 Read Cycle 2 (OE controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE V CC HIGH IMPEDANCE DATA VALID tPD tPU SUPPLY tHZCE 50% CURRENT ICC 50% ISB 1046B–7 Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid before or similar to CE transition LOW. Document #: 001-11924 Rev. ** Page 5 of 9 [+] Feedback CY7C1046BN Switching Waveforms (continued) Write Cycle 1 (CE controlled)[14, 15] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA IO tHD DATA VALID 1046B–8 Write Cycle 2 (WE controlled, OE HIGH during write)[14, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA IO tHD DATAIN VALID NOTE 16 tHZOE 1046B–9 Notes 14. Data IO is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 16. During this period the IOs are in the output state and input signals must not be applied. Document #: 001-11924 Rev. ** Page 6 of 9 [+] Feedback CY7C1046BN Switching Waveforms (continued) Write Cycle 3 (WE controlled, OE LOW)[15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA IO tHD DATA VALID NOTE 16 tLZWE tHZWE 1046B–10 Ordering Information Speed (ns) 15 Ordering Code CY7C1046BN-15VC Document #: 001-11924 Rev. ** Package Diagram 51-85033 Package Type 32-Pin (400-Mil) Molded SOJ Operating Range Commercial Page 7 of 9 [+] Feedback CY7C1046BN Package Diagram Figure 1. 32-pin (400-Mil) Molded SOJ, 51-85033 51-85033-*B All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-11924 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1046BN Document History Page Document Title: CY7C1046BN 1M x 4 Static RAM Document Number: 001-11924 REV. ECN NO. of Issue Date Orig. Change Description of Change ** 610496 See ECN New data sheet Document #: 001-11924 Rev. ** NXR Page 9 of 9 [+] Feedback