CYPRESS CY7C1351G

CY7C1351G
4-Mbit (128 K × 36) Flow-Through SRAM
with NoBL™ Architecture
4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description
■
Can support up to 133-MHz bus operations with zero wait
states
❐ Data is transferred on every clock
■
Pin compatible and functionally equivalent to ZBT™ devices
■
Internally self-timed output buffer control to eliminate the need
to use OE
■
Registered inputs for flow-through operation
■
Byte write capability
■
128 K × 36 common I/O architecture
■
2.5 V/3.3 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 6.5 ns (for 133-MHz device)
■
Clock enable (CEN) pin to suspend operation
■
Synchronous self-timed writes
■
Asynchronous output enable
■
Available in Pb-free 100-pin TQFP package
■
Burst capability – linear or interleaved burst order
■
Low standby power
The CY7C1351G is a 3.3 V, 128 K × 36 synchronous
flow-through burst SRAM designed specifically to support
unlimited true back-to-back read/write operations without the
insertion of wait states. The CY7C1351G is equipped with the
advanced No Bus Latency™ (NoBL™) logic required to enable
consecutive Read/Write operations with data being transferred
on every clock cycle. This feature dramatically improves the
throughput of data through the SRAM, especially in systems that
require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the four byte write select
(BW[A:D]) and a write enable (WE) input. All writes are conducted
with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. In order to avoid bus
contention, the output drivers are synchronously tristated during
the data portion of a write sequence.
Selection Guide
Description
Maximum access time
Maximum operating current
Maximum CMOS standby current
Cypress Semiconductor Corporation
Document Number: 38-05513 Rev. *K
•
198 Champion Court
•
133 MHz
100 MHz
Unit
6.5
225
40
8.0
205
40
ns
mA
mA
San Jose, CA 95134-1709
•
408-943-2600
Revised October 5, 2012
CY7C1351G
Logic Block Diagram
ADDRESS
REGISTER
A0, A1, A
A1
D1
A0
D0
MODE
CLK
CEN
C
CE
ADV/LD
C
BURST
LOGIC
Q1 A1'
A0'
Q0
WRITE ADDRESS
REGISTER
ADV/LD
BWA
BWB
BWC
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWD
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
WE
OE
CE1
CE2
CE3
ZZ
Document Number: 38-05513 Rev. *K
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQs
DQPA
DQPB
DQPC
DQPD
E
INPUT
E
REGISTER
READ LOGIC
SLEEP
Control
Page 2 of 20
CY7C1351G
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Burst Read Accesses .................................................. 6
Single Write Accesses ................................................. 6
Burst Write Accesses .................................................. 6
Sleep Mode ................................................................. 7
Linear Burst Address Table ......................................... 7
Interleaved Burst Address Table ................................. 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Partial Truth Table for Read/Write .................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Electrical Characteristics ................................................. 9
Document Number: 38-05513 Rev. *K
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 20
Worldwide Sales and Design Support ....................... 20
Products .................................................................... 20
PSoC Solutions ......................................................... 20
Page 3 of 20
CY7C1351G
Pin Configurations
CLK
WE
CEN
OE
ADV/LD
90
89
88
87
86
85
44
45
46
47
48
49
50
A
A
A
A
A
A
A
43
42
NC/72M
NC/36M
41
VDD
A
VSS
91
40
39
NC/144M
VSS
38
36
A1
37
35
A
A0
34
NC/288M
33
A
Document Number: 38-05513 Rev. *K
81
VDD
92
82
CE3
93
NC/9M
BWA
94
A
BWB
95
83
BWC
96
84
BWD
97
NC/18M
CE1
CE2
98
A
A
BYTE D
32
NC
VSS
DQD
DQD
VDDQ
VSS
DQD
DQD
DQD
DQD
VSS
VDDQ
DQD
DQD
DQPD
A
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1351G
31
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
BYTE C
DQPC
DQC
DQC
VDDQ
VSS
DQC
DQC
DQC
DQC
VSS
VDDQ
DQC
DQC
99
100
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
DQPB
DQB
DQB
VDDQ
VSS
DQB
DQB
DQB
DQB
VSS
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
DQA
DQA
VSS
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
Page 4 of 20
CY7C1351G
Pin Definitions
Name
I/O
Description
A0, A1, A
InputAddress inputs used to select one of the 128 K address locations. Sampled at the rising edge of
synchronous the CLK. A[1:0] are fed to the two-bit burst counter.
BW[A:D]
InputByte write inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising
synchronous edge of CLK.
WE
InputWrite enable input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal
synchronous must be asserted LOW to initiate a write sequence.
ADV/LD
InputAdvance/load input. Used to advance the on-chip address counter or load a new address. When HIGH
synchronous (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be
loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to
load a new address.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is
only recognized if CEN is active LOW.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2,
synchronous and CE3 to select/deselect the device.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device.
OE
InputOutput enable, asynchronous input, active LOW. Combined with the synchronous logic block inside
asynchronous the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as
outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during
the data portion of a write sequence, during the first clock when emerging from a deselected state, when
the device has been deselected.
CEN
InputClock enable input, active LOW. When asserted LOW the clock signal is recognized by the SRAM.
synchronous When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device,
CEN can be used to extend the previous cycle when required.
ZZ
InputZZ “sleep” input. This active HIGH input places the device in a non-time critical “sleep” condition with data
asynchronous integrity preserved. During normal operation, this pin has to be low or left floating. ZZ pin has an internal
pull-down.
DQs
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
address during the clock rise of the read cycle. The direction of the pins is controlled by OE and the
internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQs and
DQP[A:D] are placed in a tristate condition. The outputs are automatically tristated during the data portion
of a write sequence, during the first clock when emerging from a deselected state, and when the device
is deselected, regardless of the state of OE.
DQP[A:D]
I/OBidirectional data parity I/O lines. Functionally, these signals are identical to DQs. During write
synchronous sequences, DQP[A:D] is controlled by BW[A:D] correspondingly.
MODE
VDD
VDDQ
Input
strap pin
Mode input. Selects the burst order of the device. When tied to GND selects linear burst sequence.
When tied to VDD or left floating selects interleaved burst sequence.
Power supply Power supply inputs to the core of the device.
I/O power
supply
VSS
Ground
NC
–
Power supply for the I/O circuitry.
Ground for the device.
No connects. Not Internally connected to the die.
Document Number: 38-05513 Rev. *K
Page 5 of 20
CY7C1351G
Pin Definitions (continued)
Name
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
I/O
Description
–
No connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins are not internally connected to the die.
Functional Overview
The CY7C1351G is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during write-read
transitions. All synchronous inputs pass through input registers
controlled by the rising edge of the clock. The clock signal is
qualified with the clock enable input signal (CEN). If CEN is
HIGH, the clock signal is not recognized and all internal states
are maintained. All synchronous operations are qualified with
CEN. Maximum access delay from the clock rise (tCDV) is 6.5 ns
(133-MHz device).
Accesses can be initiated by asserting all three chip enables
(CE1, CE2, CE3) active at the rising edge of the clock. If clock
enable (CEN) is active LOW and ADV/LD is asserted LOW, the
address presented to the device will be latched. The access can
either be a read or write operation, depending on the status of
the write enable (WE). BW[A:D] can be used to conduct byte write
operations.
Write operations are qualified by the write enable (WE). All writes
are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) simplify depth expansion. All
operations (reads, writes, and deselects) are pipelined. ADV/LD
should be driven LOW once the device has been deselected in
order to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, (3) the write enable input signal
WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The
address presented to the address inputs is latched into the
address register and presented to the memory array and control
logic. The control logic determines that a read access is in
progress and allows the requested data to propagate to the
output buffers. The data is available within 6.5 ns (133-MHz
device) provided OE is active LOW. After the first clock of the
read access, the output buffers are controlled by OE and the
internal control logic. OE must be driven LOW in order for the
device to drive out the requested data. On the subsequent clock,
another operation (read/write/deselect) can be initiated. When
the SRAM is deselected at clock rise by one of the chip enable
signals, its output will be tristated immediately.
Burst Read Accesses
The CY7C1351G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
reads without reasserting the address inputs. ADV/LD must be
Document Number: 38-05513 Rev. *K
driven LOW in order to load a new address into the SRAM, as
described in the Single Read Accesses section above. The
sequence of the burst counter is determined by the MODE input
signal. A LOW input on MODE selects a linear burst mode, a
HIGH selects an interleaved burst sequence. Both burst
counters use A0 and A1 in the burst sequence, and will wrap
around when incremented sufficiently. A HIGH input on ADV/LD
will increment the internal burst counter regardless of the state
of chip enable inputs or WE. WE is latched at the beginning of a
burst cycle. Therefore, the type of access (read or write) is
maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are all asserted active, and (3) the write signal WE is
asserted LOW. The address presented to the address bus is
loaded into the address register. The write signals are latched
into the control logic block. The data lines are automatically
tristated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQs and
DQP[A:D].
On the next clock rise the data presented to DQs and DQP[A:D]
(or a subset for byte write operations, see truth table for details)
inputs is latched into the device and the write is complete.
Additional accesses (read/write/deselect) can be initiated on this
cycle.
The data written during the write operation is controlled by
BW[A:D] signals. The CY7C1351G provides byte write capability
that is described in the truth table. Asserting the write enable
input (WE) with the selected byte write select input will selectively
write to only the desired bytes. Bytes not selected during a byte
write operation will remain unaltered. A synchronous self-timed
write mechanism has been provided to simplify the write
operations. Byte write capability has been included in order to
greatly simplify read/modify/write sequences, which can be
reduced to simple byte write operations.
Because the CY7C1351G is a common I/O device, data should
not be driven into the device while the outputs are active. The
output enable (OE) can be deasserted HIGH before presenting
data to the DQs and DQP[A:D] inputs. Doing so will tristate the
output drivers. As a safety precaution, DQs and DQP[A:D].are
automatically tristated during the data portion of a write cycle,
regardless of the state of OE.
Burst Write Accesses
The CY7C1351G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to four
Page 6 of 20
CY7C1351G
Write operations without reasserting the address inputs. ADV/LD
must be driven LOW in order to load the initial address, as
described in the Single Write Accesses section above. When
ADV/LD is driven HIGH on the subsequent clock rise, the chip
enables (CE1, CE2, and CE3) and WE inputs are ignored and the
burst counter is incremented. The correct BW[A:D] inputs must be
driven in each cycle of the burst write, in order to write the correct
bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
and CE3, must remain inactive for the duration of tZZREC after the
ZZ input returns LOW.
Linear Burst Address Table
(MODE = GND)
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
10
11
00
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
00
01
10
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1:A0
00
01
10
11
Second
Address
A1:A0
01
00
11
10
Third
Address
A1:A0
10
11
00
01
Fourth
Address
A1:A0
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
Document Number: 38-05513 Rev. *K
Test Conditions
ZZ > VDD 0.2 V
ZZ > VDD  0.2 V
ZZ < 0.2 V
This parameter is sampled
This parameter is sampled
Min
–
–
2tCYC
–
0
Max
40
2tCYC
–
2tCYC
–
Unit
mA
ns
ns
ns
ns
Page 7 of 20
CY7C1351G
Truth Table
The truth table for CY7C1351G follows. [1, 2, 3, 4, 5, 6, 7]
Operation
Address Used CE1 CE2 CE3 ZZ ADV/LD WE BWX OE CEN CLK
DQ
Deselect cycle
None
H
X
X
L
L
X
X
X
L
L->H
Tristate
Deselect cycle
None
X
X
H
L
L
X
X
X
L
L->H
Tristate
Deselect cycle
None
X
L
X
L
L
X
X
X
L
L->H
Tristate
Continue deselect cycle
None
X
X
X
L
H
X
X
X
L
L->H
Tristate
External
L
H
L
L
L
H
X
L
L
L->H Data out (Q)
Next
X
X
X
L
H
X
X
L
L
L->H Data out (Q)
External
L
H
L
L
L
H
X
H
L
L->H
Tristate
Next
X
X
X
L
H
X
X
H
L
L->H
Tristate
READ cycle (begin burst)
READ cycle (continue burst)
NOP/DUMMY READ (begin burst)
DUMMY READ (continue burst)
WRITE cycle (begin burst)
External
L
H
L
L
L
L
L
X
L
L->H Data in (D)
WRITE cycle (continue burst)
Next
X
X
X
L
H
X
L
X
L
L->H Data in (D)
NOP/WRITE ABORT (begin burst)
None
L
H
L
L
L
L
H
X
L
L->H
Tristate
WRITE ABORT (continue burst)
Next
X
X
X
L
H
X
H
X
L
L->H
Tristate
IGNORE CLOCK EDGE (stall)
SLEEP MODE
Current
X
X
X
L
X
X
X
X
H
L->H
–
None
X
X
X
H
X
X
X
X
X
X
Tristate
Partial Truth Table for Read/Write
The Partial Truth Table for Read/Write for CY7C1351G follows. [1, 2, 8]
Function
WE
BWA
BWB
BWC
BWD
Read
H
X
X
X
X
Read
H
X
X
X
X
Write – no bytes written
L
H
H
H
H
Write byte A – (DQA and DQPA)
L
L
H
H
H
Write byte B – (DQB and DQPB)
L
H
L
H
H
Write byte C – (DQC and DQPC)
L
H
H
L
H
Write byte D – (DQD and DQPD)
L
H
H
H
L
Write all bytes
L
L
L
L
L
Notes
1. X = Don’t Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one byte write select is active, BWx = valid signifies that the desired byte write selects
are asserted, see truth table for details.
2. Write is defined by BWX, and WE. See truth table for read/write.
3. When a write cycle is detected, all I/Os are tristated, even during byte writes.
4. The DQs and DQP[A:D] pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CEN = H, inserts wait states.
6. Device will power-up deselected and the I/Os in a tristate condition, regardless of OE.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP[A:D] = tristate when OE is
inactive or when the device is deselected, and DQs and DQP[A:D] = data when OE is active.
8. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.
Document Number: 38-05513 Rev. *K
Page 8 of 20
CY7C1351G
Maximum Ratings
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Ambient temperature with
power applied .......................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Latch up current ..................................................... > 200 mA
Operating Range
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
Range
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
Ambient
Temperature (TA)
Commercial
0 °C to +70 °C
VDD
VDDQ
3.3 V – 5% / 2.5 V – 5% to
+ 10%
VDD
Electrical Characteristics
Over the Operating Range
Parameter [9, 10]
Description
Test Conditions
VDD
Power supply voltage
VDDQ
I/O supply voltage
VOH
Output HIGH voltage
For 3.3 V I/O, IOH = –4.0 mA
For 2.5 V I/O, IOH = –1.0 mA
VOL
Output LOW voltage
For 3.3 V I/O, IOL= 8.0 mA
VIH
Input HIGH voltage
Input HIGH voltage
VIL
Input LOW voltage[9]
voltage[9]
For 2.5 V I/O
Min
Unit
3.135
3.6
V
For 3.3 V I/O
3.135
VDD
V
For 2.5 V I/O
2.375
2.625
V
2.4
–
V
2.0
–
V
–
0.4
V
For 2.5 V I/O, IOL= 1.0 mA
Input LOW
Max
–
0.4
V
2.0
VDD + 0.3
V
For 2.5 V I/O
1.7
VDD + 0.3
V
For 3.3 V I/O
–0.3
0.8
V
For 3.3 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND < VI < VDDQ
and MODE
5
5
A
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input current of ZZ
Input = VSS
–5
–
A
Input = VDD
–
30
A
IOZ
Output leakage current
GND < VI < VDDQ, output disabled
–5
5
A
IDD
VDD operating supply current
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
7.5-ns cycle,
133 MHz
–
225
mA
10-ns cycle,
100 MHz
–
205
mA
7.5-ns cycle,
133 MHz
–
90
mA
10-ns cycle,
100 MHz
–
80
mA
–
40
mA
IX
ISB1
ISB2
Automatic CE power-down
current – TTL inputs
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected,
VIN > VIH or VIN  VIL, f = fMAX,
inputs switching
VDD = Max, device deselected, All speeds
VIN > VDD – 0.3 V or VIN < 0.3 V,
f = 0, inputs static
Notes
9. Overshoot: VIH(AC) < VDD +1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0 V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05513 Rev. *K
Page 9 of 20
CY7C1351G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [9, 10]
ISB3
Description
Automatic CE power-down
current – CMOS inputs
Automatic CE power-down
current – TTL inputs
ISB4
Test Conditions
Min
Max
Unit
VDD = Max, device deselected, 7.5-ns cycle,
VIN > VDDQ – 0.3 V or VIN < 0.3 V, 133 MHz
f = fMAX, inputs switching
10-ns cycle,
100 MHz
–
75
mA
–
65
mA
–
45
mA
VDD = Max, device deselected,
VIN > VIH or V IN < VIL,
f = 0, inputs static
All speeds
Capacitance
Parameter [11]
Description
CIN
Input capacitance
CCLOCK
Clock input capacitance
CI/O
I/O capacitance
100-pin TQFP
Max
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
30.32
°C/W
6.85
°C/W
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V, VDDQ=3.3 V
Thermal Resistance
Parameter [11]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Note
11. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05513 Rev. *K
Page 10 of 20
CY7C1351G
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 
3.3 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
GND
5 pF
R = 351 
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
 1ns
 1ns
(c)
(b)
2.5 V I/O Test Load
R = 1667 
2.5 V
OUTPUT
OUTPUT
RL = 50 
Z0 = 50 
GND
5 pF
R = 1538 
VT = 1.25 V
(a)
Document Number: 38-05513 Rev. *K
ALL INPUT PULSES
VDDQ
INCLUDING
JIG AND
SCOPE
(b)
10%
90%
10%
90%
 1ns
 1ns
(c)
Page 11 of 20
CY7C1351G
Switching Characteristics
Over the Operating Range
Parameter [12, 13]
tPOWER
Description
VDD(typical) to the first access [14]
-133
-100
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
10
–
ns
tCH
Clock HIGH
2.5
–
4.0
–
ns
tCL
Clock LOW
2.5
–
4.0
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
–
8.0
ns
tDOH
Data output hold after CLK rise
2.0
–
2.0
–
ns
[15, 16, 17]
0
–
0
–
ns
tCHZ
Clock to high Z
15, 16, 17]
–
3.5
–
3.5
ns
tOEV
OE LOW to output valid
–
3.5
–
3.5
ns
0
–
0
–
ns
–
3.5
–
3.5
ns
tCLZ
tOELZ
tOEHZ
Clock to low Z
OE LOW to output low Z
[15, 16, 17]
OE HIGH to output high Z
[15, 16, 17]
Set-up Times
tAS
Address set-up before CLK rise
1.5
–
2.0
–
ns
tALS
ADV/LD set-up before CLK rise
1.5
–
2.0
–
ns
tWES
WE, BWX set-up before CLK rise
1.5
–
2.0
–
ns
tCENS
CEN set-up before CLK rise
1.5
–
2.0
–
ns
tDS
Data input set-up before CLK rise
1.5
–
2.0
–
ns
tCES
Chip enable set-up before CLK rise
1.5
–
2.0
–
ns
tAH
Address hold after CLK rise
0.5
–
0.5
–
ns
tALH
ADV/LD hold after CLK rise
0.5
–
0.5
–
ns
tWEH
WE, BWX hold after CLK rise
0.5
–
0.5
–
ns
tCENH
CEN hold after CLK rise
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
0.5
–
ns
Hold Times
Notes
12. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
13. Test conditions shown in (a) of Figure 2 on page 11, unless otherwise noted.
14. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
15. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage.
16. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
tristate prior to low Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document Number: 38-05513 Rev. *K
Page 12 of 20
CY7C1351G
Switching Waveforms
Figure 3. Read/Write Waveforms [18, 19, 20]
1
2
3
tCYC
4
5
6
7
8
9
A5
A6
A7
10
CLK
tCENS
tCENH
tCES
tCEH
tCH
tCL
CEN
CE
ADV/LD
WE
BW[A:D]
A1
ADDRESS
tAS
A2
A4
A3
tCDV
tAH
tDOH
tCLZ
DQ
D(A1)
tDS
D(A2)
Q(A3)
D(A2+1)
tOEV
Q(A4+1)
Q(A4)
tDH
tOELZ
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tOEHZ
OE
COMMAND
tCHZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
DON’T CARE
BURST
READ
Q(A4+1)
tDOH
WRITE
D(A5)
READ
Q(A6)
UNDEFINED
Notes
18. For this waveform ZZ is tied LOW.
19. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20. Order of the burst sequence is determined by the status of the MODE (0 = Linear, 1 = Interleaved). Burst operations are optional.
Document Number: 38-05513 Rev. *K
Page 13 of 20
CY7C1351G
Switching Waveforms (continued)
Figure 4. NOP, STALL and DESELECT Cycles [21, 22, 23]
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CEN
CE
ADV/LD
WE
BW[A:D]
ADDRESS
A5
tCHZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
tDOH
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
DON’T CARE
STALL
NOP
READ
Q(A5)
DESELECT
CONTINUE
DESELECT
UNDEFINED
Figure 5. ZZ Mode Timing [24, 25]
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
21. For this waveform ZZ is tied LOW.
22. When CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
23. The IGNORE CLOCK EDGE or STALL cycle (Clock 3) illustrates CEN being used to create a pause. A write is not performed during this cycle.
24. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device.
25. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05513 Rev. *K
Page 14 of 20
CY7C1351G
Ordering Information
Cypress offers other versions of this type of product in many different configurations and features. The following table contains only
the list of parts that are currently available.
For a complete listing of all options, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products or contact your local sales representative.
Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Speed
(MHz)
Package
Diagram
Ordering Code
Part and Package Type
100
CY7C1351G-100AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
133
CY7C1351G-133AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Commercial
Ordering Code Definitions
CY 7
C
1351
G - XXX
A
X C
Temperature Range:
C = Commercial = 0 °C to 70 °C
X = Pb-free; X Absent = Leaded
Package Type:
A = 100-pin TQFP
Speed Grade: XXX = 100 MHz or 133 MHz
Process Technology: G 90 nm
Part Identifier: 1351 = FT, 128 Kb × 18 (2 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05513 Rev. *K
Page 15 of 20
CY7C1351G
Package Diagrams
Figure 6. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
51-85050 *D
Document Number: 38-05513 Rev. *K
Page 16 of 20
CY7C1351G
Acronyms
Document Conventions
Acronym
Description
Units of Measure
CMOS
complementary metal oxide semiconductor
CE
chip enable
°C
degree Celsius
CEN
clock enable
MHz
megahertz
EIA
electronics industries alliance
µA
microampere
I/O
input/output
mA
milliampere
JEDEC
joint electron devices engineering council
mm
millimeter
NoBL
no bus latency
ms
millisecond
OE
output enable
ns
nanosecond
SRAM
static random access memory
%
percent
TQFP
thin quad flat pack
pF
picofarad
TTL
transistor-transistor logic
V
volt
WE
write enable
W
watt
Document Number: 38-05513 Rev. *K
Symbol
Unit of Measure
Page 17 of 20
CY7C1351G
Document History Page
Document Title: CY7C1351G, 4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05513
Rev.
ECN No.
Issue Date
Orig. of
Change
Description of Change
**
224360
See ECN
RKF
New data sheet.
*A
276690
See ECN
VBL
Deleted 66 MHz
Updated Ordering Information (Changed TQFP package in Ordering
Information section to lead-free TQFP, added comment of availability of BG
lead-free package).
*B
333626
See ECN
SYT
Updated Features (Removed 117 MHz frequency related information).
Updated Selection Guide (Removed 117 MHz frequency related information).
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 100-pin TQFP and 119-ball BGA Packages as per JEDEC standards).
Updated Pin Definitions.
Updated Functional Overview (Updated ZZ Mode Electrical Characteristics
(Replaced “Snooze” with “Sleep”)).
Updated Electrical Characteristics (Updated Test Conditions of VOL, VOH
parameters, removed 117 MHz frequency related information).
Updated Truth Table (Replaced “Snooze” with “Sleep”).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to respective Thermal Values for all Packages).
Updated Switching Characteristics (Removed 117 MHz frequency related
information).
Updated Ordering Information (By shading and unshading MPNs as per
availability, changed the package name for 100-pin TQFP from A100RA to
A101).
*C
418633
See ECN
RXU
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Updated Note 10 (Modified test condition
from VDDQ < VDD to VDDQ < VDD), splitted VDDQ parameter into two rows (one
for 3.3 V I/O, another for 2.5 V I/O),
Updated Test Conditions of VOL, VOH parameters
(Changed Typo in Test Condition of VOH parameter
from “for 3.3 V I/O” to “for 3.3 V I/O, IOH = –4.0 mA” and
from “for 2.5 V I/O” to “for 2.5 V I/O, IOH = –1.0 mA”,
changed Typo in Test Condition of VOL parameter
from “for 3.3 V I/O, IOH = –4.0 mA” to “for 3.3 V I/O, IOH = 8.0 mA” and
from “for 2.5 V I/O, IOH = –1.0 mA” to “for 2.5 V I/O, IOH = 1.0 mA”),
updated Test Conditions of VIH parameter
(Changed Typo in Test Condition of VIH parameter
from “for 3.3 V I/O, IOH = 8.0 mA” to “for 3.3 V I/O” and
from “for 2.5 V I/O, IOH =1.0 mA” to “for 2.5 V I/O”),
changed “Input Load Current except ZZ and MODE” to “Input Leakage Current
except ZZ and MODE”,
updated Test Conditions of IX parameter
(Changed Typo in Test Condition of IX parameter (Corresponding to Input Load
Current except ZZ and MODE) from “for 3.3 V” to “GND  VI  VDDQ”,
changed Typo in Test Condition of IX parameter (Corresponding to Input
Current of Mode) from “for 2.5 V I/O and “GND  VI  VDDQ” to Input = VSS and
Input = VDD respectively),
updated Test Conditions of ISB4 parameter
(Changed Typo in Test Condition of ISB4 parameter from “VIN  VDDQ – 0.3 V
or VIN  0.3V” to “VIN  VIH or VIN  VIL”)).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Updated Package Diagrams (spec 51-85050 (changed revision from *A to *B)).
Document Number: 38-05513 Rev. *K
Page 18 of 20
CY7C1351G
Document History Page (continued)
Document Title: CY7C1351G, 4-Mbit (128 K × 36) Flow-Through SRAM with NoBL™ Architecture
Document Number: 38-05513
Rev.
ECN No.
Issue Date
Orig. of
Change
*D
480124
See ECN
VKN
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*E
2896584
03/20/2010
NJY
Updated Ordering Information (Removed obsolete part numbers from Ordering
Information table).
Updated Package Diagrams.
*F
3033272
09/19/2010
NJY
Added Ordering Code Definitions.
Added Acronyms and Units of Measure.
Minor edits and updated in new template.
*G
3067198
10/20/2010
NJY
Updated Ordering Information (Updated part numbers).
*H
3096309
11/28/2010
NJY
Updated Functional Description.
*I
3353119
08/24/2011
PRIT
Updated Functional Description (Updated the Note as “For best practice
recommendations, refer to SRAM System Guidelines.”).
Updated Package Diagrams (spec 51-85050 (changed revision from *C to *D)).
*J
3616656
05/14/2012
PRIT
Updated Features (Removed 119-ball BGA package related information).
Updated Functional Description (Removed the Note “For best practice
recommendations, refer to SRAM System Guidelines.” and its reference).
Updated Pin Configurations (Removed 119-ball BGA package related
information).
Updated Operating Range (Removed Industrial Temperature Range).
Updated Capacitance (Removed 119-ball BGA package related information).
Updated Thermal Resistance (Removed 119-ball BGA package related
information).
Updated Package Diagrams (Removed 119-ball BGA package related
information (spec 51-85115)).
*K
3767562
10/05/2012
PRIT
No technical updates. Completing sunset review.
Document Number: 38-05513 Rev. *K
Description of Change
Page 19 of 20
CY7C1351G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
psoc.cypress.com/solutions
cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
cypress.com/go/psoc
Touch Sensing
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2004-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05513 Rev. *K
Revised October 5, 2012
Page 20 of 20
ZBT is a trademark of Integrated Device Technology, Inc. NoBL and No Bus Latency are trademarks of Cypress Semiconductor. All products and company names mentioned in this document may be
the trademarks of their respective holders.