CY7C199D 256K (32K x 8) Static RAM Features Functional Description ■ Temperature ranges ❐ Industrial: –40°C to 85°C ❐ Automotive-E: –40°C to 125°C ■ Pin and function compatible with CY7C199C ■ High speed The CY7C199D is a high performance CMOS static RAM organized as 32,768 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE) and tri-state drivers. This device has an automatic power down feature, reducing the power consumption when deselected. The input and output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW and WE LOW). ❐ tAA ■ Low active power ❐ ICC ■ = 10 ns (Industrial) = 80 mA at 10 ns Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A14). Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0V Data Retention ■ Automatic power down when deselected ■ CMOS for optimum speed/power ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features ■ Available in Pb-free 28-pin 300-Mil wide Molded SOJ, 28-pin 300-Mil wide SOIC and 28-pin TSOP I packages Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appears on the IO pins. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Logic Block Diagram IO0 INPUT BUFFER IO1 32K x 8 ARRAY IO3 IO4 IO5 IO6 CE • IO7 POWER DOWN A14 A12 A13 A10 OE A11 COLUMN DECODER WE Cypress Semiconductor Corporation Document #: 38-05471 Rev. *E IO2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 28, 2009 [+] Feedback CY7C199D Pin Configuration Figure 1. 28-Pin SOJ (Top View) A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 IO0 IO1 IO2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE IO7 IO6 IO5 IO4 IO3 Figure 2. 28-Pin SOIC (Top View) A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 IO0 IO1 IO2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Figure 3. 28-Pin TSOP I (Top View) OE A1 A2 A3 A4 VCC WE A13 A8 A9 A11 OE A10 CE IO7 IO6 IO5 IO4 IO3 WE VCC A5 A6 A7 A8 A9 A10 A11 22 23 24 25 26 27 28 1 2 3 4 5 6 7 TSOP I Top View (not to scale) 21 20 19 18 17 16 15 14 13 12 11 10 9 8 A0 CE IO7 IO6 IO5 IO4 IO3 GND IO2 IO1 IO0 A14 A13 A12 Selection Guide -10 (Industrial) -25 (Automotive) [1] Unit Maximum Access Time 10 25 ns Maximum Operating Current 80 63 mA Maximum CMOS Standby Current 3 15 mA Description Note: 1. Automotive product information is preliminary Document #: 38-05471 Rev. *E Page 2 of 12 [+] Feedback CY7C199D Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Static Discharge Voltage......................................... > 2,001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage on VCC to Relative GND [2] ....–0.5V to +6.0V Range Ambient Temperature VCC Speed DC Voltage Applied to Outputs in High Z State [2] ................................... –0.5V to VCC + 0.5V Industrial –40°C to +85°C 5V ± 0.5V 10 ns Automotive-E –40°C to +125°C 5V ± 0.5V 25 ns DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range 7C199D-10 Parameter Description 7C199D-25 Test Conditions Unit Min VOH Output HIGH Voltage IOH=–4.0 mA VOL Output LOW Voltage IOL=8.0 mA VIH Input HIGH Voltage [2] VIL Input LOW Voltage [2] IIX Input Leakage Current IOZ ICC Max 2.4 Min Max 2.4 0.4 V 0.4 V 2.2 VCC + 0.5 2.2 VCC + 0.5 V –0.5 0.8 –0.5 0.8 V GND < VI < VCC –1 +1 –5 +5 μA Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 –5 +5 μA VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fmax = 1/tRC 100 MHz 80 – mA 83 MHz 72 – mA 66 MHz 58 – mA 40 MHz 37 63 mA ISB1 Automatic CE Power down Current— TTL Inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fmax 10 50 mA ISB2 Automatic CE Power down Current— CMOS Inputs Max VCC, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V, f=0 3 15 mA Note: 2. VIL(min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns. Document #: 38-05471 Rev. *E Page 3 of 12 [+] Feedback CY7C199D Capacitance [3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max TA = 25°C, f = 1 MHz, VCC = 5.0V Unit 8 pF 8 pF Thermal Resistance [3] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board SOJ TSOP I SOIC Unit 59.16 54.65 TBD °C/W 40.84 21.49 TBD °C/W AC Test Loads and Waveforms [4] Z = 50Ω ALL INPUT PULSES OUTPUT 3.0V 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 10% 30pF* 90% 10% 90% GND 1.5V Rise Time: ≤ 3 ns Fall Time: ≤ 3 ns (b) (a) High Z characteristics: R1 480Ω 5V OUTPUT R2 255Ω 5 pF INCLUDING JIG AND SCOPE (c) Notes: 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure (a). High Z characteristics are tested for all speeds using the test load shown in Figure (c). Document #: 38-05471 Rev. *E Page 4 of 12 [+] Feedback CY7C199D Switching Characteristics (Over the Operating Range) [5] 7C199D-10 Parameter 7C199D-25 Description Unit Min Max Min Max Read Cycle tpower [6] VCC(typical) to the first access 100 100 μs tRC Read Cycle Time 10 25 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 25 ns OE LOW to Data Valid 5 10 ns tDOE tLZOE [7] OE LOW to Low Z tHZOE [7, 8] OE HIGH to High Z [7] CE LOW to Low Z tLZCE tHZCE [7, 8] tPU [9] tPD [9] 10 3 3 ns 11 3 5 0 ns ns 11 0 10 ns ns 0 5 CE HIGH to Power down Write Cycle 3 0 CE HIGH to High Z CE LOW to Power up 25 ns ns 25 ns [10, 11] tWC Write Cycle Time 10 25 ns tSCE CE LOW to Write End 7 18 ns tAW Address Setup to Write End 7 18 ns tHA Address Hold from Write End 0 0 ns tSA Address Setup to Write Start 0 0 ns tPWE WE Pulse Width 7 18 ns tSD Data Setup to Write End 6 12 ns tHD Data Hold from Write End 0 0 ns tHZWE [7] tLZWE [7, 8] WE LOW to High Z WE HIGH to Low Z 5 3 11 3 ns ns Notes: 5. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of “AC Test Loads and Waveforms [4]” on page 4. Transition is measured ±200 mV from steady-state voltage. 9. This parameter is guaranteed by design and is not tested. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05471 Rev. *E Page 5 of 12 [+] Feedback CY7C199D Data Retention Characteristics (Over the Operating Range) Parameter Description VDR VCC for Data Retention ICCDR Data Retention Current tCDR [3] tR Conditions Min 2.0 VCC = VDR = 2.0V, CE > VCC – 0.3V, Industrial VIN > VCC – 0.3V or VIN < 0.3V Automotive-E Chip Deselect to Data Retention Time [12] Max Operation Recovery Time Unit V 3 mA 15 mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 4.5V 4.5V VDR > 2V tR tCDR CE Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [13, 14] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [14, 15] tRC CE tACE OE DATA OUT tDOE tLZOE HIGH IMPEDANCE tHZOE tHZCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 μs or stable at VCC(min) > 50 μs. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. Document #: 38-05471 Rev. *E Page 6 of 12 [+] Feedback CY7C199D Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [10, 16, 17] tWC ADDRESS tSCE CE tSA tAW tHA WE tSD DATA IO tHD DATA IN VALID Write Cycle No. 2 (WE Controlled) [10, 16, 17] tWC ADDRESS CE tAW tHA tSA WE tPWE OE tSD DATA IO NOTE 18 tHD DATAIN VALID tHZOE Write Cycle No. 3 (WE Controlled, OE LOW) [11, 17] tWC ADDRESS CE tAW tHA tSA WE tSD DATA IO NOTE 18 tHD DATAIN VALID tHZWE tLZWE Notes: 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 18. During this period the IOs are in the output state and input signals should not be applied. Document #: 38-05471 Rev. *E Page 7 of 12 [+] Feedback CY7C199D Truth Table CE WE OE H X X High Z Inputs/Outputs Deselect/Power down Mode Standby (ISB) Power L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Deselect, Output disabled Active (ICC) Ordering Information Speed (ns) 10 25 Ordering Code Package Diagram Operating Range Package Type CY7C199D-10VXI 51-85031 28-pin (300-Mil) Molded SOJ (Pb-Free) CY7C199D-10ZXI 51-85071 28-pin TSOP Type I (Pb-free) CY7C199D-25SXE 51-85026 28-pin (300-Mil) SOIC (Pb-Free) Industrial Automotive-E Please contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 4. 28-Pin (300-Mil) Molded SOJ NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE MIN. MAX. 3. DIMENSIONS IN INCHES DETAIL A EXTERNAL LEAD DESIGN PIN 1 ID 14 1 0.291 0.300 15 0.330 0.350 28 OPTION 1 0.697 0.713 A Document #: 38-05471 Rev. *E 0.014 0.020 OPTION 2 SEATING PLANE 0.120 0.140 0.050 TYP. 0.026 0.032 0.013 0.019 0.007 0.013 0.004 0.025 MIN. 0.262 0.272 51-85031-*C Page 8 of 12 [+] Feedback CY7C199D Package Diagrams (continued) Figure 5. 28-Pin (300-Mil) SOIC NOTE : PIN 1 ID 1. JEDEC STD REF MO-119 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH,BUT 14 DOES INCLUDE MOLD MISMATCH AND ARE MEASURED AT THE MOLD PARTING LINE. 1 MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.010 in (0.254 mm) PER SIDE 3. DIMENSIONS IN INCHES 0.291[7.39] MIN. MAX. 4. PACKAGE WEIGHT 0.85gms 0.300[7.62] 0.394[10.01] * 0.419[10.64] 15 28 PART # S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG. 0.026[0.66] 0.032[0.81] SEATING PLANE 0.697[17.70] 0.713[18.11] 0.092[2.33] 0.105[2.67] 0.004[0.10] 0.050[1.27] 0.013[0.33] 0.004[0.10] 0.019[0.48] 0.0118[0.30] * 0.015[0.38] 0.050[1.27] 0.0091[0.23] 0.0125[3.17] * TYP. 51-85026-*D Document #: 38-05471 Rev. *E Page 9 of 12 [+] Feedback CY7C199D Package Diagrams (continued) Figure 6. 28-Pin Thin Small Outline Package Type 1 (8x13.4 mm) 51-85071-*G Document #: 38-05471 Rev. *E Page 10 of 12 [+] Feedback CY7C199D Document History Page Document Title: CY7C199D 256K (32K x 8) Static RAM Document Number: 38-05471 Revision ECN Orig. of Change Submission Date Description of Change ** 201560 SWI See ECN Advance Information datasheet for C9 IPP *A 233728 RKF See ECN DC parameters modified as per EROS (Spec # 01-02165) Pb-free Offering in Ordering Information *B 262950 RKF See ECN Removed 28-LCC Pinout and Package Diagrams Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307594 RKF See ECN Reduced Speed bins to -10, -12 and -15 ns *D 820660 VKN See ECN Converted from Preliminary to Final Removed 12 ns and 15 ns speed bin Removed Commercial Operating range Removed “L” part Removed 28-pin PDIP and 28-pin SOIC package Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2 Changed ICC spec from 60 mA to 80 mA for 100 MHz speed bin Added ICC specs for 83 MHz, 66 MHz and 40 MHz speed bins Updated Thermal Resistance table Updated Ordering Information Table *E 2745093 VKN See ECN Included 28-Pin SOIC package Changed VIH level from 2.0V to 2.2V For Industrial grade, changed tSD from 5 ns to 6 ns, and tHZWE from 6 ns to 5 ns Included Automotive-E information Document #: 38-05471 Rev. *E Page 11 of 12 [+] Feedback CY7C199D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales Products PSoC Clocks & Buffers psoc.cypress.com clocks.cypress.com Wireless wireless.cypress.com Memories memory.cypress.com Image Sensors image.cypress.com © Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. 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Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05471 Rev. *E Revised July 28, 2009 Page 12 of 12 PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback