CY7C1019DV33 1-Mbit (128 K × 8) Static RAM 1-Mbit (128 K × 8) Static RAM Features Functional Description ■ Pin- and function-compatible with CY7C1019CV33 ■ High speed ❐ tAA = 10 ns ■ Low Active Power ❐ ICC = 60 mA @ 10 ns ■ Low CMOS Standby Power ❐ ISB2 = 3 mA ■ 2.0 V Data retention ■ Automatic power-down when deselected ■ CMOS for optimum speed/power ■ Center power/ground pinout ■ Easy memory expansion with CE and OE options ■ Available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages The CY7C1019DV33 is a high-performance CMOS static RAM organized as 131,072 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1019DV33 is available in Pb-free 32-pin 400-Mil wide Molded SOJ, 32-pin TSOP II and 48-ball VFBGA packages. Logic Block Diagram I/O0 INPUTBUFFER I/O1 128K × 8 ARRAY I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 I/O3 I/O4 I/O5 CE WE COLUMN DECODER I/O6 POWER DOWN I/O7 A9 A10 A11 A12 A13 A14 A15 A16 OE Cypress Semiconductor Corporation Document Number: 38-05481 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 20, 2011 [+] Feedback CY7C1019DV33 Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics ................................................ 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 Switching Waveforms ...................................................... 7 Truth Table ...................................................................... 10 Document Number: 38-05481 Rev. *F Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Package Diagrams .......................................................... 12 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16 Page 2 of 16 [+] Feedback CY7C1019DV33 Selection Guide -10 (Industrial) Unit Maximum Access Time 10 ns Maximum Operating Current 60 mA Maximum Standby Current 3 mA Pin Configurations Figure 1. 48-ball VFBGA (6 × 8 × 1 mm) (Top View) [1] 2 3 4 5 6 NC OE A2 A6 A7 NC A I/O0 NC A1 A5 CE I/O7 B I/O1 NC A0 A4 NC I/O6 C VSS NC NC A3 NC VCC D VCC NC NC NC NC VSS E I/O2 NC A14 A11 I/O4 I/O5 F I/O3 NC A15 A12 WE A8 G NC A10 A16 A13 A9 NC H 1 SOJ/TSOPI Top View A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Figure 2. 32-pin SOJ / TSOP II (Top View) A2 A6 A7 NC A A1 A5 CE I/O7 B A0 A4 NC I/O6 C NC A3 NC VCC D NC NC NC VSS E A14 A11 I/O4 I/O5 F A15 A12 WE A8 G A16 A13 A9 NC H A0 A1 A2 A3 CE I/O0 I/O1 VCC V SS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8 Note 1. NC pins are not connected on the die. Document Number: 38-05481 Rev. *F Page 3 of 16 [+] Feedback CY7C1019DV33 DC Input Voltage [2] ............................ –0.3 V to VCC + 0.3 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied ......................................... –55 C to +125 C Supply Voltage on VCC to Relative GND [2] ...............................–0.3 V to +4.6 V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (per MIL-STD-883, Method 3015) .......................... > 2001 V Latch-up Current .................................................... > 200 mA Operating Range DC Voltage Applied to Outputs in High Z State [2] ................................ –0.3 V to VCC + 0.3 V Range Ambient Temperature VCC Speed Industrial –40 C to +85 C 3.3 V 0.3 V 10 ns Electrical Characteristics Over the Operating Range Parameter Description -10 (Industrial) Test Conditions VOH Output HIGH voltage Min VCC, IOH = –4.0 mA Min VCC, IOL = 8.0 mA Min Max 2.4 – Unit V VOL Output LOW voltage – 0.4 V VIH Input HIGH voltage 2.0 VCC + 0.3 V VIL Input LOW voltage [2] –0.3 0.8 V IIX Input leakage current GND < VIN < VCC –1 +1 A IOZ Output leakage current GND < VIN < VCC, output disabled –1 +1 A ICC VCC operating supply current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC 100 MHz – 60 mA 83 MHz – 55 mA 66 MHz – 45 mA 40 MHz – 30 mA ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – 10 mA ISB2 Automatic CE power-down current – CMOS inputs Max VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 – 3 mA Note 2. VIL(min) = –2.0 V and VIH(max) = VCC + 1 V for pulse durations of less than 5 ns. Document Number: 38-05481 Rev. *F Page 4 of 16 [+] Feedback CY7C1019DV33 Capacitance Parameter [3] Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V Max Unit 8 pF 8 pF Thermal Resistance Parameter [3] Description JA Thermal Resistance (Junction to Ambient) JC Thermal Resistance (Junction to Case) Test Conditions 32-pin SOJ 32-pin TSOP II 48-ball VFBGA Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 56.29 62.22 36 C/W 38.14 21.43 9 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [4] ALL INPUT PULSES 3.0 V Z = 50 90% OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT GND 30 pF* 1.5V 90% 10% 10% Rise Time: 1 V/ns (a) (b) Fall Time: 1 V/ns High-Z characteristics: R1 317 3.3 V OUTPUT R2 351 5 pF (c) Notes 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 3 (a). High Z characteristics are tested for all speeds using the test load shown in Figure 3 (c). Document Number: 38-05481 Rev. *F Page 5 of 16 [+] Feedback CY7C1019DV33 Switching Characteristics Over the Operating Range Parameter [5] Description -10 (Industrial) Min Max Unit Read Cycle tpower[6] VCC(typical) to the first access 100 – s tRC Read cycle time 10 – ns tAA Address to data valid – 10 ns tOHA Data hold from address change 3 – ns tACE CE LOW to data valid – 10 ns tDOE OE LOW to data valid – 5 ns 0 – ns – 5 ns 3 – ns – 5 ns tLZOE tHZOE tLZCE OE LOW to low Z [7] OE HIGH to high Z CE LOW to low Z [7, 8] [7] [7, 8] tHZCE CE HIGH to high Z tPU[9] tPD[9] CE LOW to power-up 0 – ns CE HIGH to power-down – 10 ns Write Cycle [10, 11] tWC Write cycle time 10 – ns tSCE CE LOW to write end 8 – ns tAW Address set-up to write end 8 – ns tHA Address hold from write end 0 – ns tSA Address set-up to write start 0 – ns tPWE WE pulse width 7 – ns tSD Data set-up to write end 5 – ns tHD Data hold from write end tLZWE tHZWE 0 – ns WE HIGH to low Z [7] 3 – ns WE LOW to high Z [7, 8] – 5 ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in Figure 3 on page 5 (c). Transition is measured when the outputs enter a high impedance state. 9. This parameter is guaranteed by design and is not tested. 10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05481 Rev. *F Page 6 of 16 [+] Feedback CY7C1019DV33 Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for data retention ICCDR Data retention current tCDR [12] Chip deselect to data retention time tR[13] Operation recovery time VCC = VDR = 2.0 V, CE > VCC – 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V Min Max Unit 2.0 – V – 3 mA 0 – ns tRC – ns Data Retention Waveform Figure 4. Data Retention Waveform DATA RETENTION MODE 3.0 V VCC VDR > 2 V tCDR 3.0 V tR CE Switching Waveforms Figure 5. Read Cycle No. 1 (Address Transition Controlled) [14, 15] tRC RC ADDRESS tOHA DATA I/O tAA PREVIOUS DATA VALID DATA OUT VALID Notes 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 s or stable at VCC(min.) > 50 s. 14. Device is continuously selected. OE, CE = VIL. 15. WE is HIGH for Read cycle. Document Number: 38-05481 Rev. *F Page 7 of 16 [+] Feedback CY7C1019DV33 Switching Waveforms (continued) Figure 6. Read Cycle No. 2 (OE Controlled) [16, 17] ADDRESS tRC CE tACE OE tHZOE tDOE tHZCE tLZOE HIGH IMPEDANCE DATA I/O DATA OUT VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU ICC 50% 50% ISB Figure 7. Write Cycle No. 1 (CE Controlled) [18, 19] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA IN VALID Notes 16. WE is HIGH for Read cycle. 17. Address valid prior to or coincident with CE transition LOW. 18. Data I/O is high impedance if OE = VIH. 19. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 38-05481 Rev. *F Page 8 of 16 [+] Feedback CY7C1019DV33 Switching Waveforms (continued) Figure 8. Write Cycle No. 2 (WE Controlled, OE HIGH During Write) [20, 21] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATA IN VALID NOTE 22 tHZOE Figure 9. Write Cycle No. 3 (WE Controlled, OE LOW) [21, 23] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 22 tHD DATA IN VALID tHZWE tLZWE Notes 20. Data I/O is high impedance if OE = VIH. 21. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 22. During this period the I/Os are in the output state and input signals should not be applied. 23. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05481 Rev. *F Page 9 of 16 [+] Feedback CY7C1019DV33 Truth Table CE OE WE I/O0–I/O7 H X X High Z Power-Down Standby (ISB) L L H Data Out Read Active (ICC) L X L Data In Write Active (ICC) L H H High Z Selected, Outputs Disabled Active (ICC) Document Number: 38-05481 Rev. *F Mode Power Page 10 of 16 [+] Feedback CY7C1019DV33 Ordering Information Speed (ns) 10 Ordering Code Package Diagram Package Type CY7C1019DV33-10VXI 51-85033 32-pin (400-Mil) Molded SOJ (Pb-free) CY7C1019DV33-10ZSXI 51-85095 32-pin TSOP Type II (Pb-free) CY7C1019DV33-10BVXI 51-85150 48-ball VFBGA (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 01 9 D V33 - 10 XX X I Temperature Range: I = Industrial Pb-free Package Type: XX = V or ZS or BV V = 32-pin Molded SOJ ZS = 32-pin TSOP Type II BV = 48-ball VFBGA Speed: 10 ns Voltage range: V33 = 3 V to 3.6 V Process Technology: D = C9, 90 nm Data width: 9 = × 8-bits 01 = 1-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Please contact your local Cypress sales representative for availability of these parts. Document Number: 38-05481 Rev. *F Page 11 of 16 [+] Feedback CY7C1019DV33 Package Diagrams Figure 10. 32-pin SOJ (400 Mils) V32.4 (Molded SOJ V33) Package Outline, 51-85033 51-85033 *D Figure 11. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095 51-85095 *B Document Number: 38-05481 Rev. *F Page 12 of 16 [+] Feedback CY7C1019DV33 Package Diagrams (continued) Figure 12. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *G Document Number: 38-05481 Rev. *F Page 13 of 16 [+] Feedback CY7C1019DV33 Acronyms Acronym Document Conventions Description Units of Measure CE chip enable CMOS complementary metal oxide semiconductor °C degree Celsius I/O input/output MHz megahertz OE output enable A microampere SOJ small outline J-lead s microsecond SRAM static random access memory mA milliampere TSOP thin small outline package mm millimeter TTL transistor-transistor logic ns nanosecond VFBGA very fine-pitch ball gird array ohm WE write enable % percent pF picofarad V volt W watt Document Number: 38-05481 Rev. *F Symbol Unit of Measure Page 14 of 16 [+] Feedback CY7C1019DV33 Document History Page Document Title: CY7C1019DV33, 1-Mbit (128 K × 8) Static RAM Document Number: 38-05481 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Information data sheet for C9 IPP *A 233750 See ECN RKF DC parameters modified as per EROS (Spec # 01-02165 Rev *A) Pb-free Offering in Ordering Information *B 262950 See ECN RKF Added Data Retention Characteristics table Added Tpower Spec in Switching Characteristics table Shaded Ordering Information *C 307598 See ECN RKF Reduced Speed bins to -8 and -10 ns *D 520652 See ECN VKN Converted from Preliminary to Final Removed Commercial Operating range Removed 8 ns speed bin Added ICC values for the frequencies 83 MHz, 66 MHz and 40 MHz Added 48-ball VFBGA package Updated Thermal Resistance table Updated Ordering Information table Changed Overshoot spec from VCC + 2 V to VCC + 1 V in footnote #3 *E 3110052 12/14/2010 AJU Added Ordering Code Definitions. Updated Package Diagrams. *F 3416342 10/20/2011 TAVA Updated Functional Description (Removed the Note “For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.” and its reference in Functional Description). Updated Electrical Characteristics. Updated Switching Waveforms. Updated Package Diagrams. Added Acronyms and Units of Measure. Updated in new template. Document Number: 38-05481 Rev. *F Page 15 of 16 [+] Feedback CY7C1019DV33 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-05481 Rev. *F Revised October 20, 2011 Page 16 of 16 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback