W181 Peak-Reducing EMI Solution Features • Integrated loop filter components • Operates with a 3.3V or 5V supply • Cypress PREMIS™ family offering • Generates an EMI optimized clocking signal at the output • Selectable input to output frequency • Single 1.25% or 3.75% down or center spread output Simplified Block Diagram • Low-power CMOS design • Available in 8-pin small outline integrated circuit (SOIC) or 14-pin thin shrink small outline package (TSSOP select options only) Pin Configurations 3.3 or 5.0V SOIC XTAL Input 40 MHz Max. X2 W181 Spread Spectrum Output (EMI suppressed) 1 2 3 4 CLKIN or X1 1 NC or X2 2 GND 3 SS% 4 3.3 or 5.0V W181-02/03 W181-52/53 CLKIN or X1 NC or X2 GND SS% W181-01/51 X1 8 7 6 5 FS2 FS1 VDD CLKOUT 8 SSON# 7 FS1 6 VDD 5 CLKOUT TSSOP Oscillator or Reference Input W181 Cypress Semiconductor Corporation Document #: 38-07152 Rev. *D NC or X2 GND NC SS% NC Spread Spectrum Output (EMI suppressed) • 3901 North First Street • 1 2 3 4 5 6 7 W181-01 FS2 CLKIN or X1 14 13 12 11 10 9 8 NC NC FS1 NC VDD NC CLKOUT San Jose, CA 95134 • 408-943-2600 Revised July 06, 2004 W181 Pin Definitions Pin No. (SOIC) Pin No. (TSSOP)(-01) Pin Type CLKOUT 5 8 O Output Modulated Frequency: Frequency modulated copy of the unmodulated input clock (SSON# asserted). CLKIN or X1 1 2 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It may either be connected to an external crystal, or to an external reference clock. NC or X2 2 3 I Crystal Connection: If using an external reference, this pin must be left unconnected. 8(02/03/52/53) -- I Spread Spectrum Control (Active LOW): Asserting this signal (active LOW) turns the internal modulation waveform on. This pin has an internal pull-down resistor. FS1:2 7, 8 (01/51) 12, 1 I Frequency Selection Bit(s) 1 and 2: These pins select the frequency range of operation. Refer to Table 2. These pins have internal pull-up resistors. SS% 4 6 I Modulation Width Selection: When Spread Spectrum feature is turned on, this pin is used to select the amount of variation and peak EMI reduction that is desired on the output signal. This pin has an internal pull-up resistor. VDD 6 10 P Power Connection: Connected to 3.3V or 5V power supply. GND 3 4 G Ground Connection: Connect all ground pins to the common system ground plane. 5, 7, 9, 11, 13, 14 NC Pin Name SSON# NC Pin Description No Connection Key Specifications Overview Supply Voltages: .........................................VDD = 3.3V ± 5% .................................................................or VDD = 5V ± 10% The W181 products are one series of devices in the Cypress PREMIS family. The PREMIS family incorporates the latest advances in PLL spread spectrum frequency synthesizer techniques. By frequency modulating the output with a low-frequency carrier, peak EMI is greatly reduced. Use of this technology allows systems to pass increasingly difficult EMI testing without resorting to costly shielding or redesign. Frequency Range: ............................ 28 MHz ≤ Fin ≤ 75 MHz Crystal Reference Range.................. 28 MHz ≤ Fin ≤ 40 MHz Cycle to Cycle Jitter: ....................................... 300 ps (max.) Selectable Spread Percentage: ................... 1.25% or 3.75% Output Duty Cycle: ............................... 40/60% (worst case) Output Rise and Fall Time: .................................. 5 ns (max.) Table 1. Modulation Width Selection SS% W181-01, 02, 03 Output W181-51, 52, 53 Output 0 –1.25% (Down Spread) ±0.625 (Center Spread) 1 –3.75% (Down Spread) ±1.875% (Center Spread) Table 2. Frequency Range Selection W181 Option# FS2 FS1 -01, 51 (MHz) 0 0 28 ≤ FIN ≤ 38 28 ≤ FIN ≤ 38 0 1 38 ≤ FIN ≤ 48 38 ≤ FIN ≤ 48 N/A 1 0 46 ≤ FIN ≤ 60 N/A 46 ≤ FIN ≤ 60 1 1 58 ≤ FIN ≤ 75 N/A 58 ≤ FIN ≤ 75 Document #: 38-07152 Rev. *D -02, 52 (MHz) -03, 53 (MHz) N/A In a system, not only is EMI reduced in the various clock lines, but also in all signals which are synchronized to the clock. Therefore, the benefits of using this technology increase with the number of address and data lines in the system. The Simplified Block Diagram on page 1 shows a simple implementation. Functional Description The W181 uses a phase-locked loop (PLL) to frequency modulate an input clock. The result is an output clock whose frequency is slowly swept over a narrow band near the input signal. The basic circuit topology is shown in Figure 1. The input reference signal is divided by Q and fed to the phase detector. A signal from the VCO is divided by P and fed back to the phase detector also. The PLL will force the frequency of the VCO output signal to change until the divided output signal and the divided reference signal match at the phase detector input. The output frequency is then equal to the ratio of P/Q times the reference frequency. (Note: For the W181 the output frequency is equal to the input frequency.) The unique feature of the Spread Spectrum Frequency Timing Generator is that a modulating waveform is superimposed at the input to the VCO. This causes the VCO output to be slowly swept across a predetermined frequency band. Page 2 of 9 W181 Because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. Using frequency select bits (FS1:2 pins), the frequency range can be set. Spreading percentage is set to be 1.25% or 3.75% (see Table 1). Frequency Selection With SSFTG A larger spreading percentage improves EMI reduction. However, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. For these reasons, spreading percentages between 0.5% and 2.5% are most common. In Spread Spectrum Frequency Timing Generation, EMI reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. While the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. VDD Clock Input Reference Input Freq. Divider Q Phase Detector Charge Pump Σ VCO Post Dividers CLKOUT (EMI suppressed) Modulating Waveform Feedback Divider P PLL GND Figure 1. Functional Block Diagram Spread Spectrum Frequency Timing Generation The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 2. As shown in Figure 2, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: dB = 6.5 + 9*log10(P) + 9*log10(F) where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. Document #: 38-07152 Rev. *D The output clock is modulated with a waveform depicted in Figure 3. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. Figure 3 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. Page 3 of 9 W181 EMI Reduction Typical Clock Amplitude (dB) Amplitude (dB) SSFTG Spread Spectrum Enabled NonSpread Spectrum Frequency Span (MHz) Frequency Span (MHz) Center spread Down Spread Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX. MIN. Figure 3. Typical Modulation Profile Document #: 38-07152 Rev. *D Page 4 of 9 W181 . Absolute Maximum Conditions[2] Rating Unit VDD, VIN Parameter Voltage on any pin with respect to GND Description –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TA Operating Temperature 0 to +70 °C TB Ambient Temperature under Bias –55 to +125 °C PD Power Dissipation 0.5 W DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 3.3V ±5% Parameter Description Test Condition Min. Typ. Max. Unit – 18 32 mA – – 5 ms – – 0.8 V 2.4 – – V – – 0.4 V 2.4 – – V – – –100 µA – – 10 µA @ 0.4V, VDD = 3.3V – 15 – mA @ 2.4V, VDD = 3.3V – 15 – mA IDD Supply Current tON Power-Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current Note 3 IIH Input High Current Note 3 IOL Output Low Current IOH Output High Current First locked clock cycle after Power Good CI Input Capacitance All pins except CLKIN – v 7 pF CI Input Capacitance CLKIN pin only – 6 10 pF RP Input Pull-Up Resistor[3] – 500 – kΩ ZOUT Clock Output Impedance – 25 – Ω Min. Typ. Max. Unit 30 50 mA 5 ms 0.15VDD V 0.4 V –100 µA DC Electrical Characteristics: 0°C < TA < 70°C, VDD = 5V ±10% Parameter Description Test Condition IDD Supply Current tON Power-Up Time VIL Input Low Voltage VIH Input High Voltage VOL Output Low Voltage VOH Output High Voltage IIL Input Low Current IIH Input High Current Note 3 IOL Output Low Current @ 0.4V, VDD = 5V 24 IOH Output High Current @ 2.4V, VDD = 5V 24 CI Input Capacitance All pins except CLKIN CI Input Capacitance CLKIN pin only RP Input Pull-Up Resistor First locked clock cycle after Power Good 0.7VDD V 2.4 V Note 3 10 mA 7 6 500 µA mA 10 pF pF kΩ Notes: 1. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability 2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. 3. Inputs FS1:2 have a pull-up resistor; Input SSON# has a pull-down resistor. Document #: 38-07152 Rev. *D Page 5 of 9 W181 AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10% Parameter Description Test Condition Min. Typ. Max. Unit fIN Input Frequency Input Clock 28 75 MHz fOUT Output Frequency Spread Off 28 75 MHz tR Output Rise Time VDD, 15-pF load 0.8V–2.4V 2 5 ns tF Output Fall Time VDD, 15-pF load 2.4V–0.8V 2 5 ns tOD Output Duty Cycle 15-pF load tID Input Duty Cycle tJCYC Jitter, Cycle-to-Cycle 40 60 % 40 60 % 250 Harmonic Reduction fout = 40 MHz, third harmonic measured, reference board, 15-pF load 300 ps 8 dB CLKOUT Frequency Offset (Shift)[4,5]: TA = 0°C to +70°C, VDD = 3.3V ±5% or 5V±10% (For only W181-02, -02 and -03 products) Parameter Description Frequency Range (MHz) Min. Typ. Max. Unit FOFFSET-1 Frequency Offset (Shift) FS2=0, FS1=0, 28≤FIN≤38 –0.8 –1.0 –1.2 % FOFFSET-2 Frequency Offset (Shift) FS2=0, FS1=1, 38≤FIN≤48 –1.1 –1.4 –1.7 % FOFFSET-3 Frequency Offset (Shift) FS2=1, FS1=0, 46≤FIN≤60 –0.2 –0.5 –0.8 % FOFFSET-4 Frequency Offset (Shift) FS2=1, FS1=1, 58≤FIN≤75 –0.8 –1.0 –1.2 % Application Information increased trace inductance will negate its decoupling capability. The 10-µF decoupling capacitor shown should be a tantalum type. For further EMI protection, the VDD connection can be made via a ferrite bead, as shown. Recommended Circuit Configuration For optimum performance in system applications the power supply decoupling scheme shown in Figure 4 should be used. Recommended Board Layout VDD decoupling is important to both reduce phase jitter and EMI radiation. The 0.1-µF decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the 1 NC 2 GND 3 4 8 W181 Reference Input Figure 5 shows a recommended 2-layer board layout. 7 6 5 Clock Output R1 C1 0.1 µF 3.3 or 5V System Supply FB C2 10-µF Tantalum Figure 4. Recommended Circuit Configuration Notes: 4. The frequency offset (shift) is given with respect to ideal peak value which is the same as input reference frequency in the case of down spread only for W180-01,-02 and -03 products. 5. There is no offset (shift) for center spread for W180-51,-52 and -53 products. Document #: 38-07152 Rev. *D Page 6 of 9 W181 C1 = High frequency supply decoupling capacitor (0.1-µF recommended). C2 = Common supply low frequency decoupling capacitor (10-µF tantalum recommended). R1 = Match value to line impedance FB Reference Input G NC = Ferrite Bead Via To GND Plane = C1 G G Clock Output R1 G Power Supply Input (3.3 or 5V) C2 FB Figure 5. Recommended Board Layout (2-Layer Board) Ordering Information Ordering Code Package Type Product Flow W181-01G 8-pin Plastic SOIC (150-mil) Commercial, 0° to 70°C W181-01GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-02G 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C W181-02GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-03G 8 pin Plastic SOIC (150-mil Commercial, 0° to 70°C W181-03GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-51G 8-pin Plastic SOIC (150-mil) Commercial, 0° to 70°C W181-51GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-52G 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C W181-52GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-53G 8 pin Plastic SOIC (150-mil Commercial, 0° to 70°C W181-53GT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C W181-01X 14-pin Plastic TSSOP Commercial, 0° to 70°C W181-01XT 14-pin Plastic TSSOP – Tape and Reel Commercial, 0° to 70°C CYW181-01SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-01SXT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-02SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-02SXT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-03SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-03SXT 8 pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-51SX 8 pin Plastic SOIC (150-mil)) Commercial, 0° to 70°C CYW181-51SXT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-52SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-52SXT 8-pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C CYW181-53SX 8 pin Plastic SOIC (150-mil) Commercial, 0° to 70°C CYW181-53SXT 8 pin Plastic SOIC (150-mil) – Tape and Reel Commercial, 0° to 70°C Lead-free Devices Document #: 38-07152 Rev. *D Page 7 of 9 W181 Package Drawing and Dimension 14-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z14 PIN 1 ID 1 DIMENSIONS IN MM(INCHES) 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 14 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 0.25[0.010] BSC 1.10[0.043] MAX. GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] 0.50[0.020] 0.70[0.027] SEATING PLANE 0.09[[0.003] 0.20[0.008] 51-85117-*A 8 Lead (150 Mil) SOIC -8-lead S08 (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85066-*C PREMIS is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07152 Rev. *D Page 8 of 9 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. W181 Document History Page Document Title: W181 Peak Reducing EMI Solution Document Number: 38-07152 REV. Orig. of ECN No. Issue Date Change Description of Change ** 110262 12/15/01 SZV Change from Spec number: 38-00790 to 38-07152 *A 122687 12/27/02 RBI Added power up requirements to maximum ratings information. *B 127906 07/07/03 IJA Changed Modulation Width Selection values in Table 1 Added CLKOUT Frequency Offset Table Created Cypress approved drawings to replace old ones Updated Ordering Information to clarify and match ordering codes to Dev Master *C 131492 01/22/04 RGL Added Lead-free for all the SOIC packages in the ordering information *D 241879 See ECN RGL Corrected the Lead Free Coding in the Ordering Information table Document #: 38-07152 Rev. *D Page 9 of 9