EDI8F8512C 512Kx8 STATIC RAM CMOS, MODULE FEATURES DESCRIPTION n 512Kx8 bit CMOS Static The EDI8F8512C is a 4096K bit CMOS Static RAM based on four 128Kx8 or 256Kx4 (high speed) Static RAMs mounted on a multilayered epoxy laminate (FR4) substrate. n Random Access Memory Access Times 20 through 100ns Functional equivalence to the monolithic four megabit Static RAM is achieved by utilization of an on-board decoder that interprets the higher order address(es) to select one of the128Kx8 or 256Kx4 Static RAMs. Data Retention Function (EDI8F8512LP) TTL Compatible Inputs and Outputs Fully Static, No Clocks The 32 pin DIP pinout adheres to the JEDEC standard for the four megabit device, to ensure compatibility with future monolithics. n High Density Packaging 36 Pin SIP, No. 63 A low power version with data retention (EDI8F8512LP) is also available. 32 Pin DIP, JEDEC Pinout, No. 91 (55-100ns) 32 Pin DIP, JEDEC Pinout, No. 183 (20-35ns) All inputs and outputs are TTL compatible and operate from a single 5V supply. Fully asynchronous, the EDI8F8512C requires no clocks or refreshing for operation. n Single +5V (±10%) Supply Operation FIG. 1 PIN NAMES PIN CONFIGURATIONS AND BLOCK DIAGRAM NC VCC W DQ2 DQ3 DQ0 A1 A2 A3 A4 VSS DQ5 A10 A11 A5 A13 A14 NC E A15 A16 A12 A18 A6 DQ1 VSS A0 A7 A8 A9 DQ7 DQ4 DQ6 A17 VCC G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 8F8512C Pin Config. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 AØ-A18 VCC A15 A17 W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 E Chip Enable W Write Enable G Output Enable DQØ-DQ7 Common Data Input/Output VCC Power (+5V±10%) VSS Ground NC No Connection A0-17 W 256K x 4 DQ0-3 256K x 4 DQ4-7 G 8F8512C Pin Config A0-16 128K x 8 W G 128K x 8 256K x 4 20-35ns DQ0-7 55-100ns 128K x 8 256K x 4 20-55ns 128K x 8 A18 A17-A18 E E DECODER DECODER 8F8512C Blk Dia2 8F8512C Blk Dia July 2002 Rev. 13A ECO #15405 Address Inputs 1 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F8512C RECOMMENDED DC OPERATING CONDITIONS A BSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to VSS Operating Temperature TA (Ambient) Commercial Industrial Storage Temperature Power Dissipation Output Current -0.5V to 7.0V Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage 0°C to +70°C -40°C to +85°C -55°C to +125°C 4 Watts 20 mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Sym VCC VSS VIH VIL Min 4.5 0 2.2 -0.3 Typ 5.0 0 --- Max 5.5 0 6.0 0.8 Units V V V V AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load 20-35ns 70-100ns VSS to 3.0V 5ns 1.5V 1TTL = 30pF 1TTL, CL =100pF (note: For TEHQZ,TGHQZ and TWLQZ, CL = 5pF) DC ELECTRICAL CHARACTERISTICS Parameter Sym Operating Power Supply Current Standby (TTL) Power Supply Current Full Standby Power Supply Current (CMOS) ICC1 W, E = VIL, II/O = 0mA, -Min Cycle ICC2 E á VIH, VIN VIL DIP -VIN á VIH SIP -ICC3 E á VCC-0.2V C -VIN á VCC-0.2V or LP -VIN [ 0.2V ILI VIN = 0V to VCC -ILO V I/O = 0V to VCC -VOH IOH=-1.0mA (á70),or -4.0([35) 2.4 VOL IOL = 2.1mA (á70),or 8.0mA([35) -- Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Conditions Min [35 340 Typ* Max á55 20-25 35 55-100 70 570 390 130 Units ns mA 50 -5 -- 10 -2 40 85 -40 -- 85 -40 -- 55 65 5 400 mA mA mA µA ----- ----- ±10 ±10 -0.4 ±10 ±10 ±10 ±10 --0.4 0.4 µA µA V V *Typical: TA=25°C, VCC=5.0V CAPACITANCE TRUTH TABLE G X H L X E H L L L W X H H L Mode Standby Output Deselect Read Write Output High Z High Z DOUT DIN (f=1.0MHz, VIN=VCC or VSS) Power ICC2, ICC3 ICC1 ICC1 ICC1 Parameter Address Lines Data Lines Chip Enable Line Write and Output Enable Lines Sym CI CD/Q CC CW Max 30 43 10 32 Unit pF pF pF pF These parameters are sampled, not 100% tested. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 2 July 2002 Rev. 13A ECO #15405 EDI8F8512C AC CHARACTERISTICS READ CYCLE Symbol JEDEC Alt. TAVAV TRC TAVQV TAA TELQV TACS TELQX TCLZ TEHQZ TCHZ TAVQX TOH TGLQV TOE TGLQX TOLZ TGHQZ TOHZ Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) 20ns Min Max 20 20 20 3 10 3 13 0 8 Min 25 25ns Max 25 25 3 12 3 15 0 10 35ns Min Max 35 35 35 3 15 3 20 0 12 Units ns ns ns ns ns ns ns ns ns Note 1: Parameter guaranteed, but not tested. FIG. 2 READ CYCLE 1 - W HIGH, G, E LOW TAVAV A ADDRESS 1 ADDRESS 2 TAVQV TAVQX Q DATA 2 DATA 1 8F8512C Rd Cyc1 FIG. 3 READ CYCLE 2 - W HIGH TAVAV A TAVQV E TELQV TEHQZ TELQX G TGLQV TGHQZ TGLQX Q 8F8512C Rd Cyc2 July 2002 Rev. 13A ECO #15405 3 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F8512C AC CHARACTERISTICS READ CYCLE Parameter Read Cycle Time Address Access Time Chip Enable Access Time Chip Enable to Output in Low Z (1) Chip Disable to Output in High Z (1) Output Hold from Address Change Output Enable to Output Valid Output Enable to Output in Low Z (1) Output Disable to Output in High Z(1) Symbol JEDEC Alt. TAVAV TRC TAVQV TAA TELQV TACS TELQX TCLZ TEHQZ TCHZ TAVQX TOH TGLQV TOE TGLQX TOLZ TGHQZ TOHZ 55ns Min Max 55 55 55 5 30 3 40 0 30 70ns Min Max 70 70 70 5 30 3 40 0 30 85ns Min Max 85 85 85 5 35 3 45 0 35 100ns Min Max 100 100 100 5 40 3 50 0 40 Units ns ns ns ns ns ns ns ns ns Note 1: Parameter guaranteed, but not tested. AC CHARACTERISTICS WRITE CYCLE Write Cycle Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt TAVAV TWC TELWH TCW TELEH TCW TAVWL TAS TAVEL TAS TAVWH TAW TAVEH TAW TWLWH TWP TWLEH TWP TWHAX TWR TEHAX TWR TWHDX TDH TEHDX TDH TWLQZ TWHZ TDVWH TDW TDVEH TDW TWHQX TWLZ Min 20 15 15 0 0 15 15 15 15 0 0 3 3 0 12 12 3 20ns Max 10 Min 25 20 20 0 0 20 20 20 20 0 0 3 3 0 15 15 3 25ns Max 12 35ns Min Max 35 30 30 0 0 30 30 25 25 0 0 3 3 0 15 20 20 3 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Parameter guaranteed, but not tested. White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 4 July 2002 Rev. 13A ECO #15405 EDI8F8512C AC CHARACTERISTICS WRITE CYCLE Parameter Write Cycle Time Chip Enable to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Data Hold Time Write to Output in High Z (1) Data to Write Time Output Active from End of Write (1) Symbol JEDEC Alt. TAVAV TWC TELWH TCW TELEH TCW TAVWL TAS TAVEL TAS TAVWH TAW TAVEH TAW TWLWH TWP TWLEH TWP TWHAX TWR TEHAX TWR TWHDX TDH TEHDX TDH TWLQZ TWHZ TDVWH TDW TDVEH TDW TWHQX TWLZ 55NS Min Max 55 50 50 0 0 50 50 50 50 0 0 0 0 0 30 30 30 5 70ns Min Max 70 65 65 0 0 65 65 65 65 0 0 0 0 0 30 30 30 5 85n Min Max 85 70 70 0 0 70 70 70 70 0 0 0 0 0 35 35 35 5 100ns Min Max 100 80 80 0 0 80 80 80 80 0 0 0 0 0 40 40 40 5 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note 1: Parameter guaranteed, but not tested. FIG. 6 WRITE CYCLE 1 - W CONTROLLED TAVAV A E TELWH TWHAX TAVWH TWLWH W TAVWL TDVWH D TWHDX DATA VALID TWHQX TWLQZ HIGH Z Q 8F8512C Write Cyc1 July 2002 Rev. 13A ECO #15405 5 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F8512C FIG. 7 WRITE CYCLE 2 - E CONTROLLED TAVAV A TAVEL TELEH E TAVEH TEHAX TWLEH W TDVEH D TEHDX DATA VALID HIGH Z Q 8F8512C Write Cyc2 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 6 July 2002 Rev. 13A ECO #15405 EDI8F8512C DATA RETENTION CHARACTERISTICS Characteristic Sym Data Retention Voltage Test Conditions VDD VDD = 0.2V Data Retention Quiescent Current ICCDR E > VDD -0.2V VIN > VDD -0.2V Chip Disable to Data Retention Time (1) TCDR or VIN < 0.2V Operation Recovery Time (1) VDD LP 70-100ns Only Min Max Unit 2 -- 70°C -- --- 10 20 125 200 185 250 µA µA 0 -- -- -- ns TAVAV* -- -- -- ns 2V 3V TR Typ 85°C -- V *Read Cycle Time Note 1: Parameter guaranteed, but not tested. FIG. 8 DATA RETENTION E CONTROLLED DATA RETENTION MODE 4.5V VCC 4.5V VDD TCDR TR E VDD-0.2V E 8F8512C Data Retent. ORDERING INFORMATION Standard Power EDI8F8512C20M6C EDI8F8512C25M6C EDI8F8512C35M6C EDI8F8512C70BSC EDI8F8512C85BSC EDI8F8512C100BSC EDI8F8512C55B6C EDI8F8512C70B6C EDI8F8512C85B6C EDI8F8512C100B6C July 2002 Rev. 13A ECO #15405 Speed (ns) 20 25 35 70 85 100 55 70 85 100 Low Power with Data Retention EDI8F8512LP70BSC EDI8F8512LP85BSC EDI8F8512LP100BSC EDI8F8512LP70B6C EDI8F8512LP85B6C EDI8F8512LP100B6C Package No. 183 183 183 63 63 63 91 91 91 91 Speed (ns) 70 85 100 70 85 100 Package Leads 63 63 63 91 91 91 Note: To order an Industrial grade product substitute the letter C in the Suffix with the letter I, eg. EDI8F8512C70B6C becomes EDI8F8512C70B6I. 7 White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com EDI8F8512C PACKAGE DESCRIPTION PACKAGE NO. 63: 36 PIN SINGLE-IN-LINE PACKAGE 4.040 Max. 0.150 Max 0.575 0.565 0.125 Min 0.020 0.016 0.100 35 x 0.100 =3.500 8F8512C Pkg1 PACKAGE NO. 91: 32 PIN DUAL-IN-LINE PACKAGE 8F8512C Pkg 2 PACKAGE NO. 183: 32 PIN DUAL-IN-LINE PACKAGE EW N OR F ED D EN M OM C E R T NO S N G SI E D 8F8512C Pkg3 ALL DIMENSIONS ARE IN INCHES White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com 8 July 2002 Rev. 13A ECO #15405