EL5325A ® Data Sheet May 8, 2006 12-Channel TFT-LCD Reference Voltage Generator with External Shutdown The EL5325A with external shutdown is designed to produce the reference voltages required in TFT-LCD applications. Each output is programmed to the required voltage with 10 bits of resolution. Reference pins determine the high and low voltages of the output range, which are capable of swinging to either supply rail. Programming of each output is performed using the 3-wire, SPI compatible interface. Features • 12-channel reference outputs • Accuracy of ±1% • Supply voltage of 5V to 16.5V • Digital supply 3.3V to 5V • Low supply current of 10mA • Rail-to-rail capability A number of EL5325A can be stacked for applications requiring more than 12 outputs. The reference inputs can be tied to the rails, enabling each part to output the full voltage range, or alternatively, they can be connected to external resistors to split the output range and enable finer resolutions of the outputs. • Internal thermal protection The EL5325A has 12 outputs and is available in a 28 Ld TSSOP package. They are specified for operation over the full -40°C to +85°C temperature range. • TFT-LCD drive circuits PART TAPE & MARKING REEL PACKAGE PKG. DWG. # EL5325AIREZ (Note) 5325AIREZ - 28 Ld HTSSOP MDP0048 (Pb-Free) EL5325AIREZ-T7 (Note) 5325AIREZ 7” 28 Ld HTSSOP MDP0048 (Pb-Free) EL5325AIREZ-T13 5325AIREZ (Note) 13” 28 Ld HTSSOP MDP0048 (Pb-Free) EL5325AIRZ (Note) 5325AIRZ EL5325AIRZ-T7 (Note) 5325AIRZ EL5325AIRZ-T13 (Note) 5325AIRZ - 28 Ld TSSOP (Pb-Free) MDP0044 7” 28 Ld TSSOP (Pb-Free) MDP0044 13” 28 Ld TSSOP (Pb-Free) MDP0044 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 • External shutdown • Pb-free plus anneal available (RoHS compliant) Applications • Reference voltage generators Pinout Ordering Information PART NUMBER FN7447.1 EL5325A (28 LD TSSOP/HTSSOP) TOP VIEW ENA 1 28 OUTA SDI 2 27 OUTB SCLK 3 26 OUTC SDO 4 25 GND EXT_OSC 5 24 OUTD VS 6 23 OUTE SHDN 7 22 OUTF VSD 8 21 OUTG REFH 9 20 OUTH REFL 10 19 OUTI VS 11 18 GND GND 12 17 OUTJ CAP 13 16 OUTK NC 14 15 OUTL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL5325A Absolute Maximum Ratings (TA = 25°C) Supply Voltage between VS & GND . . . . . . 4.5V (min) to 18V (max) Supply Voltage between VSD & GND . 3V (min) to VS and 7V (max) Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 30mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA VS = 15V, VSD = 5V, VREFH = 13V, VREFL = 2V, RL = 1.5kΩ and CL = 200pF to 0V, TA = 25°C, unless Electrical Specifications otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT 10.2 12.5 mA 0.17 0.35 mA 50 150 mV SUPPLY IS Supply Current ISD Digital Supply Current No load ANALOG VOL Output Swing Low Sinking 5mA (VREFH = 15V, VREFL = 0) VOH Output Swing High Sourcing 5mA (VREFH = 15V, VREFL = 0) ISC Short Circuit Current PSRR Power Supply Rejection Ratio 14.85 14.95 V RL = 10Ω 100 140 mA VS+ is moved from 14V to 16V 45 65 dB tD Program to Out Delay 4 ms VAC Accuracy referred to the ideal value Code = 512 20 mV ΔVMIS Channel to Channel Mismatch Code = 512 2 mV VDROOP Droop Voltage 1 2 mV/ms 0.5 1.5 mV/mA 1.3 1.6 V RINH Input Resistance @ VREFH, VREFL REG Load Regulation IOUT = 5mA step 32 kΩ CAP Band Gap By pass with 0.1µF 1 Logic 1 Input Voltage VSD = 5V 4 V VSD = 3.3V 2 V DIGITAL VIH FCLK Clock Frequency VIL Logic 0 Input Voltage VSD = 3.3V/5V 5 MHz 1 V tS Setup Time 20 ns tH Hold Time 20 ns tLC Load to Clock Time 20 ns tCE Clock to Load Line 20 ns tDCO Clock to Out Delay Time 10 ns RSDIN SDIN Input Resistance 1 GΩ TPULSE Minimum Pulse Width for EXT_OSC Signal 5 µs Duty Cycle Duty Cycle for EXT_OSC Signal 50 % INL Integral Nonlinearity Error 1.3 LSB DNL Differential Nonlinearity Error 0.5 LSB F_OSC Internal Refresh Oscillator Frequency 21 kHz VIH_SHDN SHDN Voltage Input High IIH_SHDN SHDN Current Input High 2 Negative edge of SCLK OSC_Select = 0 2 SHDN = 2V V 100 µA EL5325A Pin Descriptions EL5325A PIN NAME PIN TYPE PIN FUNCTION 1 ENA Logic Input Chip select, low enables data input to logic 2 SDI Logic Input Serial data input 3 SCLK Logic Input Serial data clock 4 SDO Logic Output Serial data output 5 EXT_OSC Logic Input/Output 6, 11 VS+ Analog Power 7 SHDN Logic Input 8 VSD Digital Power 9 REFH Analog Reference Input High reference voltage 10 REFL Analog Reference Input Low reference voltage 12 GND Ground 13 CAP Analog Bypass Pin 14 NC 17 OUTJ Analog Output Channel J programmable output voltage 19 OUTI Analog Output Channel I programmable output voltage 20 OUTH Analog Output Channel H programmable output voltage 21 OUTG Analog Output Channel G programmable output voltage 22 OUTF Analog Output Channel F programmable output voltage 23 OUTE Analog Output Channel E programmable output voltage 24 OUTD Analog Output Channel D programmable output voltage 26 OUTC Analog Output Channel C programmable output voltage 27 OUTB Analog Output Channel B programmable output voltage 28 OUTA Analog Output Channel A programmable output voltage 15 OUTL Analog Output Channel L programmable output voltage 16 OUTK Analog Output Channel K programmable output voltage 18, 25 GND Power External oscillator input or internal oscillator output Positive supply voltage for analog circuits Chip shutdown: float enables chip, high > 2V disables chip Positive power supply for digital circuits (3.3V - 5V) Ground Decoupling capacitor for internal reference generator, 0.1µF Not connected 3 Ground EL5325A VS=15V, VSD=5V, VREFH=13V, VREFL=2V REFH=13V, REFL=2V 0.3 1.5 0.2 1 0.1 INL (LSB) DIFFERENTIAL NONLINEARITY (LSB) Typical Performance Curves 0 0.5 0 -0.1 -0.5 -0.2 -0.3 10 -1 210 410 610 810 0 1010 200 400 600 800 1000 1200 CODE INPUT CODE FIGURE 1. DIFFERENTIAL NONLINEARITY vs CODE FIGURE 2. INTEGRAL NONLINEARITY ERROR VS=VREFH=15V M=400ns/DIV VS=VREFH=15V M=400ns/DIV 0mA 5mA/DIV 5mA 0mA 5mA CL=1nF RS=20Ω CL=4.7nF RS=20Ω 5V 200mV/DIV CL=1nF RS=20Ω CL=4.7nF RS=20Ω CL=180pF CL=180pF FIGURE 3. TRANSIENT LOAD REGULATION (SOURCING) FIGURE 4. TRANSIENT LOAD REGULATION (SINKING) M=400µs/DIV M=400µs/DIV 5V SCLK SCLK SDA SDA 0V 5V 0V 10V 5V 0V OUTPUT OUTPUT FIGURE 5. LARGE SIGNAL RESPONSE (RISING FROM 0V TO 8V) 4 FIGURE 6. LARGE SIGNAL RESPONSE (FALLING FROM 8V TO 0V) EL5325A Typical Performance Curves (Continued) M=400µs/DIV M=400µs/DIV SCLK SCLK SDA SDA 5V 0V 5V 0V OUTPUT OUTPUT 200mV 0V FIGURE 7. SMALL SIGNAL RESPONSE (RISING FROM 0V TO 200mV) FIGURE 8. SMALL SIGNAL RESPONSE (FALLING FROM 200mV TO 0V) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 833mW 0.7 θ 0.6 JA = TS S 12 0.5 POWER DISSIPATION (W) POWER DISSIPATION (W) 0.8 O P2 0° 8 C/ W 0.4 0.3 0.2 0.1 1.333W 1.2 θ 0.8 SO P2 75 8 °C /W 0.6 0.4 0.2 0 0 0 25 75 85 50 100 125 0 25 AMBIENT TEMPERATURE (°C) JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 3.5 0.9 H 8 P2 /W SO °C TS 110 = A θJ 0.6 0.5 100 125 0.4 0.3 0.2 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3 3.333W 2.5 2 8 P2 W O / S S 0° C HT =3 A θJ 0.8 909mW 0.7 75 85 FIGURE 10. POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) 1 50 AMBIENT TEMPERATURE (°C) FIGURE 9. POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) TS JA = 1 1.5 1 0.5 0.1 0 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 11. POWER DISSIPATION vs AMBIENT TEMPERATURE 5 150 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (°C) FIGURE 12. POWER DISSIPATION vs AMBIENT TEMPERATURE 150 EL5325A General Description The EL5325A provides a versatile method of providing the reference voltages that are used in setting the transfer characteristics of LCD display panels. The V/T (Voltage/Transmission) curve of the LCD panel requires that a correction is applied to make it linear; however, if the panel is to be used in more than one application, the final curve may differ for different applications. By using the EL5325A, the V/T curve can be changed to optimize its characteristics according to the required application of the display product. Each of the eight reference voltage outputs can be set with a 10-bit resolution. These outputs can be driven to within 50mV of the power rails of the EL5325A. As all of the output buffers are identical, it is also possible to use the EL5325A for applications other than LCDs where multiple voltage references are required that can be set to 10 bit accuracy. allocated to the following functions (also refer to the Control Bits Logic Table) • Bit 15 is always set to a zero • Bit 14 controls the source of the clock, see the next section for details • Bits 13 through 10 select the channel to be written to, these are binary coded with channel A = 0, and channel H=7 • The 10-bit data is on bits 9 through 0. Some examples of data words are shown in the table of Serial Programming Examples TABLE 1. CONTROL BITS LOGIC TABLE BIT NAME B15 Test Digital Interface B14 Oscillator The EL5325A uses a simple 3-wire SPI compliant digital interface to program the outputs. The EL5325A can support the clock rate up to 5MHz. B13 A3 Channel Address B12 A2 Channel Address B11 A1 Channel Address The EL5325A is programmed through a three-wire serial interface. The start and stop conditions are defined by the ENA signal. While the ENA is low, the data on the SDI (serial data input) pin is shifted into the 16-bit shift register on the positive edge of the SCLK (serial clock) signal. The MSB (bit 15) is loaded first and the LSB (bit 0) is loaded last (see Table 1). After the full 16-bit data has been loaded, the ENA is pulled high and the addressed output channel is updated. The SCLK is disabled internally when the ENA is high. The SCLK must be low before the ENA is pulled low. B10 A0 Channel Address B9 D9 Data B8 D8 Data B7 D7 Data B6 D6 Data B5 D5 Data B4 D4 Data To facilitate the system designs that use multiple EL5325A chips, a buffered serial output of the shift register (SDO pin) is available. Data appears on the SDO pin at the 16th falling SCLK edge after being applied to the SDI pin. B3 D3 Data B2 D2 Data B1 D1 Data To control the multiple EL5325A chips from a single threewire serial port, just connect the ENA pins and the SCLK pins together, connect the SDO pin to the SDI pin on the next chip. While the ENA is held low, the 16m-bit data is loaded to the SDI input of the first chip. The first 16-bit data will go to the last chip and the last 16-bit data will go to the first chip. While the ENA is held high, all addressed outputs will be updated simultaneously. B0 D0 Data Serial Interface The Serial Timing Diagram and parameters table show the timing requirements for three-wire signals. The serial data has a minimum length of 16 bits, the MSB (most significant bit) is the first bit in the signal. The bits are 6 DESCRIPTION Always 0 0 = Internal, 1 = External EL5325A Serial Timing Diagram ENA tHE tSE T tr tf tHE tSE SCLK tSD tHD SDI B15 tw B14 MSB B13 B12-B2 B1 B0 t LSB Load MSB first, LSB last TABLE 2. SERIAL TIMING PARAMETERS PARAMETER RECOMMENDED OPERATING RANGE DESCRIPTION T ≥200ns Clock Period tr/tf 0.05 * T Clock Rise/Fall Time tHE ≥10ns ENA Hold Time tSE ≥10ns ENA Setup Time tHD ≥10ns Data Hold Time tSD ≥10ns Data Setup Time tW 0.50 * T Clock Pulse Width TABLE 3. SERIAL PROGRAMMING EXAMPLES CONTROL CHANNEL ADDRESS DATA C1 C0 A3 A2 A1 A0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Internal Oscillator, Channel A, Value = 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 Internal Oscillator, Channel A, Value = 1023 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Internal Oscillator, Channel A, Value = 512 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1‘t Internal Oscillator, Channel C, Value = 513 0 0 0 1 1 1 0 0 0 0 0 1 1 1 1 1 Internal Oscillator, Channel H, Value = 31 0 1 0 1 1 1 0 0 0 0 0 1 1 1 1 1 External Oscillator, Channel H, Value = 31 CONDITION 7 EL5325A Block Diagram REFERENCE HIGH OUTA OUTB OUTJ EIGHT CHANNEL MEMORY VOLTAGE SOURCES OUTK OUTL REFERENCE LOW REFERENCE DECOUPLE CLK SDI SDO CONTROL IF LOAD FILTER EXT_OSC Analog Section CLOCK OSCILLATOR TRANSFER FUNCTION The EL5325A requires an internal clock or external clock to refresh its outputs. The outputs are refreshed at the falling OSC clock edges. The output refreshed switches open at the rising edges of the OSC clock. The driving load shouldn’t be changed at the rising edges of the OSC clock. Otherwise, it will generate a voltage error at the outputs. This clock may be input or output via the clock pin labeled OSC. The internal clock is provided by an internal oscillator running at approximately 21kHz and can be output to the OSC pin. In a 2 chip system, if the driving loads are stable, one chip may be programmed to use the internal oscillator; then the OSC pin will output the clock from the internal oscillator. The second chip may have the OSC pin connected to this clock source. The transfer function is: data V OUT ( IDEAL ) = V REFL + ------------- × ( V REFH - V REFL ) 1024 where data is the decimal value of the 10-bit data binary input code. The output voltages from the EL5325A will be derived from the reference voltages present at the VREFL and VREFH pins. The impedance between those two pins is about 32kΩ. Care should be taken that the system design holds these two reference voltages within the limits of the power rails of the EL5325A. GND < VREFH ≤ VS and GND ≤ VREFL ≤ VREFH. In some LCD applications that require more than 12 channels, the system can be designed such that one EL5325A will provide the Gamma correction voltages that are more positive than the VCOM potential. The second EL5325A can provide the Gamma correction voltage more negative than the VCOM potential. The Application Drawing shows a system connected in this way. 8 For transient load application, the external clock Mode should be used to ensure all functions are synchronized together. The positive edge of the external clock to the OSC pin should be timed to avoid the transient load effect. The Application Drawing shows the LCD H rate signal used, here the positive clock edge is timed to avoid the transient load of the column driver circuits. After power on, the chip will start with the internal oscillator mode. At this time, the OSC pin will be in a high impedance condition to prevent contention. By setting B14 to high, the EL5325A chip is on external clock mode. Setting B14 to low, the chip is on internal clock mode. CHANNEL OUTPUTS when sinking. Where: • i = 1 to total 12 Each of the channel outputs has a rail-to-rail buffer. This enables all channels to have the capability to drive to within 50mV of the power rails, (see Electrical Characteristics for details). When driving large capacitive loads, a series resistor should be placed in series with the output. (Usually between 5Ω and 50Ω). Each of the channels is updated on a continuous cycle, the time for the new data to appear at a specific output will depend on the exact timing relationship of the incoming data to this cycle. The best-case scenario is when the data has just been captured and then passed on to the output stage immediately; this can be as short as 48µs. In the worst-case scenario this will be 576µs when the data has just missed the cycle. When a large change in output voltage is required, the change will occur in 2V steps, thus the requisite number of timing cycles will be added to the overall update time. This means that a large change of 16V can take between 4.6ms to 5.2ms depending on the absolute timing relative to the update cycle. POWER DISSIPATION AND THERMAL SHUTDOWN With the 30mA maximum continues output drive capability for each channel, it is possible to exceed the 125°C absolute maximum junction temperature. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the part to remain in the safe operation. The maximum power dissipation allowed in a package is determined according to: • VS = Supply voltage • IS = Quiescent current • VOUTi = Output voltage of the i channel • ILOADi = Load current of the i channel By setting the two PDMAX equations equal to each other, we can solve for the RLOADs to avoid the device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The EL5325A has an internal thermal shutdown circuitry that prevents overheating of the part. When the junction temperature goes up to about 150°C, the part will be disabled. When the junction temperature drops down to about 120°C, the part will be enabled. With this feature, any short circuit at the outputs will enable the thermal shutdown circuitry to disable the part. POWER SUPPLY BYPASSING AND PRINTED CIRCUIT BOARD LAYOUT Good printed circuit board layout is necessary for optimum performance. A low impedance and clean analog ground plane should be used for the EL5325A. The traces from the two ground pins to the ground plane must be very short. The thermal pad of the EL5325A should be connected to the analog ground plane. Lead length should be as short as possible and all power supply pins must be well bypassed. A 0.1µF ceramic capacitor must be place very close to the VS, VREFH, VREFL, and CAP pins. A 4.7µF local bypass tantalum capacitor should be placed to the VS, VREFH, and VREFL pins. APPLICATION USING THE EL5325A where: In the first application drawing, the schematic shows the interconnect of a pair of EL5325A chips connected to give 12 gamma corrected voltages above the VCOM voltage, and 12 gamma corrected voltages below the VCOM voltage. • TJMAX = Maximum junction temperature External Shutdown T JMAX - T AMAX P DMAX = -------------------------------------------Θ JA • TAMAX = Maximum ambient temperature • θJA = Thermal resistance of the package • PDMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by the IC is the total quiescent supply current times the total power supply voltage and plus the power in the IC due to the loads. P DMAX = V S × I S + Σ [ ( V S - V OUT i ) × I LOAD i ] The EL5325A also has an external shutdown to enable and disable the part. The SHDN pin should never be driven low. Rather, to enable the part, the SHDN pin must be left open (float). To disable, the SHDN pin must be driven HI (>2V). WIth this feature, the EL5325A can be forced to shut down, regardless of any other conditions. A simple open collector driver is adequate to control the enable and disable function: VSD R1 100K when sourcing, and: P DMAX = V S × I S + Σ ( V OUT i × I LOAD i ) 9 R2 100K SHDN Q1 PNP EL5325A SHDN EL5325A Application Drawing HIGH REFERENCE VOLTAGE +10V REFH OUTA VS OUTB 0.1µF +12V COLUMN (SOURCE) DRIVER 0.1µF +5V MICROCONTROLLER VSD OUTC 0.1µF OUTD LCD TIMING CONTROLLER SDI SCK ENA SDO HORIZONTAL RATE OUTE OSC OUTF CAP 0.1µF OUTK REFL GND OUTL EL5325A MIDDLE REFERENCE +5.5V +12V REFH OSC OUTA VS OUTB 0.1µF +5V VSD OUTC 0.1µF OUTD SDI SCK ENA CAP 0.1µF LOW REFERENCE VOLTAGE +1V OUTE OUTF REFL 0.1µF OUTK GND OUTL EL5325A 10 LCD PANEL EL5325A Package Outline Drawing (HTSSOP) 11 EL5325A TSSOP Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. 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