EL7585 ® Data Sheet March 9, 2006 FN7345.2 TFT-LCD Power Supply Features The EL7585 represents a multiple output regulators for use in all large panel, TFT-LCD applications. It features a single boost converter with integrated 3.5A FET, two positive LDOs for VON and VLOGIC generation, and a single negative LDO for VOFF generation. The boost converter can be programmed to operate in either P-mode or PI-mode for improved load regulation. • 3.5A current limit FET options The EL7585 also integrates fault protection for all four channels. Once a fault is detected, the device is latched off until the input supply or EN is cycled. This device also features an integrated start-up sequence for VBOOST, VOFF, then VON or for VOFF, VBOOST, and VON sequencing. The latter requires a single external transistor. The timing of the start-up sequence is set using an external capacitor. The EL7585 is specified for operation over the -40°C to +85°C temperature range. Ordering Information TAPE & REEL PKG. DWG. # EL7585ILZ (Note) 7585ILZ 20 Ld 4x4 QFN (Pb-free) - MDP0046 EL7585ILZ-T7 (Note) 7585ILZ 20 Ld 4x4 QFN (Pb-free) 7” MDP0046 EL7585ILZ-T13 7585ILZ (Note) 20 Ld 4x4 QFN (Pb-free) 13” MDP0046 • VBOOST/VLOGIC-VOFF-VON or VLOGIC-VOFF-VBOOSTVON sequence control • Programmable sequence delay • Fully fault protected • Thermal shutdown • Internal soft-start • 20 Ld QFN packages • Pb-Free plus anneal available (RoHS Compliant) Applications • LCD monitors (15”+) • LCD-TV (up to 40”+) • Notebook displays (up to 16”) • Industrial/medical LCD displays Pinout 16 FBB 17 SGND 18 EN NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. EL7585 (20 LD QFN) TOP VIEW 19 VDD PACKAGE • 1% regulation on all outputs CDLY 1 15 CINT DELB 2 14 VREF THERMAL PAD LX1 3 13 PGND 12 PGND LX2 4 DRVP 5 1 DRVN 10 SGND 9 FBL 8 FBP 6 11 FBN DRVL 7 PART MARKING • Up to 20V boost out 20 PG PART NUMBER • 3V to 5V input CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL7585 Absolute Maximum Ratings (TA = 25°C) Thermal Information VDELB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V VDRVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V VDRVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V VLX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) QFN Package. . . . . . . . . . . . . . . . . . . . 39 2.5 VDRVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum continuous junction temperature . . . . . . . . . . . . . . 125°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from -40°C to 85°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT 5.5 V 1.7 2.5 mA 5 20 µA 1000 1100 kHz 20 V SUPPLY VS Supply Voltage IS Quiescent Current 3 Enabled, LX not switching Disabled CLOCK Oscillator Frequency 900 VBOOST Boost Output Range 5.5 VFBB Boost Feedback Voltage FOSC BOOST VF_FBB FBB Fault Trip Point VREF Reference Voltage TA = 25°C 1.192 1.205 1.218 V 1.188 1.205 1.222 V 0.9 TA = 25°C 1.19 1.215 1.235 V 1.187 1.215 1.238 V 100 CREF VREF Capacitor 22 DMAX Maximum Duty Cycle 85 ILXMAX Switch Current Limit ILEAK Switch Leakage Current rDS(ON) Switch On-Resistance Eff Boost Efficiency I(VFBB) Feedback Input Bias Current Pl mode, VFBB = 1.35V ∆VBOOST/ ∆VIN Line Regulation CINT = 4.7nF, IOUT = 100mA, VIN = 3V to 5.5V ∆VBOOST/ ∆IBOOST Load Regulation - “P” mode CINT pin strapped to VDD, 50mA < ILOAD < 250mA ∆VBOOST/ ∆IBOOST Load Regulation - “PI” mode CINT = 4.7nF, 50mA < IO < 250mA VCINT_T CINT Pl Mode Select Threshold nF % 3.5 VLX = 16V See curves 2 V A 10 µA 160 mΩ 92 % 50 500 nA 0.05 %/V 3 % 0.1 % 4.7 4.8 V FN7345.2 March 9, 2006 EL7585 Electrical Specifications PARAMETER VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from -40°C to 85°C, unless otherwise specified. (Continued) DESCRIPTION CONDITION MIN TYP MAX UNIT IDRVP = 0.2mA, TA = 25°C 1.176 1.2 1.224 V IDRVP = 0.2mA 1.172 1.2 1.228 V 0.87 0.92 V 250 nA VON LDO VFBP FBP Regulation Voltage VF_FBP FBP Fault Trip Point VFBP falling 0.82 IFBP FBP Input Bias Current VFBP = 1.35V -250 GMP FBP Effective Transconductance VDRVP = 25V, IDRVP = 0.2 to 2mA ∆VON/∆I(VON) VON Load Regulation 50 I(VON) = 0mA to 20mA 2 ms -0.5 % 4 mA IDRVP DRVP Sink Current Max VFBP = 1.1V, VDRVP = 25V IL_DRVP DRVP Leakage Current VFBP = 1.5V, VDRVP = 35V VFBN FBN Regulation Voltage IDRVN = 0.2mA, TA = 25°C VF_FBN FNN Fault Trip Point IFBN FBN Input Bias Current VFBN = 0.2V -250 GMN FBN Effective Transconductance VDRVN = -6V, IDRVN = 0.2mA to 2mA ∆VOFF/ ∆I(VOFF) VOFF Load Regulation I(VOFF) = 0mA to 20mA IDRVN DRVN Source Current Max VFBN = 0.3V, VDRVN = -6V IL_DRVN DRVN Leakage Current VFBN = 0V, VDRVN = -20V FBL Regulation Voltage IDRVL = 1mA, TA = 25°C 1.176 1.2 1.224 V IDRVL = 1mA 1.174 1.2 1.226 V 0.87 0.92 V 500 nA 0.1 5 µA 0.173 0.203 0.233 V IDRVN = 0.2mA 0.171 0.203 0.235 V VFBN rising 0.38 0.43 0.48 V 250 nA VOFF LDO 2 50 ms -0.5 % 4 mA 0.1 5 µA VLOGIC LDO VFBL VF_FBL FBL Fault Trip Point VFBL falling 0.82 IFBL FBL Input Bias Current VFBL = 1.35V -500 GML FBL Effective Transconductance VDRVL = 2.5V, IDRVL = 1mA to 8mA 200 ms ∆VLOGIC/ ∆I(VLOGIC) VLOGIC Load Regulation I(VLOGIC) = 100mA to 500mA 0.5 % IDRVL DRVL Sink Current Max VFBL = 1.1V, VDRVL = 2.5V 16 mA IL_DRL IL_DRVL VFBL = 1.5V, VDRVL = 5.5V 0.1 tON Turn On Delay CDLY = 0.22µF 30 ms tSS Soft-start Time CDLY = 0.22µF 2 ms tDEL1 Delay Between AVDD and VOFF CDLY = 0.22µF 10 ms tDEL2 Delay Between VON and VOFF CDLY = 0.22µF 17 ms tDEL3 Delay Between VOFF and Delayed VBOOST CDLY = 0.22µF 10 ms IDELB DELB Pull-down Current VDELB > 0.6V 50 µA VDELB < 0.6V 1.4 mA 220 nF 50 ms 8 5 µA SEQUENCING CDEL Delay Capacitor 10 FAULT DETECTION tFAULT Fault Time Out CDLY = 0.22µF 3 FN7345.2 March 9, 2006 EL7585 Electrical Specifications PARAMETER VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from -40°C to 85°C, unless otherwise specified. (Continued) DESCRIPTION CONDITION OT Over-temperature Threshold IPG PG Pull-down Current MIN TYP MAX UNIT 140 °C VPG > 0.6V 15 µA VPG < 0.6V 1.7 mA LOGIC ENABLE VHI Logic High Threshold VLO Logic Low Threshold ILOW Logic Low bias Current IHIGH Logic High bias Current 2.2 V 0.8 at VEN = 5V V 0.2 1 µA 18 24 µA 12 Pin Descriptions PIN NAME PIN NUMBER DESCRIPTION 1 CDLY A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault timeout time 2 DELB Open drain output for gate drive of optional VBOOST delay FET 3, 4 LX1, LX2 5 DRVP 6 FBP 7 DRVL Logic LDO base drive; open drain of an internal N channel FET 8 FBL Logic LDO voltage feedback input pin; regulates to 1.2V nominal 9, 17 SGND Low noise signal ground 10 DRVN Negative LDO base drive; open drain of an internal P channel FET 11 FBN Negative LDO voltage feedback input pin; regulates to 0.2V nominal 12, 13 PGND Power ground, connected to source of internal N channel boost FET 14 VREF Bandgap voltage bypass, connect a 0.1µF to SGND 15 CINT VBOOST integrator output, connect capacitor to SGND for PI mode or connect to VDD for P mode operation 16 FBB Boost regulator voltage feedback input pin; regulates to 1.2V nominal 18 EN Enable pin, High=Enable; Low or floating=Disable 19 VDD 20 PG Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected Positive LDO base drive; open drain of an internal N channel FET Positive LDO voltage feedback input pin; regulates to 1.2V nominal Positive supply Push-pull gate drive of optional fault protection FET, when chip is disabled or when a fault has been detected, this is high 4 FN7345.2 March 9, 2006 EL7585 Typical Performance Curves 100 100 VO=9V 90 80 VO=12V 70 EFFICIENCY (%) EFFICIENCY (%) 80 VO=15V 60 50 40 30 50 40 30 20 10 0.1 0.2 0.3 0.4 0.5 0 0.6 0 0.5 IOUT (A) 100 VO=9V 90 80 70 VO=12V VO=15V 60 EFFICIENCY (%) EFFICIENCY (%) VO=9V 90 80 50 40 30 60 50 40 30 20 20 10 10 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.7 VO=12V VO=15V 70 0 0.5 1 1.5 IOUT (A) IOUT (A) FIGURE 3. VBOOST EFFICIENCY AT VIN=3V (P MODE) FIGURE 4. VBOOST EFFICIENCY AT VIN=5V (P MODE) 0 0 -0.1 -0.2 LOAD REGULATION (%) LOAD REGULATION (%) 1.5 FIGURE 2. VBOOST EFFICIENCY AT VIN=5V (PI MODE) 100 VO=9V -0.3 VO=15V -0.4 -0.5 1 IOUT (A) FIGURE 1. VBOOST EFFICIENCY AT VIN=3V (PI MODE) 0 VO=12V 60 10 0 VO=15V 70 20 0 VO=9V 90 VO=12V 0 0.1 0.2 0.3 IOUT (A) 0.4 0.5 0.6 FIGURE 5. VBOOST LOAD REGULATION AT VIN=3V (PI MODE) 5 -0.1 VO=9V -0.2 -0.3 -0.4 VO=12V -0.5 -0.6 VO=15V 0 0.2 0.4 0.6 0.8 IOUT (A) 1 1.2 1.4 FIGURE 6. VBOOST LOAD REGULATION AT VIN=5V (PI MODE) FN7345.2 March 9, 2006 EL7585 Typical Performance Curves (Continued) 0 0 LOAD REGULATION (%) LOAD REGULATION (%) -1 -2 -3 VO=9V -4 -5 VO=15V -6 -7 -8 VO=12V 0 0.2 0.4 0.6 -2 -4 VO=9V -6 -8 VO=15V 0.8 0 0.5 0 0 -0.1 -0.2 -0.2 -0.3 -0.4 -0.5 20 40 1.5 FIGURE 8. VBOOST LOAD REGULATION AT VIN=5V (P MODE) LOAD REGULATION (%) LOAD REGULATION (%) FIGURE 7. VBOOST LOAD REGULATION AT VIN=3V (P MODE) 0 1 IOUT (A) IOUT (A) -0.6 VO=12V -10 60 80 -0.4 -0.6 -0.8 -1 -1.2 -1.4 0 IOUT (mA) 20 40 60 80 100 IOUT (mA) FIGURE 9. VON LOAD REGULATION FIGURE 10. VOFF LOAD REGULATION LOAD REGULATION (%) 0 -0.2 VCDLY -0.4 EN -0.6 -0.8 VBOOST -1 VLOGIC -1.2 0 100 200 300 400 500 600 700 CDLY=220nF TIME (10ms/DIV) IOUT (mA) FIGURE 11. VLOGIC LOAD REGULATION 6 FIGURE 12. START-UP SEQUENCE FN7345.2 March 9, 2006 EL7585 Typical Performance Curves (Continued) VCDLY VBOOST VREF VLOGIC VBOOST VOFF VLOGIC VON CDLY=220nF CDLY=220nF TIME (10ms/DIV) TIME (10ms/DIV) FIGURE 13. START-UP SEQUENCE FIGURE 14. START-UP SEQUENCE VBOOST-DELAY VLOGIC VOFF VON VIN=5V VOUT=13V IOUT=30mA CDLY=220nF TIME (10ms/DIV) TIME (400ns/DIV) FIGURE 15. START-UP SEQUENCE FIGURE 16. LX WAVEFORM - DISCONTINUOUS MODE VIN=5V VOUT=13V IOUT=200mA TIME (400ns/DIV) FIGURE 17. LX WAVEFORM - CONTINUOUS MODE 7 FN7345.2 March 9, 2006 EL7585 EN REFERENCE GENERATOR VREF SGND OSCILLATOR SLOPE COMPENSATION COMP OSC LX PWM LOGIC CONTROLLER Σ BUFFER VOLTAGE AMPLIFIER FBB GM AMPLIFIER CINT PGND CURRENT AMPLIFIER UVLO COMPARATOR EN CURRENT REF CURRENT LIMIT COMPARATOR VDD SHUTDOWN & START-UP CONTROL PG VREF DRVP BUFFER THERMAL SHUTDOWN FBP UVLO COMPARATOR CDLY SS + - DRVN + - 0.2V VREF DELB SS + - DRVL BUFFER BUFFER FBN 0.4V FBL UVLO COMPARATOR UVLO COMPARATOR FIGURE 18. BLOCK DIAGRAM Applications Information The EL7585 is a highly integrated multiple output power solution for TFT-LCD applications. The system consists of one high efficiency boost converter and three linearregulator controllers (VON, VOFF, and VLOGIC) with multiple protection functions. A block diagram is shown in Figure 18. Table 1 lists the recommended components. The EL7585 integrates an N-channel MOSFET boost converter to minimize external component count and cost. The AVDD, VON, VOFF, and VLOGIC output voltages are independently set using external resistors. VON, VOFF voltages require external charge pumps which are post regulated using the integrated LDO controllers. TABLE 1. RECOMMENDED COMPONENTS (Continued) DESIGNATION D1 DESCRIPTION C1, C2, C3 10µF, 16V X5R ceramic capacitor (1206) TDK C3216X5R0J106K C20, C31 4.7µF, 25V X5R ceramic capacitor (1206) TDK C3216X5R1A475K 8 1A 20V low leakage Schottky rectifier (CASE 45704) ON SEMI MBRM120ET3 D11, D12, D21 200mA 30V Schottky barrier diode (SOT-23) Fairchild BAT54S L1 6.8µH 1.3A Inductor TDK SLF6025T-6R8M1R3-PF Q1 -2.4 -20V P-channel 1.8V specified PowerTrench MOSFET (SuperSOT-3) Fairchild FDN304P Q4 -2A -30V single P-channel logic level PowerTrench MOSFET (SuperSOT-3) Fairchild FDN360P Q3 200mA 40V PNP amplifier (SOT-23) Fairchild MMBT3906 Q2 200mA 40V NPN amplifier (SOT-23) Fairchild MMBT3904 Q5 1A 30V PNP low saturation amplifier (SOT-23) Fairchild FMMT549 TABLE 1. RECOMMENDED COMPONENTS DESIGNATION DESCRIPTION FN7345.2 March 9, 2006 EL7585 Boost Converter The main boost converter is a current mode PWM converter at a fixed frequency of 1MHz which enables the use of low profile inductors and multilayer ceramic capacitors. This results in a compact, low cost power system for LCD panel design. The EL7585 is designed for continuous current mode, but they can also operate in discontinuous current mode at light load. In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by: An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60kΩ is recommended. The boost converter output voltage is determined by the following equation: R1 + R2 A VDD = --------------------- × V REF R1 A VDD 1 ---------------- = ------------1–D V IN The current through the MOSFET is limited to 3.5A peak. This restricts the maximum output current based on the following equation: Where D is the duty cycle of the switching MOSFET. V IN ∆I I OMAX = I LMT – --------L × -------- 2 VO Figure 19 shows the block diagram of the boost regulator. It uses a summing amplifier architecture consisting of GM stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached. Where ∆IL is peak to peak inductor ripple current, and is set by: V IN D ∆I L = --------- × ----L fS where fS is the switching frequency. CLOCK SHUTDOWN & START-UP CONTROL SLOPE COMPENSATION Ifb Iref CURRENT AMPLIFIER PWM LX LOGIC BUFFER Ifb FBB GM AMPLIFIER Iref VOLTAGE AMPLIFIER REFERENCE GENERATOR CINT PGND FIGURE 19. BLOCK DIAGRAM OF THE BOOST REGULATOR 9 FN7345.2 March 9, 2006 EL7585 The following table gives typical values (margins are considered 10%, 3%, 20%, 10%, and 15% on VIN, VO, L, fS, and IOMAX: TABLE 2. capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage. NOTE: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. COUT in the equation above assumes the effective value of the capacitor at a particular voltage and not the manufacturer’s stated value, measured at zero volts. VIN (V) VO (V) L (µH) fS (MHz) IOMAX 3.3 9 6.8 1 1.040686 Compensation 3.3 12 6.8 1 0.719853 3.3 15 6.8 1 0.527353 5 9 6.8 1 1.576797 5 12 6.8 1 1.090686 5 15 6.8 1 0.79902 The EL7585 can operate in either P mode or PI mode. Connecting the CINT pin directly to VIN will enable P mode; For better load regulation, use PI mode with a 4.7nF capacitor in series with a 10K resistor between CINT and ground. This value may be reduced to improve transient performance, however, very low values will reduce loop stability. Input Capacitor Boost feedback resistors An input capacitor is used to supply the peak charging current to the converter. It is recommended that CIN be larger than 10µF. The reflected ripple voltage will be smaller with larger CIN. The voltage rating of input capacitor should be larger than maximum input voltage. As the boost output voltage, AVDD, is reduced below 12V the effective voltage feedback in the IC increases the ratio of voltage to current feedback at the summing comparator because R2 decreases relative to R1. To maintain stable operation over the complete current range of the IC, the voltage feedback to the FBB pin should be reduced proportionally, as AVDD is reduced, by means of a series resistor-capacitor network (R7 and C7) in parallel with R1, with a pole frequency (fp) set to approximately 10kHz for C2 effective = 10µF and 4kHz for C2 (effective) = 30µF. Boost Inductor The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Values of 3.3µH to 10µH are to match the internal slope compensation. The inductor must be able to handle the following average and peak current: R7 = ((1/0.1 x R2) - 1/R1)^-1 C7 = 1/(2 x 3.142 x fp x R7) IO I LAVG = -----------1–D PI mode CINT (C23) and RINT (R10) ∆I I LPK = I LAVG + --------L 2 The IC is designed to operate with a minimum C23 capacitor of 4.7nF and a minimum C2 (effective) = 10µF. Rectifier Diode A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The rectifier diode must meet the output current and peak inductor current requirements. Output Capacitor The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor. V O – V IN IO 1 V RIPPLE = I LPK × ESR + ------------------------ × ---------------- × ----VO C OUT f S For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output 10 Note that, for high voltage AVDD, the voltage coefficient of ceramic capacitors (C2) reduces their effective capacitance greatly; a 16V 10µF ceramic can drop to around 3µF at 15V. To improve the transient load response of AVDD in PI mode, a resistor may be added in series with the C23 capacitor. The larger the resistor the lower the overshoot but at the expense of stability of the converter loop - especially at high currents. With L = 10µH, AVDD = 15V, C23 = 4.7nF, C2 (effective) should have a capacitance of greater than 10µF. RINT (R7) can have values up to 5kΩ for C2 (effective) up to 20µF and up to 10K for C2 (effective) up to 30µF. Larger values of RINT (R7) may be possible if maximum AVDD load currents less than the current limit are used. To ensure AVDD stability, the IC should be operated at the maximum desired current and then the transient load response of AVDD should be used to determine the maximum value of RINT. FN7345.2 March 9, 2006 EL7585 Operation of the DELB Output Function An open drain DELB output is provided to allow the boost output voltage, developed at C2 (see application diagram), to be delayed via an external switch (Q4) to a time after the VBOOST supply and negative VOFF charge pump supply have achieved regulation during the start-up sequence shown in Figure 28. This then allows the AVDD and VON supplies to start-up from 0V instead of the normal offset voltage of VIN-VDIODE (D1) if Q4 were not present. When DELB is activated by the start-up sequencer, it sinks 50µA allowing a controlled turn-on of Q4 and charge-up of C9. C16 can be used to control the turn-on time of Q4 to reduce inrush current into C9. The potential divider formed by R9 and R8 can be used to limit the VGS voltage of Q4 if required by the voltage rating of this device. When the voltage at DELB falls to less than 0.6V, the sink current is increased to ~1.2mA to firmly pull DELB to 0V. The voltage at DELB is monitored by the fault protection circuit so that if the initial 50µA sink current fails to pull DELB below ~0.6V after the start-up sequencing has completed, then a fault condition will be detected and a fault time-out ramp will be initiated on the CDEL capacitor (C7). Operation of the PG Output Function The PG output consists of an internal pull-up PMOS device to VIN, to turn-off the external Q1 protection switch and a current limited pull-down NMOS device which sinks ~15µA allowing a controlled turn-on of Q1 gate capacitance. CO is used to control how fast Q1 turns-on - limiting inrush current into C1. When the voltage at the PG pin falls to less than 0.6V, the PG sink current is increased to ~1.2mA to firmly pull the pin to 0V. The voltage at PG is monitored by the fault protection circuit so that if the initial 15µA sink current fails to pull PG below ~0.6V after the start-up sequencing has completed, then a fault condition will be detected and a fault time-out ramp will be initiated on the CDEL capacitor (C7). Cascaded MOSFET Application A 20V N-channel MOSFET is integrated in the boost regulator. For the applications where the output voltage is greater than 20V, an external cascaded MOSFET is needed 11 as shown in Figure 20. The voltage rating of the external MOSFET should be greater than VBOOST. VBOOST VIN LX FB EL7585 FIGURE 20. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS Linear-Regulator Controllers (VON, VLOGIC, and VOFF) The EL7585 includes three independent linear-regulator controllers, in which two are positive output voltage (VON and VLOGIC), and one is negative. The VON, VOFF, and VLOGIC linear-regulator controller functional diagrams, applications circuits are shown in Figures 21, 22, and 23 respectively. Calculation of the Linear Regulator Base-Emitter Resistors (RBL, RBP and RBN) For the pass transistor of the linear regulator, low frequency gain (Hfe) and unity gain freq. (fT) are usually specified in the datasheet. The pass transistor adds a pole to the loop transfer function at fp=fT/Hfe. Therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency low gain switching transistor. Further improvement can be obtained by adding a base-emitter resistor RBE (RBP, RBL, RBN in the Functional Block Diagram), which increase the pole frequency to: fp=fT*(1+ Hfe *re/RBE)/Hfe, where re=KT/qIc. So choose the lowest value RBE in the design as long as there is still enough base current (IB) to support the maximum output current (IC). We will take as an example the VLOGIC linear regulator. If a Fairchild FMMT549 PNP transistor is used as the external pass transistor, Q5 in the application diagram, then for a maximum VLOGIC operating requirement of 500mA the data sheet indicates Hfe_min = 100. FN7345.2 March 9, 2006 EL7585 The base-emitter saturation voltage is: Vbe_max = 1.25V (note this is normally a Vbe ~ 0.7V, however, for the Q5 transistor an internal Darlington arrangement is used to increase it's current gain, giving a 'base-emitter' voltage of 2 x VBE). (Note that using a high current Darlington PNP transistor for Q5 requires that VIN > VLOGIC + 2V. Should a lower input voltage be required, then an ordinary high gain PNP transistor should be selected for Q5 so as to allow a lower collector-emitter saturation voltage). LX 0.1µF CP (TO -26V) LDO_OFF PG_LDON 0.4V FBN For the EL7585, the minimum drive current is: I_DRVL_min = 8mA DRVN LX VIN OR VPROT (3V TO 6V) LDO_LOG PG_LDOL RBL 500Ω + - Q5 0.1µF VLOGIC (1.3V TO 3.6V) DRVL LDO_ON RL1 CP (TO 36V) 36V ESD CLAMP COFF Q2 FIGURE 22. VOFF FUNCTIONAL BLOCK DIAGRAM 0.9V VBOOST RBN 3kΩ 36V ESD CLAMP This is the minimum value that can be used - so, we now choose a convenient value greater than this minimum value; say 500Ω. Larger values may be used to reduce quiescent current, however, regulation may be adversely affected, by supply noise if RBL is made too high in value. + - RN1 VOFF (TO -20V) + GMN RBL_min = VBE_max/(I_DRVL_min - Ic/Hfe_min) = 1.25V/(8mA - 500mA/100) = 417Ω PG_LDOP 0.1µF RN2 20kΩ 1: Nn The minimum base-emitter resistor, RBL, can now be calculated as: 0.9V VREF + CLOG 10µF FBL RBP 7kΩ 0.1µF Q3 VON (TO 35V) DRVP FBP RP1 RP2 20kΩ + GMP CON + GML RL2 20kΩ 1: N1 FIGURE 23. VLOGIC FUNCTIONAL BLOCK DIAGRAM 1: Np FIGURE 21. VON FUNCTIONAL BLOCK DIAGRAM The VON power supply is used to power the positive supply of the row driver in the LCD panel. The DC/DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_ON). The LDO_ON regulator uses an external PNP transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 4mA drive current, which is sufficient for up to 40mA or more output current under the low dropout condition (forced beta of 10). Typical VON voltage supported by EL7585 ranges from +15V to +36V. A fault comparator is also included for monitoring the output voltage. The under-voltage threshold is set at 25% below the 1.2V reference. The VOFF power supply is used to power the negative supply of the row driver in the LCD panel. The DC/DC 12 FN7345.2 March 9, 2006 EL7585 consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_OFF). The LDO_OFF regulator uses an external NPN transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 4mA drive current, which is sufficient for up to 40mA or more output current under the low dropout condition (forced beta of 10). Typical VOFF voltage supported by EL7585 ranges from -5V to -20V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 200mV above the 0.2V reference level. the transistor. VF is the forward-voltage of the charge pump rectifier diode. The VLOGIC power supply is used to power the logic circuitry within the LCD panel. The DC/DC may be powered directly from the low voltage input, 3.3V or 5.0V, or it may be powered through the fault protection switch. The LDO_LOGIC regulator uses an external PNP transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 16mA drive current, which is sufficient for up to 160mA or more output current under the low dropout condition (forced beta of 10). Typical VLOGIC voltage supported by EL7585 ranges from +1.3V to VDD-0.2V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 25% below the 1.2V reference. In the applications where the charge pump output voltage is over 36V, an external npn transistor need to be inserted into between DRVP pin and base of pass transistor Q3 as shown in Figure 24; or the linear regulator can control only one stage charge pump and regulate the final charge pump output as shown in Figure 25. The number of negative charge pump stages is given by: V OUTPUT + V CE N NEGATIVE ≥ ------------------------------------------------V INPUT – 2 × V F To achieve high efficiency and low material cost, the lowest number of charge pump stages which can meet the above requirements, is always preferred. High Charge Pump Output Voltage (>36V) Applications CHARGE PUMP VIN OUTPUT OR AVDD 7kΩ DRVP Set-Up Output Voltage NPN CASCODE TRANSISTOR Q3 VON EL7585 Refer to the Typical Application Diagram, the output voltages of VON, VOFF, and VLOGIC are determined by the following equations: FBP R 12 V ON = V REF × 1 + --------- R 11 R 22 V OFF = V REFN + ---------- × ( V REFN – V REF ) R 21 FIGURE 24. CASCODE NPN TRANSISTOR CONFIGURATION FOR HIGH CHARGE PUMP OUTPUT VOLTAGE (>36V) R 42 V LOGIC = V REF × 1 + --------- R 41 LX 0.1µF Where VREF = 1.2V, VREFN = 0.2V. AVDD 0.1µF Resistor networks in the order of 250kΩ, 120kΩ and 10kΩ are recommended for VON, VOFF and VLOGIC, respectively. 7kΩ Charge Pump DRVP To generate an output voltage higher than VBOOST, single or multiple stages of charge pumps are needed. The number of stage is determined by the input and output voltage. For positive charge pump stages: V OUT + V CE – V INPUT N POSITIVE ≥ -------------------------------------------------------------V INPUT – 2 × V F where VCE is the dropout voltage of the pass component of the linear regulator. It ranges from 0.3V to 1V depending on 13 Q3 0.1µF 0.1µF VON 0.47µF EL7585 (>36V) 0.1µF 0.22µF FBP FIGURE 25. THE LINEAR REGULATOR CONTROLS ONE STAGE OF CHARGE PUMP FN7345.2 March 9, 2006 EL7585 Discontinuous/Continuous Boost Operation and its Effect on the Charge Pumps detected, the outputs and the input protection will turn off and the chip will power down. The EL7585 VON and VOFF architecture uses LX switching edges to drive diode charge pumps from which LDO regulators generate the VON and VOFF supplies. It can be appreciated that should a regular supply of LX switching edges be interrupted, for example during discontinuous operation at light AVDD boost load currents, then this may affect the performance of VON and VOFF regulation depending on their exact loading conditions at the time. If no fault is found, CCDLY continues ramping up and down until the sequence is completed. To optimize VON/VOFF regulation, the boundary of discontinuous/continuous operation of the boost converter can be adjusted, by suitable choice of inductor given VIN, VOUT, switching frequency and the AVDD current loading, to be in continuous operation. The following equation gives the boundary between discontinuous and continuous boost operation. For continuous operation (LX switching every clock cycle) we require that: I(AVDD_load) > D*(1-D)*VIN/(2*L*FOSC) where the duty cycle, D = (AVDD - VIN)/AVDD For example, with VIN = 5V, FOSC = 1.0MHz and AVDD = 12V we find continuous operation of the boost converter can be guaranteed for: L = 10µH and I(AVDD) > 61mA During the second ramp, the device checks the status of VREF and over temperature. At the peak of the second ramp, PG output goes low and enables the input protection PMOS Q1. Q1 is a controlled FET used to prevent in-rush current into VBOOST before VBOOST is enabled internally. Its rate of turn on is controlled by Co. When a fault is detected, M1 will turn off and disconnect the inductor from VIN. With the input protection FET on, NODE1 (See Typical Application Diagram) will rise to ~VIN. Initially the boost is not enabled so VBOOST rises to VIN-VDIODE through the output diode. Hence, there is a step at VBOOST during this part of the start-up sequence. If this step is not desirable, an external PMOS FET can be used to delay the output until the boost is enabled internally. The delayed output appears at AVDD. For EL7585, VBOOST and VLOGIC soft-start at the beginning of the third ramp. The soft-start ramp depends on the value of the CDLY capacitor. For CDLY of 220nF, the soft-start time is ~2ms. VOFF turns on at the start of the fourth peak. At the fifth peak, the open drain o/p DELB goes low to turn on the external PMOS Q4 to generate a delayed VBOOST output. L = 6.8µH and I(AVDD) > 89mA VON is enabled at the beginning of the sixth ramp. AVDD, PG, VOFF, DELB and VON are checked at end of this ramp. L = 3.3µH and I(AVDD) > 184mA Fault Protection Charge Pump Output Capacitors During the startup sequence, prior to BOOST soft-start, VREF is checked to be within ±20% of its final value and the device temperature is checked. If either of these are not within the expected range, the part is disabled until the power is recycled or EN is toggled. Ceramic capacitors with low ESR are recommended. With ceramic capacitors, the output ripple voltage is dominated by the capacitance value. The capacitance value can be chosen by the following equation: I OUT C OUT ≥ -----------------------------------------------------2 × V RIPPLE × f OSC where fOSC is the switching frequency. Start-Up Sequence Figure 26 shows a detailed start-up sequence waveform. For a successful power-up, there should be six peaks at VCDLY. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. If EN is L, the device is powered down. If EN is H, and the input voltage (VDD) exceeds 2.5V, an internal current source starts to charge CDLY to an upper threshold using a fast ramp followed by a slow ramp. If EN is low at this point, the CDLY ramp will be delayed until EN goes high. The first four ramps on CDLY (two up, two down) are used to initialize the fault protection switch and to check whether there is a fault condition on CDLY or VREF. If a fault is 14 If CDELAY is shorted low, then the sequence will not start, while if CDELAY is shorted H, the first down ramp will not occur and the sequence will not complete. Once the start-up sequence is completed, the chip continuously monitors CDLY, DELB, FBP, FBL, FBN, VREF, FBB and PG and checks for faults. During this time, the voltage on the CDLY capacitor remains at 1.15V until either a fault is detected, or the EN pin is pulled low. A fault on CDELAY, VREF or temperature will shut down the chip immediately. If a fault on any other output is detected, CDELAY will ramp up linearly with a 5µA (typical) current to the upper fault threshold (typically 2.4V), at which point the chip is disabled until the power is recycled or EN is toggled. If the fault condition is removed prior to the end of the ramp, the voltage on the CDLY capacitor returns to 1.15V. FN7345.2 March 9, 2006 EL7585 Typical fault thresholds for FBP, FBL, FBN and FBB are included in the tables. PG and DELB fault thresholds are typically 0.6V. CINT has an internal current-limited clamp to keep the voltage within its normal range. If CINT is shorted low, the boost regulator will attempt to regulate to 0V. If CINT is shorted H, the regulator switches to P mode. If any of the regulated outputs (VBOOST, VON, VOFF or VLOGIC) are driven above their target levels the drive circuitry will switch off until the output returns to its expected value. If VBOOST is excessively loaded, the current limit will prevent damage to the chip. While in current limit, the part acts like a current source and the regulated output will drop. If the output drops below the fault threshold, a ramp will be initiated on CDELAY and, provided that the fault is sustained, the chip will be disabled on completion of the ramp. In some circumstances, (depending on ambient temperature and thermal design of the board), continuous operation at current limit may result in the over-temperature threshold being exceeded, which will cause the part to disable immediately. All I/O also have ESD protection, which in many cases will also provide overvoltage protection, relative to either ground or VDD. However, these will not generally operate unless abs max ratings are exceeded. 15 Component Selection for Start-Up Sequencing and Fault Protection The CREF capacitor is typically set at 220nF and is required to stabilize the VREF output. The range of CREF is from 22nF to 1µF and should not be more than five times the capacitor on CDEL to ensure correct start-up operation. The CDEL capacitor is typically 220nF and has a usable range from 47nF minimum to several microfarads - only limited by the leakage in the capacitor reaching µA levels. CDEL should be at least 1/5 of the value of CREF (See above). Note with 220nF on CDEL the fault time-out will be typically 50ms and the use of a larger/smaller value will vary this time proportionally (e.g. 1µF will give a fault time-out period of typically 230ms). Fault Sequencing The EL7585 has an advanced fault detection system which protects the IC from both adjacent pin shorts during operation and shorts on the output supplies. A high quality layout/design of the PCB, in respect of grounding quality and decoupling is necessary to avoid falsely triggering the fault detection scheme - especially during start-up. The user is directed to the layout guidelines and component selection sections to avoid problems during initial evaluation and prototype PCB generation. FN7345.2 March 9, 2006 CHIP DISABLED FAULT DETECTED VON SOFT-START DELB ON VOFF ON AVDD, VLOGIC SOFT-START PG ON VREF ON EL7585 VCDLY EN VREF VBOOST tON tOS VLOGIC VOFF tDEL1 DELAYED VBOOST tDEL2 FAULT PRESENT START-UP SEQUENCE TIMED BY CDLY NORMAL OPERATION VON FIGURE 26. START-UP SEQUENCE 16 FN7345.2 March 9, 2006 EL7585 Over-Temperature Protection An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point of 140°C, the device will shut down. Layout Recommendation The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VDD bypass capacitors close to the pins. 3. Minimize the length of traces carrying fast signals and high current. 4. All feedback networks should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point near the main decoupling capacitors. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. A signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for feedback resistor networks (R1, R11, R41) and the VREF capacitor, C22, the CDELAY capacitor C7 and the integrator capacitor C23. 9. Minimize feedback input track lengths to avoid switching noise pick-up. A two-layer demo board is available to illustrate the proper layout implementation. A four-layer demo board can be used to further optimize the layout recommendations. Demo Board Layout FIGURE 27. TOP LAYER 17 FIGURE 28. BOTTOM LAYER FN7345.2 March 9, 2006 EL7585 Typical Application Diagram LX VIN C0 C1 1nF 10µF x2 PG CDELAY C10 D1 6.8µH C7 46.5kΩ LX R2 R1 5kΩ FBB AVDD (12V) Q4 R9 C2 10µF 1MΩ X2 R7 OPEN C9 C16 0.1µF 22nF R8 C7 OPEN 10kΩ 0.22µF 4.7µF C41 NODE 1 10Ω C6 4.7µF R7 10kΩ VDD 0.1µF VREF C22 CINT R41 CP 1nF DRVP C14 0.1µF Q3 R12 C11 0.1µF C13 0.1µF 7kΩ VREF FBP 5.4kΩ 10kΩ LX 4.7nF R13 DRVL R42 R10 C 23 EN 0.1µF 500Ω Q5 DELB R6 R43 VLOGIC (2.5V) C 31 4.7µF L1 NODE 1 Q1 C12 D12 0.1µF D11 230kΩ R11 C15 20kΩ 0.47µF FBL VON (15V) C24 LX 0.1µF R23 5kΩ C25 3kΩ DRVN FBN SGND PGND 0.1µF D21 Q2 R22 104K R21 C20 20K 4.7µF VOFF (-5V) VREF NOTE: The SGND should be connected to the exposed die plate and connected to the PGND at one point only. 18 FN7345.2 March 9, 2006 EL7585 QFN Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 19 FN7345.2 March 9, 2006