EL8176 ® Data Sheet PRELIMINARY October 5, 2005 Micropower Single Supply Rail-to-Rail Input-Output Precision Op Amp Features • 55µA supply current The EL8176 is a micropower precision operational amplifier optimized for single supply operation at 5V and can operate down to 2.4V. The EL8176 draws minimal supply current while meeting excellent DC-accuracy noise and output drive specifications. Competing devices seriously degrade these parameters to achieve micropower supply current. Offset current, voltage and current noise, slew rate, and gain-bandwidth product are all two to ten times better than on previous micropower op amps. The EL8176 can be operated from one lithium cell or two Ni-Cd batteries. The input range includes both positive and negative rail. The output swings to both rails. Ordering Information PART NUMBER PART MARKING • 100µV max offset voltage • 500pA input bias current • 400kHz gain-bandwidth product • 1MHz -3dB bandwidth • 0.13V/µs slew rate • Single supply operation down to 2.4V • Rail-to-rail input and output • Output sources and sinks 26mA load current • Pb-free plus anneal available (RoHS compliant) Applications • Battery- or solar-powered systems PACKAGE TAPE & REEL PKG. DWG. # EL8176AIW-T7 BBGA 6 Ld SOT-23 7” MDP0038 (3K pcs) EL8176AIW-T7A BBGA 6 Ld SOT-23 7” MDP0038 (250 pcs) EL8176AIWZ-T7 (Note) BBNA 6 Ld SOT-23 7” MDP0038 (Pb-free) (3K pcs) EL8176AIWZ-T7A (Note) BBNA 6 Ld SOT-23 7” MDP0038 (Pb-free) (250 pcs) EL8176BIW-T7 BBGA 6 Ld SOT-23 7” MDP0038 (3K pcs) EL8176BIW-T7A BBGA 6 Ld SOT-23 7” MDP0038 (250 pcs) EL8176BIWZ-T7 (Note) BBNA 6 Ld SOT-23 7” MDP0038 (Pb-free) (3K pcs) EL8176BIWZ-T7A (Note) BBNA 6 Ld SOT-23 7” MDP0038 (Pb-free) (250 pcs) EL8176ISZ (Note) 8176ISZ 8 Ld SO (Pb-free) - MDP0027 EL8176ISZ-T7 (Note) 8176ISZ 8 Ld SO (Pb-free) 7” MDP0027 EL8176ISZ-T13 (Note) 8176ISZ 8 Ld SO (Pb-free) 13” MDP0027 • 4mA to 20mA current loops • Handheld consumer products • Medical devices • Thermocouple amplifiers • Photodiode pre amps • pH probe amplifiers Pinouts EL8176 (6 LD SOT-23) TOP VIEW OUT 1 VS- 2 6 VS+ + - IN+ 3 5 ENABLE 4 IN- EL8176 (8 LD SO) TOP VIEW NC 1 IN- 2 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 FN7436.2 IN+ 3 VS- 4 8 ENABLE + 7 VS+ 6 VOUT 5 NC CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. EL8176 Absolute Maximum Ratings (TA = 25°C) Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature Range . . . . . . . . . .-40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VS + 0.5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VOS VS = 5V, 0V, VCM = 0.1V, VO = 1.4V, TA = 25°C unless otherwise specified. DESCRIPTION Input Offset Voltage CONDITIONS MIN TYP MAX UNIT Grade A 50 100 µV Grade B 110 400 µV ∆V OS -----------------∆Time Long Term Input Offset Voltage Stability ∆V OS ---------------∆T Input Offset Drift vs Temperature IOS Input Offset Current 0.4 1.2 nA IB Input Bias Current 0.5 2 nA eN Input Noise Voltage Density fO = 1kHz 25 nV/√Hz iN Input Noise Current Density fO = 1kHz 0.1 pA/√Hz CMIR Input Voltage Range Guaranteed by CMRR test 0 CMRR Common-Mode Rejection Ratio VCM = 0V to 5V 90 110 dB PSRR Power Supply Rejection Ratio VS = 2.4V to 5V 90 110 dB AVOL Large Signal Voltage Gain VO = 0.5V to 4.5V, RL = 100kΩ 200 500 V/mV VO = 0.5V to 4.5V, RL = 1kΩ 25 V/mV Output low, RL = 100kΩ 3 6 mV 130 200 mV VOUT Maximum Output Voltage Swing TBD µV/Mo EL8176IW 0.7 µV/°C EL8176IS 0.3 µV/°C Output low, RL = 1kΩ Output high, RL = 100kΩ Output high, RL = 1kΩ 5 V 4.994 4.997 V 4.8 4.88 V 0.09 0.13 SR Slew Rate GBW Gain Bandwidth Product fO = 100kHz BW -3dB Bandwidth Unity gain, CLOAD = 27pF, RF = 100Ω IS,ON Supply Current, Enabled IS,OFF Supply Current, Disabled IO+ Short Circuit Output Current RL = 10Ω 18 31 mA IO- Short Circuit Output Current RL = 10Ω 17 26 mA VS Minimum Supply Voltage VINH Enable Pin High Level VINL Enable Pin Low Level IENH Enable Pin Input Current VEN = 5V 0.25 0.7 2 µA IENL Enable Pin Input Current VEN = 0V -0.5 0 +0.5 µA 2 40 0.17 V/µs 400 kHz 1 MHz 55 75 µA 3 10 µA 2.2 2.4 V 2 V 0.8 V FN7436.2 October 5, 2005 EL8176 Typical Performance Curves 45 6 40 VS=±1.25V 3 35 GAIN (dB) GAIN (dB) 30 0 VS=±2.5V -3 -6 VS=±1.0V AV=1 CL=27pF RF=100Ω RG=OPEN -9 1K 10K 100K 1M FREQUENCY (Hz) 10M 50 40 30 20 10 2.5 3 3.5 4 4.5 AV=100 15 RL=10kΩ CL=2.7pF 10 R /R =99.02 F G RF=221kΩ 5 RG=2.23kΩ 0 100 1K 5 5.5 INPUT OFFSET VOLTAGE (µV) INPUT OFFSET VOLTAGE (µV) 100 VDD=5V 0 VDD=2.5V -100 -150 1 1M 1K IB+ 100 IOS IB- 10 1 0 1 2 3 4 5 0 VCM=VDD/2 150 AV=-1 0 100K FIGURE 4. INPUT BIAS + OFFSET CURRENTS vs COMMONMODE INPUT VOLTAGE 200 -200 10K COMMON-MODE INPUT VOLTAGE (V) FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE -50 VS=±1.0V 10K SUPPLY VOLTAGE (V) 50 VS=±1.25V FIGURE 2. FREQUENCY RESPONSE vs SUPPLY VOLTAGE INPUT BIAS, OFFSET CURRENTS (pA) SUPPLY CURRENT (µA) 60 2 VS=±2.5V 20 FREQUENCY (Hz) FIGURE 1. UNITY GAIN FREQUENCY RESPONSE vs SUPPLY VOLTAGE 0 25 2 3 4 5 OUTPUT VOLTAGE (V) FIGURE 5. INPUT OFFSET VOLTAGE vs OUTPUT VOLTAGE 3 -20 VOS, µV -40 -60 -80 -100 0 1 2 3 4 5 COMMON-MODE INPUT VOLTAGE (V) FIGURE 6. INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE FN7436.2 October 5, 2005 EL8176 (Continued) 200 100 150 80 PHASE GAIN (dB) 0 GAIN PHASE (°) GAIN (dB) 50 40 -100 100 1K 10K 80 40 40 0 0 -40 -40 -80 -50 0 -20 10 80 100 60 20 120 100K -80 -150 1M 1 10 100K 1M -120 10M FIGURE 8. AVOL vs FREQUENCY @ 100kΩ LOAD 1K VOLTAGE NOISE (nV/√Hz) 10.00 CURRENT NOISE (pA/√Hz) 10K FREQUENCY (Hz) FIGURE 7. AVOL vs FREQUENCY @ 1kΩ LOAD 1.00 0.10 1 10 100 1K 10K 100 10 1 10 100K 100 FREQUENCY (Hz) 1K 10K 100K FREQUENCY (Hz) FIGURE 10. VOLTAGE NOISE vs FREQUENCY FIGURE 9. CURRENT NOISE vs FREQUENCY 120 120 110 110 100 100 90 90 80 80 PSRR (dB) CMRR (dB) 1K 100 FREQUENCY (Hz) 0.01 PHASE (°) Typical Performance Curves 70 60 50 PSRR+ 70 60 50 40 40 30 30 20 20 10 10 PSRR- 0 0 1 10 100 1K 10K 100K FREQUENCY (Hz) FIGURE 11. CMRR vs FREQUENCY 4 1M 1 10 100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 12. PSRR vs FREQUENCY FN7436.2 October 5, 2005 EL8176 Typical Performance Curves (Continued) 130 500 SOT23-6 PACKAGE 10 SAMPLES INPUT OFFSET VOLTAGE (µV) 400 SOT23-6 PACKAGE 125 300 120 200 115 PSRR (dB) 100 0 -100 110 105 -200 100 -300 95 -400 -500 -50 0 50 90 100 -50 0 FIGURE 13. VOS vs TEMPERATURE 130 SOT23-6 PACKAGE OPEN LOOP GAIN (dB) CMRR (dB) 110 105 100 95 SOT23-6 PACKAGE 125 120 115 110 105 90 -60 -40 -20 0 20 40 60 80 100 -60 100 -40 -20 TEMPERATURE (°C) 20 40 60 80 100 FIGURE 16. AVOL vs TEMPERATURE 70 2000 1500 0 TEMPERATURE (°C) FIGURE 15. CMRR vs TEMPERATURE SOT23-6 PACKAGE 65 SOT23-6 PACKAGE 60 1000 55 500 IS (mA) IB (pA) 100 FIGURE 14. PSRR vs TEMPERATURE 120 115 50 TEMPERATURE (°C) TEMPERATURE (°C) 0 50 45 -500 40 -1000 -1500 -60 35 30 -40 -20 0 20 40 60 80 TEMPERATURE (°C) FIGURE 17. IB vs TEMPERATURE 5 100 -60 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) FIGURE 18. IS vs TEMPERATURE FN7436.2 October 5, 2005 EL8176 Typical Performance Curves 20 (Continued) 500 36 SOIC SAMPLES TYPICAL = 0.30µV/C 0 400 300 -20 200 VOS (µV) VOS (µV) -40 -60 -80 -100 100 0 -100 -200 -120 -300 -140 -400 -160 -60 -40 -20 0 20 40 60 80 -500 100 120 36 6-PIN SOT SAMPLES TYPICAL = 0.67µV/C -60 -40 -20 0 FIGURE 19. EL8176SOIC VOS vs TEMPERATURE (VS = 5V) 0.7 SO T2 θJ 3-6 A =2 30 °C /W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Applications Information Introduction The EL8176 is a rail-to-rail input and output micro-power precision single supply operational amplifier with an enable feature. The device achieves rail-to-rail input and output operation and eliminates the concerns introduced by a conventional rail-to-rail I/O operational amplifier. Rail-to-Rail Input The input common-mode voltage range of the EL8176 goes from negative supply to positive supply without introducing offset errors or degrading performance associated with a conventional rail-to-rail input operational amplifier. Many railto-rail input stages use two differential input pairs, a long-tail PNP (or PFET) and an NPN (or NFET). Severe penalties have to be paid for this circuit topology. As the input signal moves from one supply rail to another, the operational amplifier switches from one input pair to the other causing 6 100 120 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.6 625mW 0.5 8 /W SO 0°C 6 =1 435mW 80 A A 8 /W SO 0°C 1 =1 0.6 60 θJ POWER DISSIPATION (W) 909mW 0.8 40 FIGURE 20. EL8176SOT VOS vs TEMPERATURE (VS = 5V) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD θJ POWER DISSIPATION (W) 1 20 TEMPERATURE (°C) TEMPERATURE (°C) 0.4 391mW θ 0.3 SO JA = 0.2 25 T2 3- 6 6° C/ W 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 22. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE drastic changes in input offset voltage and an undesired change in magnitude and polarity of input offset current. The EL8176 achieves input rail-to-rail without sacrificing important precision specifications and without degrading distortion performance. The EL8176's input offset voltage exhibits a smooth behavior throughout the entire commonmode input range. The input bias current versus the common-mode voltage range for the EL8176 gives us an undistorted behavior from typically 10mV above the negative rail all the way up to the positive rail. 10mV above the negative rail to the positive rail is the range of operation of yet another feature of the EL8176, input bias current compensation. Input Bias Current Compensation The input bias currents of the EL8176 are decimated down to a typical of 500pA while maintaining an excellent bandwidth for a micro-power operational amplifier. Inside the EL8176 is an input bias canceling circuit. The input stage FN7436.2 October 5, 2005 EL8176 transistors are still biased with an adequate current for speed but the canceling circuit sinks most of the base current, leaving a small fraction as input bias current. The input bias current compensation/cancellation operates from typically 10mV to the positive supply rail and also from -40°C to 85°C. Rail-to-Rail Output A pair of complementary MOSFET devices achieves rail-torail output swing. The NMOS sinks current to swing the output in the negative direction. The PMOS sources current to swing the output in the positive direction. The EL8176 with a 100kΩ load will swing to within 3mV of the supply rails. FIGURE 24. Enable/Disable Feature The EL8176 offers an EN pin. The active low enable pin disables the device when pulled up to at least 2.2V. Upon disable the part consumes typically 3µA, while the output is in a high impedance state. The EN also has an internal pull down. If left open, the EN pin will pull to negative rail and the device will be enabled by default. The high impedance at output during disable allows multiple EL8176s to be connected together as a MUX. The outputs are tied together in parallel and a channel can be selected by the EN pin. Proper Layout Maximizes Performance HIGH IMPEDANCE INPUT 6 To achieve the maximum performance of the high input impedance and low offset voltage of the EL8176, care should be taken in the circuit board layout. The PC board surface must remain clean and free of moisture to avoid leakage currents between adjacent traces. Surface coating of the circuit board will reduce surface moisture and provide a humidity barrier, reducing parasitic resistance on the board. The use of guard rings around the amplifier inputs will further reduce leakage currents. Figure 23 shows how the guard ring should be configured and Figure 24 shows the top view of how a surface mount layout can be arranged. The guard ring does not need to be a specific width, but it should form a continuous loop around both inputs. By setting the guard ring voltage equal to the voltage at the non-inverting input, parasitic capacitance is minimized as well. For further reduction of leakage currents, components can be mounted to the PC board using Teflon standoff insulators. Typical Applications R4 100kΩ R3 10kΩ R2 K TYPE THERMOCOUPLE 10kΩ V+ + EL8176 V- 410µV/°C + 5V R1 100kΩ FIGURE 25. THERMOCOUPLE AMPLIFIER Thermocouples are the most popular temperature-sensing device because of their low cost, interchangeability, and ability to measure a wide range of temperatures. The EL8176 is used to convert the differential thermocouple voltage into single-ended signal with 10X gain. The EL8176's rail-to-rail input characteristic allows the thermocouple to be biased at ground and the converter to run from a single 5V supply. V+ EL8176 3 1 4 2 5 IN FIGURE 23. 7 FN7436.2 October 5, 2005 EL8176 SO Package Outline Drawing 8 FN7436.2 October 5, 2005 EL8176 SOT-23 Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 9 FN7436.2 October 5, 2005