EM78P468N
OTP ROM
EM78P468N
8-BIT MICRO-CONTROLLER
Version 1.0
EM78P468N
OTP ROM
Version
1.0
Specification Revision History
Content
Initial version
2004/4/10
Application Note
This specification is subject to change without prior notice.
2
04.10.2004 (V1.0)
EM78P468N
OTP ROM
1. GENERAL DESCRIPTION
The EM78P468N is an 8-bit RISC type microprocessor with high speed CMOS technology and low
power consumption. Integrated onto a single chip are on chip watchdog (WDT), Data RAM, ROM,
programmable real time clock counter, internal/external interrupt, power down mode, LCD driver
IROUT function, and tri-state I/O. It provides a PROTECTION bit to protect against intrusion of user’s
code in the OTP memory and a 10-OPTION bit to accommodate user’s requirements. It also provides a
especial 13 bits customer ID option.
With its OTP-ROM feature, the EM78P468N offers a convenient way of developing and verifying user’s
programs. Moreover, user developed code can be easily programmed with the ELAN writer.
2. FEATURES
CPU
Operating voltage range : 2.2V∼5.5V
Operating temperature range: -40°C ~ +85°C.
Dual clock operation
High frequency oscillator can select between Crystal, RC, or PLL (phase lock loop)
Low frequency oscillator can select between Crystal or RC mode
Totally 272 bytes SRAM
144 bytes general purpose register
128 bytes bits on chip data RAM
4K*13 bits on chip Electrical OTP-ROM (One Time Programmable Read Only Memory).
Up to 28 bi-directional tri-state I/O ports
Typically, 12 bi-directional tri-state I/O ports.
16 bi-directional tri-state I/O ports shared with LCD segment output pin.
8-level stack for subroutine nesting
8-bit real time clock/counter (TCC)
One IROUT/PWM generator
Four sets of 8 bit auto reload counter/timer can be used as interrupt sources
Counter 1: independent counter
Counter 2, High Pulse Width Timer (HPWT), and Low Pulse Width Timer (LPWT) shared with IR
function
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
Programmable free running on chip watchdog timer (WDT)
Low voltage detector (LVD)
Operation modes
Normal mode :CPU operate on high frequency oscillator
Green mode :CPU operate on low frequency oscillator
Idle mode :CPU idle, LCD display remains working
Sleep mode :whole chip stop working
Input port wake up function (PORT6, PORT8)
9 interrupt sources, 3 external, 6 internal
Internal: TCC; Counter1, 2; High pulse width timer; Low pulse width timer; & Low voltage detector
External: INT0, INT1, & Pin change wake-up (Port 6 and Port 8)
59 pin dice/ 64 pin QFP package
LCD
Common driver pins: 4
Segment driver pins: 32
1/3, 1/2 bias
1/4, 1/3, 1/2 duty
Applications
Remote control for air conditioner
Health care
Home appliances
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
P6.7
P6.6
P6.5
P6.4
P6.3
P6.2
P6.1
P6.0
P5.7/ IROUT
NC
45
44
43
42
41
40
39
38
37
36
P5.5/ INT1
SEG31/ P8.7
46
33
NC
47
NC
NC
48
P5.6/ TCC
NC
49
34
SEG30/ P8.6
50
35
SEG29/ P8.5
51
3. PIN ASSIGNMENTS
SEG28/ P8.4
52
32
P5.4/ INT0
SEG27/ P8.3
53
31
XOUT
SEG26/P8.2
54
30
XIN
SEG25/P8.1
55
29
VDD
SEG24/P8.0
56
28
OSCO
SEG23/P7.7
57
27
R-OSCI
SEG22/P7.6
58
SEG21/P7.5
59
SEG20/P7.4
SEG19/P7.3
EM78P468N
64 QFP
10
11
12
13
14
15
16
17
18
19
SEG 5
SEG 4
SEG 3
SEG 2
SEG 1
SEG 0
COM 3
COM 2
COM 1
9
SEG 6
8
SEG 7
COM 0
SEG 8
20
7
64
6
SEG16/ P7.0
SEG 9
VB
SEG 10
VA
21
5
22
63
SEG 11
62
SEG17/ P7.1
4
SEG18/ P7.2
3
VLCD 2
SEG 12
VLCD 3
23
SEG 13
24
61
2
60
1
/RESET
SEG 14
GND
25
SEG 15
26
Fig. 1 EM78P468N Pin Configuration for 64 Pin QFP Package
Table 1 Pin Description
PIN
PIN number
29
26
I/O type
I
I
R-OSCI
27
I
OSCO
28
O
Xin
30
I
Xout
31
O
/RESET
25
I
VDD
GND
Description
* Power supply pin
* System ground pin
* In crystal mode: crystal input
* In RC mode: resistor pull high.
* In PLL mode: connect 0.01μF capacitance to GND
* Must be pull high or low when high frequency is not use
* In crystal mode: crystal output
* In RC mode: instruction clock output
* Must be pull high or low when high frequency is not use.
*In crystal mode: Input pin for sub-oscillator. Connect to a
32.768KHz crystal
* RC mode: this pin is connected with a resistor to high level.
* In crystal: Connect to a 32.768KHz crystal
* In RC mode: instruction clock output
* Low active. If set as /RESET and remains at logic low, the
devices will be reset
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
PIN
PIN number
I/O type
P5.4/INT0
P5.5/INT1
32
33
I/O
P5.6/TCC
34
I/O
P5.7/IROUT
37
I/O
P6.0
~
P6.7
38~45
I/O
COM3~0
SEG0~SEG15
SEG16/P7.0
~
SEG23/P7.7
SEG24/P8.0
~
SEG30/P8.6
SEG31/P8.7
VB
VA
VLCD2
VLCD3
17~20
16~1
64
~
57
56
~
50
46
21
22
23
24
O
O
O/(I/O)
Description
* General purpose I/O pin. /external interrupt.
* INT0 interruption source can be set to falling or rising edge by
IOC81 register bit 7 (INT_EDGE).
* INT1 interruption source is a falling edge signal.
* All pins wake up from sleep mode when the pin status
changes.
* General purpose I/O/ external counter input
* This pin works in idle mode.
* General purpose I/O pin or IR mode output pin,
* Capable of sinking 20mA/5V.
* General purpose I/O pin.
* Pull-high/ pull-low/ Open drain function support.
* All pins can wake up from sleep and idle modes when the
pin status changes.
* LCD common output pin.
* LCD segment output pin.
* LCD segment output pin. Can be shared with general purpose
I/O pin
* LCD segment output pin. Can be shared with general I/O pin
* For general purpose I/O use, can wake up from sleep mode
O/(I/O)
and idle mode when the pin status changes.
* For general purpose I/O use, supports pull-low function.
* Connect capacitors for LCD bias voltage
* Connect capacitors for LCD bias voltage
I/O (Power) * One of LCD bias voltage
I/O (Power) * One of LCD bias voltage
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
4. FUNCTION DESCRIPTION
CPU
Data RAM
Timing Control
ROM
LCD driver
LCD
IO PORT
IO
Oscillator
PLL/Crystal/RC
IR/PWM
Xout
Xin
OSCO
R-OSCI
Timer/ Counter
Oscillator Timing
Control
ROM
WDT timer
STACK
Interruption
register
R1 (TCC)
General RAM
Control w ake-up
on I/O port
R2
Interruption
control
ALU
Instruction
decoder
R3
R4
ACC
Data & Control BUS
128 byte
Data RAM
LCD RAM
PORT5
IOC5
Common
driver
Segment
driver
PORT6
R
5
IOC6
PORT7
R
6
IOC9
PORT8
R
7
IOC9
R
8
Fig. 2 System Block Diagram
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
4.1 Operational Registers
1. R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is used as indirect addressing pointer. Any instructtion using R0 as register actually accesses the data pointed by the RAM Select Register (R4).
2. R1 (Time Clock /Counter)
Increases by an external signal edge applied to TCC, or by the instruction cycle clock.
Written and read by the program as any other register.
3. R2 (Program Counter)
* The structure is depicted in Fig. 3
* Generates 4K × 13 on-chip ROM addresses to the relative programming instruction codes.
* "JMP" instruction allows direct loading of the low 10 program counter bits.
* "CALL" instruction loads the low 10 bits of the PC and PC+1, then push it into the stack.
* "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of
stack.
* "MOV R2, A" allows the loading of an address from the A register to the PC. The contents of the
ninth and tenth bits do not change.
* "ADD R2, A" allows a relative address be added to the current PC. The contents of the ninth and
tenth bits do not change.
* The most significant bit (A10~A11) will be loaded with the content of bits PS0~PS1 in the Status
register (R3) upon execution of a "JMP'' or "CALL'' instruction.
R3
PC
00 PAGE0 0000~03FF
01 PAGE1 0400~07FF
10 PAGE2 0800~0BFF
A10
A9 A8
CALL
RET
RETL
RETI
A7
~
A0
STACK LEVEL 1
STACK LEVEL 2
STACK LEVEL 3
Reset v ector
000H
TCC ov erf low interrupt v ector
003H
Exteral INT0 pin interrupt v ector
006H
Exteral INT1 pin interrupt v ector
009H
Counter 1 underf low interrupt v ector
00CH
Counter 2 underf low interrupt v ector
00FH
high pulse width timer underf low interrupt v ector 012H
low pulse width timer underf low interrupt v ector 015H
STACK LEVEL 4
STACK LEVEL 5
Port 6,Port8 pin change wake-up interrupt v ector 018H
01BH
Low v oltage detector interrupt v ector
STACK LEVEL 6
STACK LEVEL 7
STACK LEVEL 8
User Memory Space
11 PAGE3 0C00~0FFF
A11
On-Chip Program memory
FFFH
Fig. 3 Program Counter Organization
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
ADDRESS
0 0 R0 (Indirect Addressing Register)
0 1 R1 (Time Clock Counter)
0 2 R2 (P rogram Counter)
0 3 R3 (Status Register)
0 4 R4 (RAM select register)
0 5 R5 (P ort5 & IOCP AGE )
0 6 R6 (P ort6)
0 7 R7 (P ort7)
0 8 R8 (P ort8)
0 9 R9 (LCD control register)
0 A RA (LCD address)
0 B RB (LCD data buffer)
0 C RC (LVD control & Counter enable)
0 D RD (system & P LL/Booster frequency )
0 E RE (IR & INT0/1,TCC control)
0 F RF (interrupt status register)
R5 bit 0 -> 0
control re giste r page 0
R5 bit 0 -> 1
control re giste r page 1
IOC50 (P ort5 I/O control & LCD segment)
IOC60 (P ort6 I/O control )
IOC61(Wake up & P 5.7 sink current)
IOC70 (P ort7 I/O control )
IOC71(TCC & INT0 control register)
IOC80 (P ort8 I/O control )
IOC81(WDT control register)
IOC90 (128 byte RAM addressl )
IOC91(Counter 1,2 control)
IOCA0 (128 byte RAM data bufferl)
IOCA1(high/low pulse width timer control)
IOCB0 (Counter 1 preset)
IOCB1(P ort 6 pull-high control)
IOCC0 (Counter 2 preset)
IOCC1(P ort 6 open drain control)
IOCD0 (High-pulse width timer preset)
IOCD1(P ort 8 pull-high control)
IOCE0 (Low-pulse width timer preset)
IOCE1(P ort 6 pull-down control)
IOCF0 (interrupt mask register)
IOCF1 (interrupt mask register)
10
|
1F
16 byte common register
LCD RAM 4*32 bits
20
|
3F
bank 0 ~ bank 3
32 byte common register
128 byte data RAM
Fig. 4 Data Memory Configuration
4. R3 (Status Register)
Bit 7
--
Bit 6
PS1
Bit 5
PS0
Bit 4
T
Bit 3
P
Bit 2
Z
Bit 1
DC
Bit 0
C
Bit 7: Not used
Bit 6, 5 (PS1, 0): Page select bits
PS1
0
0
1
1
PS0
0
1
0
1
Program memory page (Address)
Page 0
Page 1
Page 2
Page 3
User can use PAGE instruction to change page and maintains the program page. Otherwise, user
can use “far jump” (FJMP) or “far call” (FCALL) MACRO to program user's code. The program
page is maintained by EMC's complier. It changes the user's program by inserting instructions
within the program.
This specification is subject to change without prior notice.
9
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Bit 4 (T): Time-out bit. Set to 1 by the "SLEP" and "WDTC" commands or during power up and
reset to 0 by WDT timeout.
EVENT
WDT wake up from sleep mode
WDT time out (not sleep mode)
/RESET wake up from sleep
Power up
Low pulse on /RESET
T
0
0
1
1
X
P
0
1
0
1
X
REMARK
X: don't care
Bit 3 (P): Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a
"SLEP" command.
Bit 2 (Z): Zero flag
Bit 1 (DC): Auxiliary carry flag
Bit 0 (C): Carry flag
5. R4 (RAM Select Register)
Bits 7 ~ 6 determine which bank is activated among the 4 banks. See the configuration of the
data memory in Fig.4. Use BANK instruction to change bank.
Bits 5 ~ 0 are used to select up to 64 registers in the indirect addressing mode.
6. R5 (PORT5 and Program Page Select Register)
Bit 7
R57
Bit 6
R56
Bit 5
R55
Bit 4
R54
Bit 3
--
Bit 2
--
Bit 1
--
Bit 0
IOCPAGE
Bit 7~4: 4-bit I/O registers of PORT5
Bit 3~1: Not used
Bit 0 (IOCPAGE): change IOC8 ~ IOCF to another page, 0/1 => page0 / page1
7. R6 (PORT6)
Bit 7
R67
Bit 6
R66
Bit 5
R65
Bit 4
R64
Bit 3
R63
Bit 2
R62
Bit 1
R61
Bit 0
R60
Bit 4
R74
Bit 3
R73
Bit 2
R72
Bit 1
R71
Bit 0
R70
Bit 4
R84
Bit 3
R83
Bit 2
R82
Bit 1
R81
Bit 0
R80
Bit 7~0: PORT 6 8-bit I/O registers
8. R7 (PORT7)
Bit 7
R77
Bit 6
R76
Bit 5
R75
Bit 7~0: PORT 7 8-bit I/O registers
9. R8 (PORT8)
Bit 7
R87
Bit 6
R86
Bit 5
R85
Bit 7~0: PORT 8 8-bit I/O registers
This specification is subject to change without prior notice.
10
04.10.2004 (V1.0)
EM78P468N
OTP ROM
10. R9 (LCD Control Register)
Bit 7
BS
Bit 6
DS1
Bit 5
DS0
Bit 4
LCDEN
Bit 3
--
Bit 2
Bit 1
LCDTYPE LCDF1
Bit 0
LCDF0
Bit 7 (BS): LCD bias select bit, 0/1=>(1/2 bias) / (1/3 bias)
Bit 6,5 (DS1, 0): LCD duty select
DS1
0
0
1
DS0
0
1
X
LCD duty
1/2 duty
1/3 duty
1/4 duty
Bit 4 (LCDEN): LCD enable bit: 0/1 -> LCD circuit disable/enable. When LCD function is disabled,
all common/segment outputs are set to ground (GND) level.
Bit 3: Not used
Bit 2 (LCDTYPE): LCD drive waveform type select bit
0: A type waveform
1: B type waveform
Bit 1, 0(LCDF1, 0): LCD clock pre-scaler ratio control bit
LCDF1
LCDF0
0
0
1
1
0
1
0
1
LCD frame frequency (Fs=32.768KHz)
1/2 duty
1/3 duty
1/4 duty
Fs/(256*2)=64.0
Fs/(172*3)=63.5
Fs/(128*4) =64.0
Fs/(280*2)=58.5
Fs/(188*3)=58.0
Fs/(140*4) =58.5
Fs/(304*2)=53.9
Fs/(204*3)=53.5
Fs/(152*4) =53.9
Fs/(232*2)=70.6
Fs/(156*3)=70.0
Fs/(116*4) =70.6
Fs: sub-oscillator frequency
11. RA (LCD Address)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
LCD_A4
Bit 3
LCD_A3
Bit 2
LCD_A2
Bit 1
LCD_A1
Bit 0
LCD_A0
Bit 7 ~ 5: Not used, fixed to “0”
Bit 4~0 (LCDA4~0): LCD RAM address
RB (LCD data buffer)
RA
Segment
Bit 3
Bit 2
Bit 1
Bit 0
(LCD address) Bit 7 Bit 6 Bit 5 Bit 4
(LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
----00H
SEG0
01H
02H
|
1EH
1FH
Common
---
---
---
---
---X
---X
---X
---X
SEG1
SEG2
|
SEG29
SEG30
SEG31
|
This specification is subject to change without prior notice.
COM3
11
COM2
COM1
COM0
04.10.2004 (V1.0)
EM78P468N
OTP ROM
12. RB (LCD Data Buffer)
Bit 7
--
Bit 6
--
Bit 5
--
Bit 4
--
Bit 3
Bit 2
Bit 1
Bit 0
LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0
Bit 7 ~ 4: Not used
Bit 3~0 (LCD_D3~0): LCD RAM data transfer register
13. RC (LVD Control and Counter Enable Register)
Bit 7
LVDEN
Bit 6
/LV
Bit 5
LVDF
Bit 4
LVD0
Bit 3
Bit 2
Bit 1
Bit 0
LPWTEN HPWTEN CNT2EN CNT1EN
Bit 7(LVDEN): Enable low voltage detector.
1: enable LVD function.
0: disable LVD function.
Bit 6(/LV): Low voltage detector. This is a read only bit. When the VDD pin voltage is lower than
Vdet (selected by LVD0), this bit will be cleared.
0: the low voltage is detected.
1: the low voltage is not detected or LVD function is disabled.
Bit 5 (LVDF): interrupt flag of Low voltage detector.
Bit 4(LVD0): the low voltage detector select bits
LVD0
0
1
Vdet
2.1 V
2.3 V
LVD0=0: if Vdet voltage drops lower than 2.1V or rises higher than 2.3V, then interrupt occurs.
LVD0=1: if Vdet voltage drops lower than 2.3V or rises higher than 2.5V, then interrupt occur.
Bit 3(LPWTEN): low pulse width time enable bit, 0/1 => disable/enable
Bit 2(HPWTEN): high pulse width timer enable bit, 0/1 => disable/enable
Bit 1(CNT2EN): counter 2 enable bit, 0/1 => disable/enable
Bit 0(CNT1EN): counter 1 enable bit, 0/1 => disable/enable
14. RD (System Clock, Booster Frequency, and PLL Frequency Control
Registers)
Bit 7
--
Bit 6
CLK2
Bit 5
CLK1
Bit 4
CLK0
Bit 3
IDLE
Bit 2
BF1
Bit 1
BF0
Bit 0
CPUS
Bit 7: Not used
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
Bit 6~4 (CLK2~0): main clock select bit for PLL mode (code option select)
CLK2
0
0
0
0
1
CLK1
0
0
1
1
--
CLK0
0
1
0
1
--
Main clock
32.768K*130=4.26 MHz
32.768K*65=2.13 MHz
2.13MHz/2
2.13MHz/4
32.768K*244=8 MHz
Bit 3 (IDLE): idle mode enable bit. This bit will decide the intended mode of the SLEP instruction.
IDLE=”0”+SLEP instruction => sleep mode
IDLE=”1”+SLEP instruction => idle mode
Bit 2,1 (BF1, 0): LCD booster frequency select bit
BF1
0
0
1
1
BF0
0
1
0
1
Booster frequency
Fs
Fs/4
Fs/8
Fs/16
Bit 0 (CPUS): CPU oscillator source select, 0/1=> sub-oscillator (Fs)/ main oscillator (Fm)
When CPUS=0, the CPU oscillator select sub-oscillator and the main oscillator is stopped.
CPU Operation Mode
Code option
HLFS=1
Normal Mode
Code option
HLFS=0
fm:oscillation
fs: oscillation
it must delay a little times for the main
oscillation stable w hile your system timing
control is conscientious
RESET
CPU: using fosc
CPUS="0"
CPUS="1"
SLEEP Mode
IDLE="0"
SLEP
Fm:stop
Fs: stop
CPU: stop
Green Mode
IDLE="1"
SLEP
fm:stop
fs: oscillation
Wake up
CPU: using fs
The w ake up time from sleep to green mode is
approximately 18ms+16*1/fs
IDLE Mode
fm:stop
fs: oscillation
w ake up
CPU: stop
The w ake up time from idle to green
mode is 16*1/fs
Fig. 5 CPU Operation Mode
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
15. RE (IR Control and PORT5 Function Pins Set Register)
Bit 7
IRE
Bit 6
HF
Bit 5
LGP
Bit 4
--
Bit 3
IROUTE
Bit 2
TCCE
Bit 1
EINT1
Bit 0
EINT0
Bit 7 (IRE): Infrared Remote Enable bit
0: Disable IRE. Disable H/W Modulator Function. IROUT pin fixed to high level
1: Enable IRE. Enable H/W Modulator Function. Pin 6.7 defined as IROUT.
Bit 6 (HF): High frequency.
0: For PWM application, IROUT waveform is created according to high-pulse and low-pulse
width time as determined by the high pulse and low pulse width timers respectively.
1: For IR application mode, the low time sections of the generated pulse is modulated with
the frequency Fcarrier,
Bit 5 (LGP): long pulse.
0: the high-pulse timer register and low-pulse width timer is valid.
1: The high-pulse width timer register is ignored. So the IROUT waveform is dependent on
low-pulse width timer register only
Bit 4: Not used
Bit 3 (IROUTE): control bit is used to define the function of P5.7 (IROUT) pin.
0: P5.7, bi-directional I/O pin.
1: IROUT, in this case, the I/O control bit of P5.7 (bit 7 of IOC5) must be set to “0”
Bit 2 (TCCE): control bit is used to define the function of P5.6 (TCC) pin.
0: P5.6, bi-directional I/O pin.
1: TCC, external input pin of TCC. In this case, the I/O control bit of P5.6 (bit 6 of IOC5)
must be set to “1”
Bit 1 (EINT1): control bit is used to define the function of P5.5 (INT1) pin.
0: P5.5, bi-directional I/O pin.
1: INT1, external interrupt pin. In this case, the I/O control bit of P5.5 (bit 5 of IOC5) must be
set to “1”
Bit 0 (EINT0): control bit is used to define the function of P5.4 (INT0) pin.
0: P5.4, bi-directional I/O pin.
1: INT0, external interrupt pin. In this case, the I/O control bit of P5.4 (bit 4 of IOC5) must be
set to “1”
This specification is subject to change without prior notice.
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EM78P468N
OTP ROM
16. RF (Interrupt Status Register)
Bit 7
ICIF
Bit 6
LPWTF
Bit 5
HPWTF
Bit 4
CNT2F
Bit 3
CNT1F
Bit 2
INT1F
Bit 1
INT0F
Bit 0
TCIF
Bit 7 (ICIF): Port 6, Port 8, input status changed interrupt flag. Set when PORT6, PORT8 input
changes.
Bit 6 (LPWTF): interrupt flag of internal low-pulse width timer underflow.
Bit 5 (HPWTF): interrupt flag of internal high-pulse width timer underflow.
Bit 4 (CNT2): interrupt flag of internal counter 2 under-flow.
Bit 3 (CNT1): interrupt flag of internal counter 1 underflow.
Bit 2 (INT1F): external INT1 pin interrupt flag.
Bit 1 (INT0F): external INT0 pin interrupt flag.
Bit 0 (TCIF): TCC timer overflow interrupt flag. Set when TCC timer overflows.
17. R10~R3F (General Purpose Register)
R10~R31F and R20~R3F (Banks 0~3) are general purposes register.
4.2 Special Purpose Registers
1. A (Accumulator)
* Internal data transfer, or instruction operand holding
* This is not an addressable register.
2. IOC50 (PORT5 I/O Control and PORT7, 8 for LCD Segment Control Register)
Bit 7
IOC57
Bit 6
IOC56
Bit 5
IOC55
Bit 4
IOC54
Bit 3
P8HS
Bit 2
P8LS
Bit 1
P7HS
Bit 0
P7LS
Bit 7~4(IOC57~4): PORT5 I/O direction control register
0: set the relative I/O pins as output
1: set the relative I/O pin into high impedance (input pin)
Bit 3(P8HS): Switch to high nibble I/O of Port8 or to LCD segment output as share pins
SEGxx/P8.x pins
0: select high nibble of PORT8 as normal P8.4~P8.7
1: select LCD SEGMENT output as SEG28~SEG31 output
Bit 2(P8LS): Switch to low nibble I/O of Port8 or to LCD segment output as share pins
SEGxx/P8.x pins
0: select low nibble of PORT8 as normal P8.0~P8.3
1: select LCD SEGMENT output as SEG24~SEG27 output
This specification is subject to change without prior notice.
15
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Bit 1(P7HS): Switch to high nibble I/O of Port7 or to LCD segment output as share pins
SEGxx/P7.x pins
0: select high nibble of PORT7 as normal P7.4~P7.7
1: select LCD SEGMENT output as SEG20~SEG23 output
Bit 0(P7LS): Switch to low nibble I/O of PORT7 or to LCD segment output as share pins
SEGxx/P7.x pins
0: select low nibble of PORT7 as normal P7.0~P7.3
1: select LCD SEGMENT output as SEG16~SEG19 output
3. IOC60 (PORT6 I/O Control Register)
Bit 7
IOC67
Bit 6
IOC66
Bit 5
IOC65
Bit 4
IOC64
Bit 3
IOC63
Bit 2
IOC62
Bit 1
IOC61
Bit 0
IOC60
Bit 1
IOC71
Bit 0
IOC70
Bit 1
IOC81
Bit 0
IOC80
Bit 7 (IOC67)~Bit 0(IOC60): PORT6 I/O direction control register
0: set the relative I/O pins as output
1: set the relative I/O pin into high impedance (input pin)
4. IOC70 (PORT7 I/O Control Register)
Bit 7
IOC77
Bit 6
IOC76
Bit 5
IOC75
Bit 4
IOC74
Bit 3
IOC73
Bit 2
IOC72
Bit 7 (IOC77)~Bit 0(IOC70): PORT7 I/O direction control register
0: set the relative I/O pins as output
1: set the relative I/O pin into high impedance (input pin)
5. IOC80 (PORT8 I/O Control Register)
Bit 7
IOC87
Bit 6
IOC86
Bit 5
IOC85
Bit 4
IOC84
Bit 3
IOC83
Bit 2
IOC82
Bit 7 (IOC87)~Bit 0(IOC80): PORT8 I/O direction control register
0: set the relative I/O pins as output
1: set the relative I/O pin into high impedance (input pin)
6. IOC90 (128 Bytes RAM Address)
Bit 7
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
Bit 7: Not used, fixed at “0”
Bit 6~0: 128 bytes RAM address
This specification is subject to change without prior notice.
16
04.10.2004 (V1.0)
EM78P468N
OTP ROM
7. IOCA0 (128 Bytes RAM Data Buffer)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
Bit 7~0: 128 bytes RAM data transfer register
8. IOCB0 (Counter 1 Preset Register)
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Bit 7 ~ Bit 0: All are Counter 1 buffer that user can read and write. Counter 1 is an 8-bit
down-counter with 8-bit pre-scaler that is used as IOCB to preset the counter and read preset
value. After an interruption, it will auto reload the preset value.
9. IOCC0 (Counter 2 Preset Register)
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Bit 7 ~ Bit 0: All are Counter 2 buffer that user can read and write. The Counter 2 is an 8-bit
down-counter with 8-bit pre-scaler that is used as IOCC to preset the counter and read preset
value. After an interruption, it will reload the preset value.
When IR output is enabled, this control register can obtain carrier frequency output.
If the Counter 2 clock source is equal to FT–
Carrier frequency (Fcarrier) = FT/[2*(preset value+1)*prescaler]
10. IOCD0 (High-Pulse Width Timer Preset Register)
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Bit 7 ~ Bit 0: All are high-pulse width timer buffer that user can read and write. High-pulse width
timer preset register is an eight-bit down-counter with 8-bit pre-scaler that is used as IOCD to
preset the counter and read preset value. After an interruption, it will reload the preset value.
For PWM or IR application, this control register is set as high pulse width.
If the high-pulse width source clock is FT–
the high pulse width=prescaler*(high-pulse width preset value+1)/ FT
This specification is subject to change without prior notice.
17
04.10.2004 (V1.0)
EM78P468N
OTP ROM
11. IOCE0 (Low-Pulse Width Timer Preset Register)
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
Bit 7 ~ Bit 0: All are low-pulse width timer buffer that user can read and write. Low-pulse width
timer preset is an eight-bit down-counter with 8-bit pre-scaler that is used as IOCE to preset the
counter and read preset value. After an interruption, it will reload the preset value.
For PWM or IR application, this control register is set as low pulse width.
If the low-pulse width timer source clock is FT–
the low pulse width=prescaler*(preset value+1)/ FT
12. IOCF0 (Interrupt Mask Register)
Bit 7
ICIE
Bit 6
LPWTE
Bit 5
HPWTE
Bit 4
CNT2E
Bit 3
CNT1E
Bit 2
INT1E
Bit 1
INT0E
Bit 0
TCIE
Bit 3
/WUE8H
Bit 2
/WUE8L
Bit 1
/WUE6H
Bit 0
/WUE6L
Bit 7~Bit 0: interrupt enable bit.
0: disable interrupt
1: enable interrupt
IOCF0 register is readable and writable.
13. IOC61 (Wake Up Register)
Bit 7
IROCS
Bit 6
--
Bit 5
--
Bit 4
--
Bit 7: IROCS: IROUT/PORT5.7 output sink current set
IROCS
0
1
P5.7/IROUT Sink current
VDD=5V
VDD=3V
10 mA
7 mA
20 mA
14 mA
Bit 6,5,4: Not used
Bit 3 (/WUE8H): 0/1=> enable/disable P8.4~P8.7 pin change wake up function
Bit 2 (/WUE8L): 0/1=> enable/disable P8.0~P8.3 pin change wake up function
Bit 1 (/WUE8H): 0/1=> enable/disable P6.4~P6.7 pin change wake up function
Bit 0 (/WUE8L): 0/1=> enable/disable P6.0~P6.3 pin change wake up function
This specification is subject to change without prior notice.
18
04.10.2004 (V1.0)
EM78P468N
OTP ROM
14. IOC71 (TCC Control Register)
Bit 7
INT_EDGE
Bit 6
INT
Bit 5
TS
Bit 4
TE
Bit 3
PSRE
Bit 2
TCCP2
Bit 1
TCCP1
Bit 0
TCCP0
Bit 7 (INT_EDGE):
0: P5.4 's (INT0) interruption source is a rising edge signal.
1: P5.4 's (INT0) interruption source is a falling edge signal.
Bit 6 (INT): INT enable flag, this bit is read only
0: interrupt masked by DISI or hardware interrupt
1: interrupt enabled by ENI/RETI instructions
Bit 5 (TS): TCC signal source
0: internal instruction cycle clock
1: transition on TCC pin, TCC period > internal instruction clock period
Bit 4 (TE): TCC signal edge
0: increment by TCC pin rising edge
1: increment by TCC pin falling edge
Bit 3 (PSRE): Prescaler Register enable bit
0: TCC rate 1:1
1: as indicated in the table below:
Bit 2~0 (TCCP2~0): TCC pre-scaler bits.
TCCP2
0
0
0
0
1
1
1
1
TCCP1
0
0
1
1
0
0
1
1
TCCP0
0
1
0
1
0
1
0
1
TCC rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
15. IOC81 (WDT Control Register)
Bit 7
--
Bit 6
--
Bit 5
--
Bit 4
--
Bit 3
WDTE
Bit 2
WDTP2
Bit 1
WDTP1
Bit 0
WDTP0
Bit 7 ~ 4:Not used
Bit 3 (WDTE): watchdog timer enable. This control bit is used to enable the Watchdog timer,
0: Disable WDT function.
1: enable WDT function.
This specification is subject to change without prior notice.
19
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Bit 2~0 (WDTP2~0): watchdog timer pre-scaler bits. The WDT source clock is sub-oscillation
frequency.
WDTP2
0
0
0
0
1
1
1
1
WDTP1
0
0
1
1
0
0
1
1
WDTP0
0
1
0
1
0
1
0
1
WDT rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
16. IOC91 (Counter 1, 2 Control Register)
Bit 7
CNT2S
Bit 6
CNT2P2
Bit 5
CNT2P1
Bit 4
CNT2P0
Bit 3
CNT1S
Bit 2
CNT1P2
Bit 1
CNT1P1
Bit 0
CNT1P0
Bit 7(CNT2S): Counter 2 clock source select 0/1 => Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)
Bit 6~4(CNT2P2~0): Counter 2 prescaler select bits
CNT2P2
0
0
0
0
1
1
1
1
CNT2P1
0
0
1
1
0
0
1
1
CNT1P0
0
1
0
1
0
1
0
1
Counter 2 scale
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3(CNT1S): Counter 1 clock source select 0/1 => Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)
Bit 2~0 (CNT1P2~0): Counter 1 prescaler select bits
CNT1P2
0
0
0
0
1
1
1
1
CNT1P1
0
0
1
1
0
0
1
1
This specification is subject to change without prior notice.
CNT1P0
0
1
0
1
0
1
0
1
20
Counter 1 scale
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
04.10.2004 (V1.0)
EM78P468N
OTP ROM
17. IOCA1 (High-Pulse Width Timer, Low-Pulse Width Timer Control Register)
Bit 7
LPWTS
Bit 6
Bit 5
Bit 4
LPWTP2 LPWTP1 LPWTP0
Bit 3
Bit 2
Bit 1
Bit 0
HPWTS HPWTP2 HPWTP1 HPWTP0
Bit 7(LPWTS): low-pulse width timer clock source select 0/1 -> Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)
Bit 6~4 (LPWTP2~0): low-pulse width timer prescaler select bits
LPWTP2
0
0
0
0
1
1
1
1
LPWTP1
0
0
1
1
0
0
1
1
LPWTP0
0
1
0
1
0
1
0
1
Low--pulse width timer scale
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
Bit 3(HPWTS): high-pulse width timer clock source select 0/1 -> Fs/ Fm*
(*Fs: sub-oscillator clock, Fm: main-oscillator clock)
Bit 2~0(HPWTP2~0): high-pulse width timer prescaler select bits
HPWTP2
0
0
0
0
1
1
1
1
HPWTP1
0
0
1
1
0
0
1
1
HPWTP0
0
1
0
1
0
1
0
1
High-pulse width timer scale
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
18. IOCB1 (PORT 6 Pull High Control Register)
Bit 7
PH67
Bit 6
PH66
Bit 5
PH65
Bit 4
PH64
Bit 3
PH63
Bit 2
PH62
Bit 1
PH61
Bit 0
PH60
Bit 1
OP61
Bit 0
OP60
Bit 7 ~ Bit 0: The enable bits of Port 6 pull high function.
0: disable internal pull-high resistor function
1: enable internal pull-high resistor function
19. IOCC1 (PORT 6 Open Drain Control Register)
Bit 7
OP67
Bit 6
OP66
Bit 5
OP65
Bit 4
OP64
Bit 3
OP63
Bit 2
OP62
Bit 7 ~ Bit 0: The enable bits of Port 6 open drain function.
0: disable open drain function
1: enable open drain function
This specification is subject to change without prior notice.
21
04.10.2004 (V1.0)
EM78P468N
OTP ROM
20. IOCD1 (PORT 8 Pull High Control Register)
Bit 7
PH87
Bit 6
PH86
Bit 5
PH85
Bit 4
PH84
Bit 3
PH83
Bit 2
PH82
Bit 1
PH81
Bit 0
PH80
Bit 2
PL62
Bit 1
PL61
Bit 0
PL60
Bit 7 ~ Bit 0: The enable bits of Port 8 pull-high function.
0: disable internal pull-high resistor function
1: enable pull-high resistor function
21. IOCE1 (PORT 6 Pull-Down Control Register)
Bit 7
PL67
Bit 6
PL66
Bit 5
PL65
Bit 4
PL64
Bit 3
PL63
Bit 7 ~ Bit 0: The enable bits of port 6 pull low function.
0: disable internal pull-down resistor function
1: enable internal pull-down resistor function
22. IOCF1 (Interrupt Mask register)
Bit 7
--
Bit 6
--
Bit 5
--
Bit 4
--
Bit 3
--
Bit 2
--
Bit 1
--
Bit 0
LVDE
Bit 7~1: Not used
Bit 0: interrupt enable bit for low voltage detector function.
0: disable interrupt
1: enable interrupt
IOCF1 register is readable and writable.
4.3 TCC and WDT Pre-scaler
Two 8-bit counters are available as pre-scalers for the TCC (Time Clock Counter) and WDT (Watch
Dog Timer). The TCCP2~TCCP0 bits of the IOC71 register are used to determine the ratio of the
TCC pre-scaler. Likewise, the WDTP2~WDTP0 bits of the IOC81 register are used to determine the
WDT pre-scaler. The TCC pre-scaler (TCCP2~TCCP0) is cleared by the instructions each time they
are written into TCC, while the WDT pre-scaler is cleared by the “WDTC” and “SLEP” instructions.
Fig.7 depicts the circuit diagram of TCC and WDT.
R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be selected by internal instruction
clock or external signal input (edge selectable from the TCC control register). If TCC signal source is
from internal instruction clock, TCC will increase by 1 at every instruction cycle (without pre-scaler).
If TCC signal source is from external clock input, TCC will increase by 1 at every falling edge or
rising edge of the TCC pin.
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after
the oscillator driver has been turned off. During Normal mode, Green mode, or Idle mode operation,
a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at
any time during the Normal mode and Green mode by software programming. Refer to WDTE bit of
IOC81 register. With no pre-scaler, the WDT time-out period is equal to (prescaler*256/ Fs)
Data Bus
Instruction Clock
TCC
Pin
TCC (R1)
MUX
Prescaler
PSRE TCCP2~0
(IOC71)(IOC71)
TE (IOC71)
8 to 1 MUX
TCC overflow interrupt
TS (IOC71)
Fig. 7(a) Block Diagram of TCC
WDT
8 bit counter
WDTE (IOC81)
8 to 1 MUX
Prescaler
Fs
(Sub oscillator)
WDTP2~0
(IOC81)
WDT Time out
Fig. 7(b) Block Diagram of WDT
This specification is subject to change without prior notice.
23
04.10.2004 (V1.0)
EM78P468N
OTP ROM
4.4 I/O Ports
The I/O registers, (Port 5, Port 6, Port 7, and Port 8), are bi-directional tri-state I/O ports. Port 6 and
Port 8 are pulled-high internally by software; Port 6 is also pulled-low internally by software.
Furthermore, Port 6 has its open-drain output also through software. Port 6 and Port 8 features an
input status changed interrupt (or wake-up) function and is pulled-high by software. Each I/O pin can
be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC8). The I/O registers and
I/O control registers are both readable and writable. The I/O interface circuits are shown in Fig. 8
NOTE: Open-drain, pull high, and pull down are not shown in the figure.
Fig. 8 The Circuit of I/O Port and I/O Control Register for Port 5, Port 6, Port 7and Port 8
4.5 RESET and Wake-up
A RESET can be activated by
Power on reset
WDT timeout. (if enabled)
/RESET pin pull low
Note: The power on reset circuit is always enabled. It will reset CPU at about 1.9V and consumed
about 0.5uA.
Once RESET occurs, the following functions are performed
The oscillator is running, or will be started.
The Program Counter (R2) is set to all "0".
All I/O port pins are configured as input mode (high-impedance state).
The TCC/Watchdog timer and pre-scaler are cleared.
When power on, the Bit 6 of R3 and the upper 2 bits of R4 are cleared.
Bits of the IOC71 register are set to all "1" except for Bit 6 (INT flag).
For other registers, see Table 2 below.
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)
EM78P468N
OTP ROM
Table 2 Summary of the Initialized Values for Registers
Address
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Name
IOC50
IOC60
IOC70
IOC80
IOC90
IOCA0
IOCB0
IOCC0
IOCD0
IOCE0
IOCF0
IOC61
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
IOC57
1
1
IOC56
1
1
IOC55
1
1
IOC54
1
1
P8HS
0
0
P8LS
0
0
P7HS
0
0
P7LS
0
0
P
P
P
P
P
P
P
P
IOC67
1
1
IOC66
1
1
IOC65
1
1
IOC64
1
1
IOC63
1
1
IOC62
1
1
IOC61
1
1
IOC60
1
1
P
P
P
P
P
P
P
P
IOC77
1
1
IOC76
1
1
IOC75
1
1
IOC74
1
1
IOC73
1
1
IOC72
1
1
IOC71
1
1
IOC70
1
1
P
P
P
P
P
P
P
P
IOC87
1
1
IOC86
1
1
IOC85
1
1
IOC84
1
1
IOC83
1
1
IOC82
1
1
IOC81
1
1
IOC80
1
1
P
P
P
P
P
P
P
P
X
0
0
P
RAM_D7
0
0
RAM_A6 RAM_A5 RAM_A4 RAM_A3 RAM_A2 RAM_A1 RAM_A0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
P
P
P
P
P
P
P
P
ICIE
0
0
LPWTE
0
0
HPWTE
0
0
CNT2E
0
0
CNT1E
0
0
INT1E
0
0
INT0E
0
0
TCIE
0
0
P
P
P
P
P
P
P
P
IROCS
0
0
X
U
U
X
U
U
X
U
U
P
U
U
U
This specification is subject to change without prior notice.
25
/WUE8H /WUE8L /WUE6H /WUE6L
0
0
0
0
0
0
0
0
P
P
P
P
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Address
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x00
0x01
0x02
Name
IOC71
IOC81
IOC91
IOCA1
IOCB1
IOCC1
IOCD1
IOCE1
IOCF1
R0(IAR)
R1(TCC)
R2(PC)
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
INT_EDGE
1
1
INT
0
0
TS
1
1
TE
1
1
PSRE
1
1
TCCP2
1
1
TCCP1
1
1
TCCP0
1
1
P
P
P
P
P
P
P
P
X
U
U
X
U
U
X
U
U
X
U
U
WDTE
0
0
WDTP2
1
1
WDTP1
1
1
WDTP0
1
1
U
U
U
P
P
P
U
CNT2S
0
0
P
LPWTS
0
0
CNT2P2 CNT2P1 CNT2P0
0
0
0
0
0
0
P
P
P
P
CNT1S
0
0
P
CNT1P2 CNT1P1 CNT1P0
0
0
0
0
0
0
P
P
P
LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
P
P
P
P
PH67
0
0
PH66
0
0
PH65
0
0
PH64
0
0
PH63
0
0
PH62
0
0
PH61
0
0
PH60
0
0
P
P
P
P
P
P
P
P
OP67
0
0
OP66
0
0
OP65
0
0
OP64
0
0
OP63
0
0
OP62
0
0
OP61
0
0
OP60
0
0
P
P
P
P
P
P
P
P
PH87
0
0
PH86
0
0
PH85
0
0
PH84
0
0
PH83
0
0
PH82
0
0
PH81
0
0
PH80
0
0
P
P
P
P
P
P
P
P
PL67
0
0
PL66
0
0
PL65
0
0
PL64
0
0
PL63
0
0
PL62
0
0
PL61
0
0
PL60
0
0
P
P
P
P
P
P
P
P
X
U
U
X
U
U
X
U
U
X
U
U
X
U
U
X
U
U
X
U
U
LVDE
0
0
U
U
U
U
U
U
U
P
Bit 7
U
P
Bit 6
U
P
Bit 5
U
P
Bit 4
U
P
Bit 3
U
P
Bit 2
U
P
Bit 1
U
P
Bit 0
U
P
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
P
P
P
P
P
P
P
P
Bit 7
0
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
0
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
0
This specification is subject to change without prior notice.
Jump to address 0x0018 or continue to execute next instruction
26
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Address
0x03
0x04
0x05
0x06
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
Name
R3(SR)
R4(RSR)
R5
R6
R7
R8
R9
RA
RB
RC
RD
RE
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
X
U
U
PS1
0
0
PS0
0
0
T
1
t
P
1
t
Z
U
P
DC
U
P
C
U
P
U
P
P
t
t
P
P
P
Bank1
0
0
Bank0
0
0
-U
P
-U
P
-U
P
-U
P
-U
P
-U
P
P
P
P
P
P
P
P
P
R57
1
1
R56
1
1
R55
1
1
R54
1
1
X
U
U
X
U
U
X
U
U
IOCPAGE
P
P
P
P
U
U
U
P
R67
1
1
R66
1
1
R65
1
1
R64
1
1
R63
1
1
R62
1
1
R61
1
1
R60
1
1
P
P
P
P
P
P
P
P
R77
1
1
R76
1
1
R75
1
1
R74
1
1
R73
1
1
R62
1
1
R71
1
1
R70
1
1
P
P
P
P
P
P
P
P
R87
1
1
R86
1
1
R85
1
1
R84
1
1
R83
1
1
R82
1
1
R81
1
1
R80
1
1
P
P
P
P
P
P
P
P
BS
1
1
DS1
1
1
DS0
0
0
LCDEN
0
0
X
U
U
LCDTYPE
0
0
LCDF1
0
0
LCDF0
0
0
P
P
P
P
U
P
P
P
X
0
0
X
0
0
X
0
0
P
P
P
P
X
U
U
X
U
U
X
U
U
X
U
U
U
U
U
U
LVDEN
0
0
/LV
1
1
LVDF
0
0
LVD
0
0
P
P
0
P
P
P
P
P
X
U
U
CLK2
0
0
CLK1
0
0
CLK0
0
0
IDLE
1
1
BF1
0
0
BF0
0
0
CPUS
*1
*1
U
P
P
P
P
P
P
P
IRE
0
0
HF
0
0
LGP
0
0
X
U
U
IROUTE
0
0
TCCE
0
0
EINT1
0
0
EINT0
0
0
P
P
P
U
P
P
P
P
This specification is subject to change without prior notice.
27
0
0
LCD_A4 LCD_A3 LCD_A2 LCD_A1 LCD_A0
0
0
0
0
0
0
0
0
0
0
P
P
P
P
LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0
0
0
0
0
0
0
0
0
P
P
P
P
LPWTEN HPWTEN CNT2EN CNT1EN
0
0
0
0
0
0
0
0
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Address
0xF
0x10~0x3F
Name
RF
(ISR)
R10~R3F
Reset Type
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
Bit Name
Power-On
/RESET and WDT
Wake-Up from Pin
Change
ICIF
0
0
LPWTF
0
0
HPWTF
0
0
CNT2F
0
0
CNT1F
0
0
INT1F
0
0
INT0F
0
0
TCIF
0
0
N
P
P
P
P
P
P
P
Bit 7
U
U
Bit 6
U
U
Bit 5
U
U
Bit 4
U
U
Bit 3
U
U
Bit 2
U
U
Bit 1
U
U
Bit 0
U
U
P
P
P
P
P
P
P
P
X: not used. U: unknown or don’t care.
t : check R3 register explain.
P: previous value before reset.
N: Monitors interrupt operation status;
–: Not defined
1=running; P=not running
Note 1: This bit is equal to code option HLFS bit data
The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows:
Wakeup signal
TCC time out
IOCF bit0=1
INT0 pin
IOCF bit1=1
INT1 pin
IOCF bit2=1
Counter 1
IOCF bit3=1
Counter 2
IOCF bit4=1
High-pulse timer
IOCF bit5=1
Low-pulse timer
IOCF bit6=1
Port6, Port 8
(input status
change wake-up)
WDT time out
Sleep mode
Idle mode
*2
Wake-up
X
+ interrupt
+ next instruction
Wake-up
Wake-up
+ interrupt
+ interrupt
+ next instruction + next instruction
Wake-up
Wake-up
+ interrupt
+ interrupt
+ next instruction + next instruction
Wake-up
+ interrupt
X
+ next instruction
Wake-up
X
+ interrupt
+ next instruction
Wake-up
X
+ interrupt
+ next instruction
Wake-up
X
+ interrupt
+ next instruction
IOCF bit7=0
IOCF bit7=0
Wake-up
Wake-up
+ next instruction + next instruction
IOCF bit7=1+ENI
instruction
Wake-up
+ interrupt
+ next instruction
X
IOCF bit7=1+ENI
instruction
Wake-up
+ interrupt
+ next instruction
RESET
Green mode
Normal mode
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
X
X
RESET
RESET
Note 2: Only external TCC pin can Wake-up from idle mode.
This specification is subject to change without prior notice.
28
04.10.2004 (V1.0)
EM78P468N
OTP ROM
4.6 Oscillator
4.6.1. Oscillator Modes
The EM78P468N can operate in the three different oscillator modes from main oscillator (R-OSCI,
OSCO), such as RC oscillator with external resistor and Internal capacitor mode (IC); crystal
oscillator mode; and PLL operation mode. User can select one of them by programming FMMD1 and
FMMD0 in the CODE options register. The sub-oscillator can be operated in crystal mode and ERIC
mode. Table3 below shows how these three modes are defined.
Table 3 Oscillator Modes as defined by FSMD, FMMD1, FMMD0.
FSMD
0
0
0
1
1
1
FMMD1
0
0
1
0
0
1
FMMD0
0
1
X
0
1
X
Main clock
RC type (ERIC)
Crystal type
PLL type
RC type (ERIC)
Crystal type
PLL type
Sub-clock
RC type (ERIC)
RC type (ERIC)
RC type (ERIC)
Crystal type
Crystal type
Crystal type
Table 4 Summary of maximum operating speeds
Conditions
Two clocks
VDD
2.3
3.0
5.0
Fxt max.(MHz)
4
8
10
4.6.2. Crystal Oscillator/Ceramic Resonators (XTAL)
EM78P468N can be driven by an external clock signal through the R-OSCI pin as shown in Fig.9
below.
In most applications, the R-OSCI pin and the OSCO pin can be connected with a crystal or ceramic
resonator to generate oscillation. Fig. 10 depicts such circuit. Table 5 provides the recommended
values of C1 and C2. Since each resonator has its own attribute, user should refer to its specification
for appropriate values of C1 and C2. RS, a serial resistor, may be necessary for AT strip cut crystal
or low frequency mode.
R-OSCI
EM78P468N
OSCO
Fig.9 Circuit for External Clock Input
This specification is subject to change without prior notice.
29
04.10.2004 (V1.0)
EM78P468N
OTP ROM
C1
C1
R-OSCI
EM78P468N
Xin
XTAL
EM78P468N
OSCO
Rs
XTAL
Xout
C2
Rs
C2
Fig. 10 Circuit for Crystal/Resonator
Table 5 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonators
Oscillator
source
Oscillator Type
Frequency
455 kHz
2.0 MHz
4.0 MHz
455KHz
1.0MHz
2.0MHz
4.0MHz
32.768kHz
Ceramic Resonators
Main oscillator
Crystal Oscillator
Sub-oscillator
Crystal Oscillator
C1 (pF)
100~150
20~40
10~30
20~40
15~30
15
15
25
C2(pF)
100~150
20~40
10~30
20~150
15~30
15
15
25
4.6.3. RC Oscillator Mode with Internal Capacitor
If both precision and cost are taken into consideration, EM78P468N also offers a special
oscillation mode, which is equipped with an internal capacitor and an external resistor connected
to VDD. The internal capacitor functions as temperature compensator. In order to obtain more
accurate frequency, a precise resistor is recommended.
VDD
Rext
R-OSCI
or Xin
EM78P468N
Fig. 11 Circuit for Internal C Oscillator Mode
Table 6 RC Oscillator Frequencies
Pin
R-OSCI
Xin
Rext
Average Fosc 5V, 25°C Average Fosc 3V, 25°C
51k
100k
300k
2.2M
2.2221 MHz
1.1345 MHz
381.36KHz
32.768KHz
2.1972 MHz
1.1203 MHz
374.77 KHz
32.768KHz
Note: Measured from QFP packages with frequency drift of about ±30%.
Values provided are for design reference only
This specification is subject to change without prior notice.
30
04.10.2004 (V1.0)
EM78P468N
OTP ROM
4.7 Power-on Considerations
Any microcontroller (as with i EM78P468N ) s not warranted to start operating properly before the
power supply stabilizes in steady state. The EM78P468N is equipped with Power On Reset (POR)
with detection level range of 1.9V to 2.1V. The circuitry eliminates the extra external reset circuit but
will work well only if the VDD rises quickly enough (50 ms or less). However, under critical
applications, extra devices are still required to assist in solving power-on problems.
4.7.1. External Power-on Reset Circuit
This circuit implements an external RC to produce a reset pulse (see Fig.12). The pulse width (time
constant) should be kept long enough to allow VDD to reach minimum operation voltage. This circuit
is used when the power supply rise time is slow. Because the current leakage from the /RESET pin
is about ±5µA, it is recommended that R should not be great than 40K. In this way, the voltage at Pin
/RESET is held below 0.2V. The diode (D) acts as a short circuit at power-down. The capacitor, C, is
discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD
(electrostatic discharge) from flowing into Pin /RESET.
Fig. 12 External Power on Reset Circuit
7.7.2. Residue-Voltage Protection
When battery is replaced, device power (VDD) is disconnected but residue-voltage remains. The
residue-voltage may trips below minimum VDD, but above zero. This condition may cause poor
power on reset. Fig.13 and Fig.14 show how to build a residue-voltage protection circuit
Fig. 13 Circuit 1 for the Residue Voltage Protection
This specification is subject to change without prior notice.
31
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Fig. 14 Circuit 2 for the Residue Voltage Protection
4.8 Interrupt
The EM78P468N has nine interrupt sources as listed below:
TCC overflow interrupt.
External interrupt P5.4/INTO pin
External interrupt P5.5/INT1 pin
Counter 1 underflow interrupt
Counter 2 underflow interrupt
High-pulse width timer underflow interrupt
Low-pulse width timer underflow interrupt
Port 6, Port 8 input status change wake-up
Low voltage detector
This IC has internal interrupts which are falling edge triggered or as follows:
TCC timer overflow interrupt,
Four 8-bits down counter/timer underflow interrupt
VDD level down to less than LVD setting level
If these interrupt sources change signal from high to low, the RF register will generate “1” flag to
corresponding register if the IOCF0 or IOCF1 register is enabled.
RF is the interrupt status register. It records the interrupt request in flag bit. IOCF is the interrupt
mask register. Global interrupt is enabled by ENI instruction and disabled by DISI instruction. When
one of the interrupts (when enabled) is generated, it will cause the next instruction to be fetch from
address 0003H~001BH according to interrupt source.
This specification is subject to change without prior notice.
32
04.10.2004 (V1.0)
EM78P468N
OTP ROM
With EM78P468N, each individual interrupt source has its own interrupt vector as depicted in Table 3.
Before the interrupt subroutine is executed, the contents of ACC and the R3 register are initially
saved by hardware. After the interrupt service routine is completed, ACC and R3 are restored. The
existing interrupt service routine does not allow other interrupt service routine to be executed. So if
other interrupts occur while the existing interrupt service routine is being executed, the hardware will
save the later interrupts. Only after the existing interrupt service routine is completed that the next
interrupt service routine is executed.
Interrupt Occur
ACC
Interrupt Source
STACKACC
ENI/ DISI
R3
RETI
STACKR3
Fig. 15. Interrupt Backup Diagram
Table 3 Interrupt Vector
Interrupt Vector
0003H
0006H
0009H
000CH
000FH
0012H
0015H
0018H
001BH
Interrupt Status
TCC overflow interrupt.
External interrupt P5.4/INT0 pin
External interrupt P5.5/INT1 pin
Counter 1 underflow interrupt
Counter 2 underflow interrupt
High-pulse width timer underflow interrupt
Low-pulse width timer underflow interrupt
Port 6, Port 8 input status change wake-up
Low voltage detector
4.9 LCD Driver
The EM78P468N can drive LCD of up to 32 segments and 4 commons that can drive a total of 4*32
dots. LCD block is made up of LCD driver, display RAM, segment output pins, common output pins,
and LCD operating power supply pins. This circuit works on normal mode, green mode, and idle
mode. The LCD duty, bias, the number of segment, the number of common, and frame frequency
are determined by the LCD controller register.
The basic structure contains a timing control that uses a subsystem clock to generate the proper
timing for different duty and display accesses. The R9 register is a command register for LCD driver
which includes LCD enable/disable, bias (1/2 and 1/3), duty (1/2, 1/3, 1/4), and LCD frame frequency
control. The register RA is an LCD contrast and LCD RAM address control register. The register RB
is an LCD RAM data buffer. LCD booster circuit can change operation frequency to improve VLCD2
and VLCD3 drive capability. The control register is explained as follows.
This specification is subject to change without prior notice.
33
04.10.2004 (V1.0)
EM78P468N
OTP ROM
R9 (LCD Control Register)
Bit 7
BS
Bit 6
DS1
Bit 5
DS0
Bit 4
LCDEN
Bit 3
--
Bit 2
Bit 1
LCDTYPE LCDF1
Bit 0
LCDF0
Bit 7 (BS): LCD bias select bit, 0/1=>(1/2 bias) / (1/3 bias)
Bit 6, 5 (DS1, 0): LCD duty select
DS1
0
0
1
DS0
0
1
X
LCD Duty
1/2 duty
1/3 duty
1/4 duty
Bit 4 (LCDEN): LCD enable bit: 0/1 -> LCD circuit disable/enable
When LCD function is disabled, all common/segment output is set to ground (GND) level
Bit 3: Not used
Bit 2 (LCDTYPE): LCD drive waveform type select bit
0: “A” type waveform
1: “B” type waveform
Bit 1, 0(LCDF1, 0): LCD clock pre-scaler ratio control bits
LCDF1
LCDF0
0
0
1
1
0
1
0
1
LCD frame frequency (Fs=32.768KHz)
1/2 duty
1/3 duty
1/4 duty
Fs/(256*2)=64.0
Fs/(172*3)=63.5
Fs/(128*4) =64.0
Fs/(280*2)=58.5
Fs/(188*3)=58.0
Fs/(140*4) =58.5
Fs/(304*2)=53.9
Fs/(204*3)=53.5
Fs/(152*4) =53.9
Fs/(232*2)=70.6
Fs/(156*3)=70.0
Fs/(116*4) =70.6
Fs: sub-oscillator frequency
RA (LCD Address)
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
LCD_A4
Bit 3
LCD_A3
Bit 2
LCD_A2
Bit 1
LCD_A1
Bit 0
LCD_A0
Bit 7 ~ 5: Not used, fixed to “0”
Bit 4~0 (LCDA4~0): LCD RAM address
RB (LCD Data Buffer)
RA
Segment
Bit 3
Bit 2
Bit 1
Bit 0
(LCD Address) Bit 7 Bit 6 Bit 5 Bit 4
(LCD_D3) (LCD_D2) (LCD_D1) (LCD_D0)
----00H
SEG0
01H
02H
|
1EH
1FH
Common
---
---
---
---
---X
---X
---X
---X
SEG1
SEG2
|
SEG29
SEG30
SEG31
|
This specification is subject to change without prior notice.
COM3
34
COM2
COM1
COM0
04.10.2004 (V1.0)
EM78P468N
OTP ROM
RB (LCD Data Buffer)
Bit 7
--
Bit 6
--
Bit 5
--
Bit 4
--
Bit 3
Bit 2
Bit 1
Bit 0
LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0
Bit 7 ~ 4: Not used
Bit 3~0 (LCD_D3~0): LCD RAM data transfer registers
RD (System Clock, Booster Frequency and PLL Frequency Control Register)
Bit 7
--
Bit 6
CLK2
Bit 5
CLK1
Bit 4
CLK0
Bit 3
IDLE
Bit 2
BF1
Bit 1
BF0
Bit 0
CPUS
Bit 2, 1 (BF1, 0): LCD booster frequency select bits
BF1
0
0
1
1
BF0
0
1
0
1
Booster frequency
Fs
Fs/4
Fs/8
Fs/16
The initial setting flowchart for LCD function
IC RESET occur
*Set Port 7 snd Port 8 for general I/O or LCD segment ( IOC50 )
*it must be set to output port when the pin of port 7 and the pin of port 8 for
LCD segemnt (IOC70 and IOC80 )
Set LCD Type, duty, bias, LCD frame frequency ( R9 )
Set LCD Booster Frequency ( RD)
Clear all LCD RAM (RA and RB )
Enable LCD function (R9 )
Use LCD address and LCD data buffer to implment user's applications.
(RA and RB )
END
Fig.16. The Initial Setting Flowchart for LCD Function
This specification is subject to change without prior notice.
35
04.10.2004 (V1.0)
EM78P468N
OTP ROM
The connecting of boosting circuits for LCD voltage is as below:
1/3 Bias
VA
VB
VDD(3V)
VDD(4.5V)
VLCD2(2V)
VLCD2(3V)
VA
VLCD3(1V)
GND
VB
VLCD3(1.5V)
GND
1/2 Bias
VDD(3V)
VDD(4.5V)
VLCD2(1.5V)
VA
VB
VLCD2(2.2.5V)
VA
VLCD3(1.5V)
GND
VB
VLCD3(2.25V)
GND
Fig. 17 The Connection of Charge Bump Circuit
This specification is subject to change without prior notice.
36
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Fig. 18 LCD Waveform for 1/2 Bias, 1/2 Duty
Fig. 19 LCD Waveform for 1/2 Bias, 1/3 Duty
This specification is subject to change without prior notice.
37
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Fig. 20 LCD Waveform for 1/3 Bias, 1/3 Duty
Fig. 21 LCD Waveform for 1/3 Bias, 1/4 Duty
This specification is subject to change without prior notice.
38
04.10.2004 (V1.0)
EM78P468N
OTP ROM
4.10 Infrared Remote Control Application / PWM Waveform Generate
This LSI can output infrared carrier in a friendly manner or in PWM standard waveform. The IR and
PWM waveform generated functions include an 8-bit down count timer/counter, high-pulse width
timer, low-pulse width timer, and IR control register. The IR system block diagram is show in Fig.21,
The IROUT pin waveform is determined by IR control register (RE), IOC90 (Counter 1, 2 control
register), IOCA0 (high-pulse width timer, low-pulse width timer control register), IOCC0 (Counter 2
preset), IOCD0 (high-pulse width timer preset register), and IOCE0 (low-pulse width timer preset
register). Details on Fcarrier, high-pulse time, and low pulse time are explained as follows:
If Counter 2 source clock is FT (this clock source can set by IOC91);
Fcarrier= FT/(2* [1+decimal counter 2 preset value (IOCC0)*prescaler])
If high-pulse width timer source clock is FT (this clock source can set by IOCA1);
High-pulse time= prescaler*[1+decimal high-pulse width timer value (IOCD0)]/ FT
If low-pulse width timer source clock is FT (this clock source can set by IOCA1);
Low-pulse time= prescaler*[1+decimal low-pulse width timer value (IOCE0)]/ FT
This specification is subject to change without prior notice.
39
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Fs
Fm
Pre-scaler
Auto-reload buffer
Auto-reload buffer
8
8
Pre-scaler
Pre-scaler
8 bit binary dow n counter
(high-pulse w idth timer)
Fcarrier
8 bit binary dow n counter
(low -pulse w idth timer)
8
8 bit binary
down counter
(counter 2)
8
H/W Modulator
8
Auto-reload
buffer
HF
LGP
IRE
IROUT pin
Fm: Internal instruction cycle clock; Fs: sub-oscillator frequency
Fig. 21 IR/PWM System Block Diagram
The IROUT output waveform is further explained in the following figures:
Fig. 22 LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in low-pulse
width time.
Fig. 23 LGP=0, HF=0, the IROUT waveform cannot modulate Fcarrier waveform when in low-pulse
width time. So IROUT waveform is determined by high-pulse time and low-pulse time. This
mode can produce standard PWM waveform
Fig. 24 LGP=0, HF=1, the IROUT waveform can modulate Fcarrier waveform when in low-pulse
width time. When IRE goes from high to low, the output waveform of IROUT will keep on
transmitting till high-pulse width timer interrupt occurs.
Fig. 25 LGP=0, HF=0, the IROUT waveform can not modulate Fcarrier waveform when in low-pulse
width time. So IROUT waveform is determined by high-pulse time and low-pulse time. This
mode can produce standard PWM waveform. When IRE goes from high to low, the output
waveform of IROUT will keep on transmitting till high-pulse width timer interrupt occurs.
Fig.26 LGP=1, when this bit is set to high level, the high-pulse width timer is ignored. So IROUT
waveform output from low-pulse width timer is established.
This specification is subject to change without prior notice.
40
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Fcarrier
low-pulse width
high-pulse width
high-pulse width
low-pulse width
HF
start
IRE
IROUT
Fig. 22 LGP=0, IROUT Pin Output Waveform
Fcarrier
low-pulse width
high-pulse width
high-pulse width
low-pulse width
HF
start
IRE
IROUT
Fig. 23 LGP=0, IROUT Pin Output Waveform
Fcarrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
HF
start
IRE
IR disable
IROUT
Always high-level
Fig. 24 LGP=0, IROUT Pin Output Waveform
This specification is subject to change without prior notice.
41
04.10.2004 (V1.0)
EM78P468N
OTP ROM
Fcarrier
low-pulse width
high-pulse width
low-pulse width
high-pulse width
HF
start
IRE
IR disable
IROUT
Always high-level
Fig. 25 LGP=0, IROUT Pin Output Waveform
Fcarrier
low-pulse width
Low-pulse width
high-pulse width
low-pulse width
HF
start
IRE
IR disable
IROUT
Always high-level
Fig. 26 LGP=1, IROUT Pin Output Waveform
This specification is subject to change without prior notice.
42
04.10.2004 (V1.0)
EM78P468N
OTP ROM
IR/PWM function enable flowchart
STRAT
STRAT
SET P5.7 to OUTPUT state (IOC 50)
SET P5.7 to OUTPUT state (IOC 50)
SET P5.7 for IR/PW M Function
Output Pin (RE)
SET P5.7 for IR/PWM Function
Output Pin (RE)
SET Counter 2 clock source and
prescaler (IOC91)
SET High pulse width timer, Low
pulse width timer source clock and
prescaler (IOCA1)
SET High pulse width tim er, Low
pulse width tim er source clock and
prescaler (IOCA1)
High pulse width timer (IOD0), Low
pulse width timer (IOCE0)preset
value
SET Counter 2 (IOC0), High pulse
width tim er (IOD0), Low pulse width
tim er (IOCE0)preset value
Enable IR (RE)
HF="0", and IRE="1"
Enable IR (RE)
HF="1", and IRE="1"
Enable HPWT and LPWT Interrupt
Set IOCF0 and ENI instruction
Enable HPW T and LPW T Interrupt
Set IOCF0 and ENI instruction
Enable high pulse width timer and
Low pulde width timer (RC)
Enable counter 2, high pulse width
tim er and Low pulde width tim er (RC)
END
END
(a) IR application
(b) PWM application
Fig. 27 IR/PWM Function Enable Flowchart
This specification is subject to change without prior notice.
43
04.10.2004 (V1.0)
EM78P468N
OTP ROM
4.11 Code Options
The EM78P468N has one CODE option word that is not a part of the normal program memory. The
option bits cannot be accessed during normal program execution.
Code Option Register and Customer ID Register arrangement distribution:
Word1 of code options is for customer ID code application.
Word 1
Bit12~Bit 0
Word0 of Code Options is for IC function setting. The following are the settings for OTP IC
programming:
Bit12~10 Bit9
1
CYES
Word 0
Bit8
Bit7
Bit6
Bit5
Bit4
HLFS ENWDTB FSMD FMMD1 FMMD0
Bit3
HLP
Bit2
PR2
Bit1
PR1
Bit0
PR0
• Bit 12 ~ 10: Not used.
These bits are set to “1” all the time.
• Bit 9 (CYES): Cycle select for JMP and CALL instructions
0: only one instruction cycle (JMP or CALL) can be executed
1: two instructions cycles (JMP and CALL) can be executed
• Bit 8 (HLFS): main or sub-oscillator select
0: CPU is set to select sub-oscillator when reset occurred.
1: CPU is set to select main-oscillator when reset occurred.
• Bit 7(ENWDTB): Watchdog timer enable/disable bit.
0: Enable
1: Disable
• Bit 6 (FSMD): sub-oscillator type selection.
0: RC type (internal C)
1: XTAL type (Xin and Xout)
• Bit 5, 4 (FMMD1, 0): main Oscillator type selection.
FMMD1
0
0
1
FMMD0
0
1
X
This specification is subject to change without prior notice.
Main Oscillator Type
RC type (external R, internal C)
XTAL type (R-OSCI, OSCO)
PLL type
44
04.10.2004 (V1.0)
EM78P468N
OTP ROM
• Bit 3 (HLP): Power consumption selection. If your system usually runs in green mode, it must be
set to low power consumption. Take note and help support the energy saving issue. We recommend
that low power consumption mode is selected.
0: Low power consumption mode
1: High power consumption mode
• Bit 2~0 (PR2~PR0): Protect Bit
PR2~PR0 are protect bits as explained below:
PR2
1
PR1
1
others
PR0
1
Protect
Disable
Enable
4.12 Instruction Set
Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more
operands. Normally, all instructions are executed within one single instruction cycle (one instruction
consists of 2 oscillator periods), unless the program counter is changed by instruction "MOV R2,A",
"ADD R2,A", or by instructions of arithmetic or logic operation on R2 (e.g. "SUB R2,A", "BS(C) R2,6",
"CLR R2", ⋅⋅⋅⋅). In this case, the execution takes two instruction cycles.
If for some reasons, the specification of the instruction cycle is not suitable for certain applications,
try modifying the instruction as follows:
Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", & "RETI" instructions, or
the conditional skip instructions ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") which were tested to be
true. Also execute within two instruction cycles the instructions that are written to the program
counter.
Additionally, the instruction set offers the following features:
(1) Every bit of any register can be set, cleared, or tested directly.
(2) The I/O register can be regarded as general register. That is, the same instruction can operate
on I/O register.
The symbol "R" represents a register designator that specifies which one of the registers (including
operational registers and general purpose registers) is to be utilized by the instruction. "b" represents
a bit field designator that selects the value for the bit that is located in the register "R", and affects
operation. "k" represents an 8 or 10-bit constant or literal value.
This specification is subject to change without prior notice.
45
04.10.2004 (V1.0)
EM78P468N
OTP ROM
0
0
0
0
0
0
0
0
INSTRUCTION
BINARY
0000 0000 0000
0000 0000 0001
0000 0000 0011
0000 0000 0100
0000 0000 rrrr
0000 0001 0000
0000 0001 0001
0000 0001 0010
HEX
MNEMONIC
0000
0001
0003
0004
000r
0010
0011
0012
NOP
DAA
SLEP
WDTC
IOW
ENI
DISI
RET
R
0 0000
0001
0011
0013
RETI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0001
01rr
1000
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
00rr
01rr
10rr
11rr
rrrr
rrrr
0000
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
rrrr
001r
00rr
0080
00rr
01rr
01rr
01rr
01rr
02rr
02rr
02rr
02rr
03rr
03rr
03rr
03rr
04rr
04rr
04rr
04rr
05rr
05rr
05rr
05rr
IOR
MOV
CLRA
CLR
SUB
SUB
DECA
DEC
OR
OR
AND
AND
XOR
XOR
ADD
ADD
MOV
MOV
COMA
COM
INCA
INC
DJZA
DJZ
R
A,
R,
R
R
A,
R,
A,
R,
A,
R,
A,
R,
A,
R,
R
R
R
R
R
R
0 0110
00rr
rrrr
06rr
RRCA
R
0 0110
01rr
rrrr
06rr
RRC
R
0 0110
10rr
rrrr
06rr
RLCA
R
0 0110
11rr
rrrr
06rr
RLC
R
0 0111
00rr
rrrr
07rr
SWAPA R
0 0111
0 0111
01rr
10rr
rrrr
rrrr
07rr
07rr
SWAP
JZA
0000
0000
0000
0000
0001
0001
0001
0001
0010
0010
0010
0010
0011
0011
0011
0011
0100
0100
0100
0100
0101
0101
0101
0101
R
R, A
R
R
This specification is subject to change without prior notice.
R
A
R
A
R
A
R
A
R
A
R
R
OPERATION
No Operation
Decimal Adjust A
0 → WDT, Stop oscillator
0 → WDT
A → IOCR
Enable Interrupt
Disable Interrupt
[Top of Stack] → PC
[Top of Stack] → PC,
Enable Interrupt
IOCR → A
A→R
0→A
0→R
R-A → A
R-A → R
R-1 → A
R-1 → R
A∨R→A
A∨R→R
A&R→A
A&R→R
A⊕R→A
A⊕R→R
A+R→A
A+R→R
R→A
R→R
/R → A
/R → R
R+1 → A
R+1 → R
R-1 → A, skip if zero
R-1 → R, skip if zero
R(n) → A(n-1),
R(0) → C, C → A(7)
R(n) → R(n-1),
R(0) → C, C → R(7)
R(n) → A(n+1),
R(7) → C, C → A(0)
R(n) → R(n+1),
R(7) → C, C → R(0)
R(0-3) → A(4-7),
R(4-7) → A(0-3)
R(0-3) ↔ R(4-7)
R+1 → A, skip if zero
46
STATUS
AFFECTED
None
C
T, P
T, P
None <Note1>
None
None
None
None
None <Note1>
None
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
Z
Z
Z
Z
Z, C, DC
Z, C, DC
Z
Z
Z
Z
Z
Z
None
None
C
C
C
C
None
None
None
04.10.2004 (V1.0)
EM78P468N
OTP ROM
0
0
0
0
0
INSTRUCTION
BINARY
0111 11rr
rrrr
100b bbrr rrrr
101b bbrr rrrr
110b bbrr rrrr
111b bbrr rrrr
HEX
MNEMONIC
07rr
0xxx
0xxx
0xxx
0xxx
JZ
BC
BS
JBC
JBS
R
R,
R,
R,
R,
1 00kk
kkkk
kkkk
1kkk
CALL
k
1
1
1
1
1
1
1
1
1
1
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
1000
1001
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
00kk
00kk
kkkk
1kkk
18kk
19kk
1Akk
1Bkk
1Ckk
1Dkk
1E8k
1E9K
1Fkk
JMP
MOV
OR
AND
XOR
RETL
SUB
PAGE
BANK
ADD
k
A,
A,
A,
A,
k
A,
k
k
A,
01kk
1000
1001
1010
1011
1100
1101
1110
1110
1111
OPERATION
R+1 → R, skip if zero
0 → R(b)
1 → R(b)
if R(b)=0, skip
if R(b)=1, skip
PC+1 → [SP],
(Page, k) → PC
(Page, k) → PC
k→A
A∨k→A
A&k→A
A⊕k→A
k → A, [Top of Stack] → PC
k-A → A
k->R5(1:0)
k->R4(7:6)
k+A → A
b
b
b
b
k
k
k
k
k
k
STATUS
AFFECTED
None
None <Note2>
None <Note3>
None
None
None
None
None
Z
Z
Z
None
Z, C, DC
None
None
Z, C, DC
<Note1> This instruction is applicable to IOC5 ~ IOCF
<Note2> This instruction is not recommended for R3F operation.
<Note3> This instruction cannot operate under R3F.
This specification is subject to change without prior notice.
47
04.10.2004 (V1.0)
EM78P468N
OTP ROM
4.13 Timing Diagram
AC Test Input/Output Waveform
2.4
2.0
0.8
TEST POINTS
2.0
0.8
0.4
AC Testing : Input is driven at 2.4V for logic "1",and 0.4V for logic "0".Tim ing m easurem ents are
m ade at 2.0V for logic "1",and 0.8V for logic "0".
RESET Timing (CLK="0")
NOP
Instruction 1
Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLKS="0")
Tins
CLK
TCC
Ttcc
Ttrf
Ttrr
90%
Port (n+1)
90%
10%
10%
Tiod
Port (n)
*n=0、2、4、6
This specification is subject to change without prior notice.
48
04.10.2004 (V1.0)
EM78P468N
OTP ROM
5. ABSOLUTE MAXIMUM RATINGS
Items
Supply voltage
Input voltage
Output voltage
Operation temperature
Storage temperature
Power dissipation
Operating Frequency
Symbol
VDD
VI
VO
TOPR
TSTG
PD
This specification is subject to change without prior notice.
Condition
Port5, Port6, Port7, Port8
Port5, Port6, Port7, Port8
49
Rating
Min.
Max.
GND-0.3
+7.0
GND-0.3 VDD+0.3
GND-0.3 VDD+0.3
-40
85
-65
150
500
32.768K
10M
Unit
V
V
V
℃
℃
mW
Hz
04.10.2004 (V1.0)
EM78P468N
OTP ROM
6. ELECTRICAL CHARACTERISTIC
6.1 DC ELECTRICAL CHARACTERISTICS
(Ta= 25 °C, VDD= 5.0V, GND= 0V)
Symbol
FXT
Fs
ERIC
IIL
VIH1
VIL1
VIHT1
VILT1
VIHT2
VILT2
Vdet
Parameter
ISB
Sleep mode current
ICC1
Idle mode current
ICC2
Green mode current
ICC3
Normal mode
ICC4
Normal mode
IOH1
IOL2
Typ.
Max.
Unit
8M
32.768
10M
Hz
KHz
R: 300KΩ, internal capacitance
270
384
500
KHz
R: 2.2MΩ, internal capacitance
29.5
32.768
42.6
KHz
VIN = VDD, GND
-1
0
1
µA
Ports 5, 6, 7, 8
Ports 5, 6, 7, 8
2.0
0.8
V
V
/RESET
2.0
The voltage of Vdet is determined by RC
control register
IPH
IPL
IOL1
Min.
32.768K
Low voltage detector voltage
Output High Voltage
(Ports 5, 6, 7, 8)
Output Low Voltage
(Ports 5, 6, 7, 8)
Output high voltage
(IROUT pin)
Output Low Voltage
(IR OUT pin)
Pull-high current
Pull-low current
IOH1
Condition
XTAL: VDD to 5V
Sub-oscillator
External R, internal C for
sub-oscillator
External R, internal C for
sub-oscillator
Input Leakage Current for input
pins
Input High Voltage
Input Low Voltage
Input High Threshold Voltage
(Schmitt trigger)
Input Low Threshold Voltage
(Schmitt trigger)
Input High Threshold Voltage
(Schmitt trigger)
Input Low Threshold Voltage
(Schmitt trigger)
Two cycle with two clocks
Two cycle with two clocks
V
/RESET
0.8
TCC, INT0, INT1
2.0
V
TCC, INT0, INT1
VOH = 2.4V
Vdet-0.2
Vdet
V
Vdet+0.2
V
mA
VOL = 0.4V
10
-20
Pull-high active, input pin at GND
Pull-low active, input pin at VDD
All input and I/O pins at VDD, output pin
floating, WDT disabled
/RESET= 'High', CPU OFF, sub-oscillator
clock (32.768KHz) ON, output pin floating,
LCD enable, no load
/RESET= 'High', CPU ON, used
sub-oscillator clock (32.768KHz), output pin
floating, WDT enabled, LCD enable
/RESET= 'High', Fosc=4MHz (Crystal type,
CLKS="0"), output pin floating
/RESET= 'High', Fosc=10MHz (Crystal type,
CLKS="0"), output pin floating
50
-55
55
mA
mA
VOL = 0.4V
This specification is subject to change without prior notice.
0.8
-10
VOH = 2.4V
V
20
mA
-75
75
-95
5
µA
µA
0.3
1
µA
12
16
µA
22
30
µA
2.2
2.5
mA
3.1
3.5
mA
04.10.2004 (V1.0)
EM78P468N
OTP ROM
(Ta= 25 °C, VDD= 3.0V, GND= 0V)
Symbol
FXT
Fs
ERIC
IIL
VIH1
VIL1
VIHT1
VILT1
VIHT2
VILT2
Vdet
Parameter
ISB
Sleep mode current
ICC1
Idle mode current
ICC2
Green mode current
ICC3
Normal mode
IOH1
IOL2
Typ.
Max.
Unit
8M
32.768
10M
Hz
KHz
R: 300KΩ, internal capacitance
270
384
500
KHz
R: 2.2MΩ, internal capacitance
29.5
32.768
42.6
KHz
VIN = VDD, GND
-1
0
1
µA
Ports 5, 6, 7, 8
Ports 5, 6, 7, 8
1.6
0.6
V
V
/RESET
1.6
The voltage of Vdet is determined by RC
control register
IPH
IPL
IOL1
Min.
32.768K
Low voltage detector voltage
Output High Voltage
(Ports 5, 6, 7, 8)
Output Low Voltage
(Ports 5, 6, 7, 8)
Output high voltage
(IROUT pin)
Output Low Voltage
(IR OUT pin)
Pull-high current
Pull-low current
IOH1
Condition
XTAL: VDD to 5V
Sub-oscillator
External R, internal C for
sub-oscillator
External R, internal C for
sub-oscillator
Input Leakage Current for input
pins
Input High Voltage
Input Low Voltage
Input High Threshold Voltage
(Schmitt trigger)
Input Low Threshold Voltage
(Schmitt trigger)
Input High Threshold Voltage
(Schmitt trigger)
Input Low Threshold Voltage
(Schmitt trigger)
Two cycle with two clocks
Two cycle with two clocks
V
/RESET
0.6
TCC, INT0, INT1
1.6
V
TCC, INT0, INT1
VOH = 2.4V
Vdet-0.2
Vdet
V
Vdet+0.2
V
mA
VOL = 0.4V
7
-3.5
Pull-high active, input pin at GND
Pull-low active, input pin at VDD
All input and I/O pins at VDD, output pin
floating, WDT disabled
/RESET= 'High', CPU OFF, sub-oscillator
clock (32.768KHz) ON, output pin floating,
LCD enable, no load
/RESET= 'High', CPU ON, used
sub-oscillator clock (32.768KHz), output pin
floating, WDT enabled, LCD enable
/RESET= 'High', Fosc=4MHz (Crystal type,
CLKS="0"), output pin floating
51
-16
16
mA
mA
VOL = 0.4V
This specification is subject to change without prior notice.
0.6
-1.8
VOH = 2.4V
V
14
mA
-23
23
-30
30
µA
µA
0.1
1
µA
4
8
µA
10
20
µA
0.73
1.2
mA
04.10.2004 (V1.0)
EM78P468N
OTP ROM
6.2 AC Electrical Characteristics
(Ta=- 40°C ~ 85 °C, VDD=5V±5%, GND=0V)
Symbol
Parameter
Dclk
Input CLK duty cycle
Tins
Ttcc
Tdrh
Trst
Twdt
Tset
Thold
Tdelay
Tiod
Ttrr1
Ttrf1
Ttrr2
Ttrf2
Instruction cycle time
(CLKS="0")
TCC input period
Device reset hold time
/RESET pulse width
Watchdog timer period
Input pin setup time
Input pin hold time
Output pin delay time
I/O delay for EMI enable
Through rate for EMI
enable(rising)
Through rate for EMI
enable(falling)
Through rate for EMI
enable(rising)
Through rate for EMI
enable(falling)
Conditions
Crystal type
RC type
Ta = 25°C
Ta = 25°C
Ta = 25°C
Min
45
100
500
(Tins+20)/N*
11.3
2000
11.3
Typ
50
Max
55
DC
DC
16.2
21.6
21.6
6
Unit
%
ns
ns
ns
ms
ns
ms
ns
ns
ns
ns
Cload=20pF
Cload=150pF
4
16.2
0
20
50
5
Cload=150pF
45
50
55
ns
Cload=150pF
45
50
55
ns
Cload=300pF
90
100
110
ns
Cload=300pF
90
100
110
ns
* N= selected pre-scaler ratio.
This specification is subject to change without prior notice.
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EM78P468N
OTP ROM
7. Application Circuit
IROUT control external BJT circuit to drive infrared emitting diodes
IROUT direct drive infrared emitting diodes
This specification is subject to change without prior notice.
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EM78P468N
OTP ROM
APPENDIX A:
Package information
This specification is subject to change without prior notice.
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EM78P468N
OTP ROM
APPENDIX B:
EM78P468N Program Pin List
It uses DWRT to program EM78P468N IC’s. The DWTR connector is selected by CON4 (EM78P451), and
software is selected by EM78P468N.
Program Pin Name
VPP
ACLK
DINCLK
DATAIN
/PGMB
/OEB
VDD
GND
QFP Pin Number
25
32
33
34
38
39
29
26
IC Pin Name
/RESET
P54/INT0
P55/INT1
P56/TCC
P60
P61
VDD
GND
Wiring diagram for DWTR (Display writer).
This specification is subject to change without prior notice.
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EM78P468N
OTP ROM
ELAN (HEADQUARTER) MICROELECTRONICS CORP., LTD.
Address : No. 12, Innovation 1st. Rd. Science-Based Industrial Park, Hsinchu City, Taiwan.
Telephone: 886-3-5639977
Facsimile : 886-3-5639966
ELAN (H.K.) MICROELECTRONICS CORP., LTD.
Address : Rm. 1005B, 10/F, Empire Centre, 68 Mody Road, Tsimshatsui, Kowloon, Hong Kong.
Telephone: 852-27233376
Facsimile : 852-27237780
E-mail : [email protected]
ELAN MICROELECTRONICS SHENZHEN, LTD.
Address : SSMEC Bldg. 3F , Gaoxin S. Ave. 1st , South Area , Shenzhen High-tech Industrial Park., Shenzhen
Telephone: 86-755-26010565
Facsimile : 86-755-26010500
ELAN MICROELECTRONICS SHANGHAI, LTD.
Address : #23 Building No.115 Lane 572 BiBo Road. Zhangjiang, Hi-tech Park, Shanghai
Telephone: 86-21-50803866
Facsimile : 86-21-50804600
Elan Information Technology Group.
Address: 1821 Saratoga Avenue, suite 250, Saratoga, CA 95070, USA
Telephone: 1-408-366-8225
Facsimile : 1-408-366-8220
Elan Microelectronics Corp. (Europe)
Address: Dubendorfstrasse 4, 8051 Zurich, Switzerland
Telephone: 41-43-2994060
Facsimile : 41-43-2994079
Email : [email protected]
Web-Site : www.elan-europe.com
Copy © 2004 by Elan Microelectronics Corp.
Elan is the owner of the intellectual property rights of the information and technology
mentioned above, as may exist now and hereafter come into exist, and all renewals and
extensions thereof. However, there is no warranty for the use of the specifications described,
either expressed or implied, including, but not limited to ,the implied warranties of
merchantability and fitness for particular purpose. The entire risk as to the quality and
performance of the application is with the user, therefore, the user will be liable for damages
including any general, special, incidental or consequential damages arising out of the use or
inability to use the information and technology. Elan reserves the right to modify the
information without prior notification. The most up-to-day information will be available on the
web site (http://www.emc.com.tw)
This specification is subject to change without prior notice.
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04.10.2004 (V1.0)