ETC FA5502P/M

Quality is our message
FA5502P/M
FUJI Power Supply Control IC
Power Factor Correction
FA5502P/M
Application Note
June `02
Fuji Electric Co., Ltd.
Matsumoto Factory
1
Quality is our message
FA5502P/M
WARNING
1.This Data Book contains the product specifications, characteristics, data, materials, and
structures as of June 2002. The contents are subject to change without notice for specification
changes or other reasons. When using a product listed in this Data Book, be sure to obtain the
latest specifications.
2. All applications described in this Data Book exemplify the use of Fuji's products for your
reference only. No right or license, either express or implied, under any patent, copyright, trade
secret or other intellectual property right owned by Fuji Electric Co., Ltd. is (or shall be deemed)
granted. Fuji makes no representation or warranty, whether express or implied, relating to the
infringement or alleged infringement of other's intellectual property rights which may arise from
the use of the applications described herein.
3. Although Fuji Electric is enhancing product quality and reliability, a small percentage of
semiconductor products may become faulty. When using Fuji Electric semiconductor products in
your equipment, you are requested to take adequate safety measures to prevent the equipment
from causing a physical injury, fire, or other problem if any of the products become faulty. It is
recommended to make your design fail-safe, flame retardant, and free of malfunction.
4.The products introduced in this Data Book are intended for use in the following electronic and
electrical equipment which has normal reliability requirements.
• Computers • OA equipment • Communications equipment (terminal devices)
• Measurement equipment
• Machine tools • Audiovisual equipment
• Electrical home appliances • Personal equipment
• Industrial robots, etc.
5.If you need to use a product in this Data Book for equipment requiring higher reliability than
normal, such as for the equipment listed below, it is imperative to contact Fuji Electric to obtain
prior approval. When using these products for such equipment, take adequate measures such
as a backup system to prevent the equipment from malfunctioning even if a Fuji's product
incorporated in the equipment becomes faulty.
• Transportation equipment (mounted on cars and ships)
• Trunk communications equipment
• Traffic-signal control equipment
• Gas leakage detectors with an auto-shut-off feature
• Emergency equipment for responding to disasters and anti-burglary devices • Safety devices
6. Do not use products in this Data Book for the equipment requiring strict reliability such as
(without limitation)
• Space equipment
• Aeronautic equipment
• Atomic control equipment
• Submarine repeater equipment
• Medical equipment
7. Copyright © 1995 by Fuji Electric Co., Ltd. All rights reserved. No part of this Data Book may be
reproduced in any form or by any means without the express permission of Fuji Electric.
8. If you have any question about any portion in this Data Book, ask Fuji Electric or its sales
agents before using the product. Neither Fuji nor its agents shall be liable for any injury caused
by any use of the products not in accordance with instructions set forth herein.
2
Quality is our message
FA5502P/M
CONTENTS
page
1.
Description
•••••••••••••••
4
2.
Features
•••••••••••••••
4
3.
Outline
•••••••••••••••
4
4.
Block diagram
•••••••••••••••
5
5.
Pin assignment
•••••••••••••••
5
6.
Ratings and characteristics
•••••••••••••••
6
7.
Characteristic curves
•••••••••••••••
9
8.
Description of each circuit
•••••••••••••••
13
9.
Design advice
•••••••••••••••
18
Example of application circuit
•••••••••••••••
23
10.
Note
• Parts tolerance and characteristics are not defined in all application described in this Data book. When design an
actual circuit for a product, you must determine parts tolerances and characteristics for safe and economical
operation.
3
Quality is our message
FA5502P/M
1. Description
FA5502P/M is a control IC for a power factor correction system. This IC uses a CMOS device with high dielectric
strength (30V) to implement low power consumption. This IC uses the average current control system to ensure stable
operation. With this system, a power factor of 99% or better can be achieved.
2. Features
•
•
•
•
•
•
•
•
•
•
Low current consumption by CMOS process
Stand-by : 3µA(max), Start-up : 30µA(max), Operating : 4mA(typ)
Good regulation of PFC output voltage from no-load to full-load
Drive circuit for connecting a power MOSFET(IOUT = ±1.5A)
Pulse-by-pulse overcurrent and overvoltage limiting function
±2% accuracy reference voltage for setting DC output and overvoltage protection
Output ON/OFF control function by external signal
External synchronizing input pin for synchronous operation with other circuits
Undervoltage lockout function (ON:16.5V, OFF:8.9V)
16-pin package (DIP/SOP)
3. Outline
DIP-16 (FA5502P)
16
SOP-16 (FA5502M)
9
1
8
8
3.4 ± 0.1
19.4 ± 0.3
1.5 ± 0.3
1. 80 ± 0. 05
0.3 ±
0.1
7.6 ± 0.2
17.78 ± 0.3
10 º
0.08
0º - 15º
1.27
4
0.40 ± 0.05
0. 10 ± 0. 10
0.5 ± 0.1
4.0 ± 0.3
7.3 ± 0.5
10.2 ± 0.1
2.54 TYP
0. 75 ± 0. 1
9
7. 8 ± 0. 2
1
16
5. 3 ± 0. 1
6.5 ± 0.2
0.15 ± 0.05
- 0
º
Quality is our message
FA5502P/M
4. Block diagram
SYNC
(14)
REF(13)
CS(11)
CT(15)
VCC(10)
ON/OFF(12)
ON/OFF
OSC
11µA
UVLO
5V
16.5V/8.9V
3.95V/
2.8V
REF
VC
(9)
OUT
(8)
PWM.COMP
1.55V
+
15k
CUR.AMP
4.85k
R
S
S
0.39V
GND
(7)
ER.AMP
-
11k
+
MUL
1.55V
OVP.COMP
Q
1.64V
OCP.COMP
IDET(16)
IFB(1)
VDET(3)
IIN-(2)
5. Pin assignment
Pin No.
Symbol
Function
error amplifier
1
IFB
Current
output
2
IIN-
Inverting input to current
error amplifier
3
VDET
Multiplier input
4
OVP
5
VFB
Overvoltage
protection
input
Voltage error amplifier
output
6
VIN-
Inverting input to voltage
error amplifier
7
8
9
GND
OUT
VC
Ground
Output
Power supply to output
circuit
Power Supply
Soft-start
Output ON/OFF control
input
Reference voltage
Oscillator synchronization
input
Oscillator timing capacitor
and resistor
10
11
12
VCC
CS
ON/OFF
13
14
REF
SYNC
15
CT
16
IDET
Non-inverting input
current error amplifier
Description
Output of current error amplifier to connect
compensation network
Inverting input of current error amplifier to
connect compensation network
Input of multiplier to detect sinusoidal
waveform
Input to overvoltage protection circuit
Output of voltage error amplifier to connect
compensation network
Inverting input to voltage error amplifier to
detect PFC output voltage
Ground
Output for direct driving a power MOSFET
Power supply to output circuit
Power supply for IC
A pin to connect a capacitor for soft-start
Input of ON/OFF control circuit
Reference voltage output
Input of synchronization signal
A pin to connect timing capacitor and
resistor to set oscillation frequency
Input of inductor current signal
to
5
VIN(6)
VFB
(5)
OVP
(4)
Quality is our message
FA5502P/M
6. Ratings and characteristics
The contents are subject to change without notice. When using a product, be sure to obtain the latest
specifications.
(1) Absolute maximum ratings
Item
Supply
Voltage
VC pin
VCC pin
Low impedance source
(Icc>15mA)
VCC pin
Internal zener clamp voltage
(Icc<15mA)
Output peak current
SYNC,VIN-,VDET and OVP pins
Input voltage
IDET pin input voltage
ON/OFF pin input voltage
REF pin source current
Power dissipation (Ta=25ºC)
Symbol
VC
Rating
Vcc
Unit
V
VCC1
30
V
VCC2
Self Limiting
V
IOUT
±1.5
A
VSYNC
VVINVVDET
VOVP
VIDET
VON/OFF
-0.3 to 5.0
V
-10 to 5.0
-0.3 to Vcc
V
V
-10
mA
850
mW
650
mW
Ambiance temperature
Ta
-30 to +105
°C
Maximum junction temperature
Tj
+150
°C
Storage temperature
Tstg
-40 to +150
°C
Note) VC and ON/OFF pins voltage must be less than or equal to VCC pin voltage in all the conditions.
Peak current at OUT pin may flow to rated value neither according to supply voltage nor temperature conditions.
DIP-16
SOP-16
IREF
Pd
Ma xim um diss ipation curve
Maximum power
dissipation
650mW(SOP)
850mW(DIP)
-30
25
105
Ambience temperature Ta(ºC)
150
(2) Recommended operating conditions
Item
Supply voltage
IDET pin input voltage
VDET pin input voltage
VDET pin peak input voltage
Oscillation frequency
Oscillation timing capacitance
Oscillation timing resistance
Noise filter resistance connected to IDET
pin
REF-GND capacitance
Note) If the sync hronous operation is not
Symbol
Vcc,Vc
VIDET
VVDET
VPVDET
fOSC
CT
RT
Rn
MIN
10
-1.0
0
0.65
15
330
10
0
TYP.
MAX
28
0
2.4
2.4
150
1000
75
27
Unit
V
V
V
V
kHz
pF
kΩ
Ω
Cref
0.1
0.47
µF
neces sary, connec t the SYNC pin to GND.
6
Quality is our message
FA5502P/M
(3) Electrical Characteristics (Unless otherwise specified, Vcc=Vc=18V, Ta=25°C, CT=470pF, RT=22kΩ)
Reference voltage section
Item
Output voltage
Line regulation
Load regulation
Temperature stability
(REF pin)
Symbol
VREF
Vrdv
Vrdi
VrdT
MAX
5.2
±25
Unit
V
mV
mV
mV/°C
TYP
MAX
Unit
78
85
kHz
±1
±0.04
3.4
±3
±0.07
%
%/°C
V
1.0
1.5
2.0
75
125
175
V
µA
MIN
91
TYP
94
MAX
97
Unit
%
Overcurrent limiter circuit section
(IDET pin)
Item
Symbol
Condition
Input threshold voltage
VTHOCP
IDET pin voltage
Delay time
Tpd OCP
MIN
-1.20
TYP
-1.10
150
MAX
-1.00
Unit
V
ns
Soft start circuit section
Item
Charge current
MIN
TYP
-11
0.34
3.40
MAX
Unit
µA
V
V
MIN
TYP
3.55
2.40
3.95
2.80
MAX
±500
4.35
3.20
Unit
nA
V
V
MIN
1.519
TYP
1.550
±0.5
±0.2
MAX
1.581
Unit
V
mV
mV/°C
nA
dB
V
mV
mA
µA
Oscillator section
Item
MIN
4.8
TYP
5
-50
-25
±0.5
Condition
CT=470pF,
RT=22kΩ, Ta=25°C
Vcc=10 to 28V
Ta=-30 to +105°C
MIN
71
VTHSYNC
SYNC pin voltage
ISYNC
SYNC pin=2V
(CT, SYNC pin)
Symbol
Oscillation frequency
fOSC
Voltage stability
Temperature stability
Output peak voltage
Synchronizing input
threshold voltage
SYNC pin input current
fdv
fdT
VOSC
Pulse width modulation circuit section
Item
Symbol
Maximum duty cycle
DMAX
Input threshold voltage
(CS pin)
Symbol
ICHG
VTHCS0
VTHCSM
Output ON/OFF control circuit section
Item
Symbol
On-state input current
ITHON
VTHON
ON/OFF control
threshold voltage
VTHOFF
Condition
Vcc=10 to 28V
ILoad=0.1 to 2mA
Ta=-30 to 105°C
(OUT pin)
Condition
Condition
CS pin=0V
Dutycycle=0%
Dutycycle=DMAX
(ON/OFF pin)
Condition
ON/OFF pin=VTHON
OFF→ON
ON→OFF
Voltage error amplifier section
(VIN-, VFB pin)
Item
Symbol
Condition
Reference voltage
Vr
Line regulation
Vredv
Vcc=10 to 28V
Temperature stability
VredT
Ta=-30 to 105°C
Input bias current
IBE
Open loop gain
Ave
VOE+
No load
Output voltage
VOENo load
Output source current
IOE+
VFB pin=0V
Output sink current
IOEVFB pin=2V
±500
60
3.7
7
4.1
50
-2.8
280
200
Quality is our message
FA5502P/M
Current error amplifier section
(IIN-, IFB, IDET pin)
Item
Symbol
Condition
VDET pin=0V
Input threshold voltage
VTHIDET
VFB pin=Vr
Rn=30Ω
Input bias current
IBC
IDET pin=0V
Open loop gain
Avc
VOC+
No load
Output voltage
No load
VOCOutput source current
IOC+
IFB pin=0V
Output sink current
IOC-
Unit
-50
0
50
mV
-350
60
3.55
-250
-150
3.8
50
-5.1
200
µA
dB
V
mV
mA
800
TYP
1.640
MAX
1.673
Unit
V
1.037
1.058
1.079
-
-1.0
-0.3
150
MIN
TYP
MAX
Unit
VTHUON
15.5
16.5
17.5
V
VTHUOFF
8.2
8.9
9.6
V
VUHYS
6.8
7.6
8.4
V
Condition
IOL=100mA
IOH=-100mA,
Vcc=18V
No load
No load
MIN
TYP
0.5
MAX
1.0
Unit
V
15.5
16.5
V
50
50
ns
ns
Condition
Vcc=14V
Vcc=start threshold
MIN
α
Input bias current
Delay time
IBOVP
Tpdovp
Undervoltage lockout circuit section
Item
Symbol
(OUT, VC pin)
Symbol
VOL
High output voltage
VOH
Rise time
Fall time
tr
tf
Power supply current
(VCC pin)
Item
Symbol
Stand-by current
ICCST
Starting-up current
ICCSTA
Operating-state supply
ICCOP
current
OFF-state supply current
ICCOFF
(OVP pin)
Condition
OVP pin voltage
OVP pin=0V
(VCC pin)
Condition
MIN
0
1.5
-1.5
TYP
MIN
1.607
µA
Unit
V
V
µA
µA
-
VTHOVP/Vr ratio
Output circuit section
Item
Low output voltage
MAX
MAX
2.4
3.5
Overvoltage protection circuit section
Item
Symbol
Input threshold voltage
VTHOVP
Hysteresis voltage
TYP
IFB pin=2V
Multiplier section
(VDET, IIN-, VFB pin)
Item
Symbol
Condition
VDET pin input voltage
V MVDET
VFB pin input voltage
VMVFB
Input bias current
IBVDET
VDET pin=0V
Output current
IM
IIN- pin=0V
Output voltage factor
K
Start-up threshold
voltage
Shutdown threshold
voltage
MIN
-0.5
-44
-1.2
10
MAX
3
30
Unit
µA
µA
No load
4
6
mA
ON/OFF pin=0V
80
200
µA
8
TYP
µA
ns
Quality is our message
FA5502P/M
7. Characteristic curves
(Unless otherwise specified, Vcc=Vc=18V, Ta=25°C, CT=470pF, RT=22kΩ)
Oscillation frequency (fosc) vs.
timing resistor (R T)
Oscillation frequency(fosc) vs.
supply voltage(Vcc)
78.4
78.2
CT=330pF
fosc (kHz)
fosc(kHz)
100
CT=470pF
CT=1000pF
10
77.8
77.6
CT=680pF
10
78.0
77.4
10
100
15
20
Vcc (V)
RT (k Ω )
Oscillation frequency(fosc) vs.
junction temperature(Tj)
80
25
30
Maximum duty cycle(DMAX) vs.
timing resistor(RT)
100
98
79
DMAX (%)
fosc (kHz)
96
78
77
76
92
90
88
CT=330pF
to 1000pF
86
75
-50
0
50
Tj (°C)
100
84
150
10
Maximum duty cycle(DMAX) vs.
Junction temperature(Tj)
95
D (%)
93
92
91
90
-50
0
50
Tj (°C)
100
100
RT (kΩ)
Output duty cycle(D) vs.
CS pin voltage(VCS)
94
DMAX (%)
94
150
100
90
80
70
60
50
40
30
20
10
0
0
1
2
3
VCS (V)
9
4
5
Quality is our message
FA5502P/M
IDET pin voltage(VIDET) vs.
IIN- pin voltage(VIIN- )
Multiplier input voltage(VVDET) vs.
output voltage(V IIN-)
V VFB=1.1V V VFB=0.5V
VVFB=1.5V
1.0
V VFB=1.7V
VVFB=2.9V
V VFB=2.4V
V VFB=2.1V
VVFB=1.9V
0.8
0.6
0.4
V IDET(V)
VIIN-(V)
1.2
(Normal operation)
0.0
1.4
-0.5
-1.0
0.2
0.0
0
1
2
-1.5
3
0
VVDET (V)
1
1.5
1.56
1.554
1.552
1.55
Vr (V)
1.550
1.548
1.54
1.53
1.546
1.544
1.52
10
15
20
25
30
-50
0
50
Tj (°C)
Vcc (V)
OVP input threshold voltage(V THOVP) vs.
junction temperature(Tj)
1.66
-1.07
1.65
-1.08
1.64
1.63
-1.10
-1.11
1.61
-1.12
0
50
Tj (°C)
100
150
-1.09
1.62
-50
100
OCP input threshold voltage(V THOCP) vs.
junction temperature(Tj)
VTHOCP(V)
VTHOVP(V)
VIIN- (V)
Voltage error amplifier
reference voltage(Vr) vs. junction temperature(Tj)
Voltage error amplifier
reference voltage(Vr) vs. supply voltage(Vcc)
Vr (V)
0.5
-50
150
0
50
Tj (°C)
10
100
150
Quality is our message
FA5502P/M
4.5
3.5
4.0
3.0
V THOFF(V)
V THON(V)
ON/OFF control circuit
ON threshold voltage(VTHON) vs.
junction temperature(Tj)
3.5
3.0
ON/OFF control circuit
OFF threshold voltage(VTHOFF) vs.
junction temperature(Tj)
2.5
2.0
1.5
2.5
1.0
2.0
-50
0
50
Tj (°C)
100
-50
150
L-level output voltage(V OL) vs.
supply voltage(Vcc)
0.9
Vcc-V OH (V)
0.25
VOL (V)
100
150
IOH=-100mA
0.8
0.30
0.20
0.15
0.10
0.7
0.6
0.5
0.4
0.3
0.2
0.05
0.1
0.00
0.0
10
15
20
Vcc (V)
25
10
30
UVLO startup threshold voltage(VTHUON) vs.
junction temperature(Tj)
17.0
15
20
Vcc (V)
25
30
UVLO shutdown threshold voltage(V THUOFF) vs.
junction temperature(Tj)
9.00
16.8
8.95
VTHUOFF(V)
VTHUON(V)
50
Tj (°C)
H-level output voltage(V OH) vs.
supply voltage(Vcc)
IOL=100mA
0.35
0
16.6
16.4
8.90
8.85
16.2
16.0
8.80
-50
0
50
100
150
-50
Tj (°C)
0
50
Tj (°C)
11
100
150
Quality is our message
FA5502P/M
Supply current(Icc) vs. supply voltage(Vcc)
Supply current(Icc) vs. supply voltage(Vcc)
(enlarged)
16
ON/OFF pin:
pull up to Vcc
14
10
Icc (mA)
Icc (mA)
12
8
6
4
2
0
0
10
20
Vcc (V)
30
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
40
ON/OFF pin:
pull up to Vcc
0
10
20
Vcc (V)
30
40
Operating-state supply current(Iccop) vs.
junction temperature(Tj)
4.5
4.0
Iccop (mA)
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-50
0
50
Tj (°C)
100
150
OFF-state supply current(ICCOFF) vs.
supply voltage(Vcc)
700
OFF-state supply current(ICCOFF) vs.
supply voltage(Vcc) (enlarged)
250
600
200
ICCOFF(µA)
ICCOFF(µA)
500
400
300
150
100
200
50
100
0
0
10
15
20
Vcc (V)
25
30
10
12
15
20
Vcc (V)
25
30
Quality is our message
FA5502P/M
8. Description of each circuit
(1) Oscillator section
The oscillator generates sawtooth waveform
between 0.3V and 3.4V by charging and discharging
capacitor. Fig.1 shows the connection. The oscillation
frequency is determined by CT and RT.
(see characteristics curve).
Rsy
synchronizing
signal
CT
15
CT
OSC
SYNC pin voltage waveform
less
than
5V
0.3V
t
Dmax
VSYNC
=1.5V(typ)
D2
Fig.2 SYNC pin circuit (1)
3.4V
0
16k
SYNC pin
signal
SYNC pin voltage
RT
CT pin voltage
REF
SYNC
14
The oscillator waveform is input to the PWM
comparator. The oscillator is also used for determining
the maximum duty cycle of output pulses. Concretely,
a signal is sent to the output circuit section and the
OUT pin is forced to be Low level during the CT
discharge period (fall time of CT pin voltage).
13
OSC
Csy
Dead time
2V
more than 50ns
1V
less than 200ns
Fig.1 Oscillator circuit
0
SYNC pin (pin 14) is a synchronizing signal input pin.
It is usable for synchronized operation. When it is
desired to adopt synchronized operation, the
free-running frequency (determined by CT and RT)
must be set about 10% lower than that of external
synchronizing signal.
t
Fig.3 Condition for SYNC pin signal
Rsy
The input resistance in SYNC pin is approximately
16kΩ. Usually, a square-wave synchronizing signal is
differentiated by R and C, and the voltage input to
SYNC pin is so arranged to be below 1V within CT
discharge period. Concretely, the waveform must
satisfy the condition in Fig.3.
Depending on the amplitude, etc. of square-wave
signal used as external synchronizing signal, the RC
differentiating circuit shown in Fig.2 could not generate
a waveform in Fig.3. In such a case, add a resistor
between SYNC pin and GND so as to clear the
condition in Fig.3.
OSC
Csy
SYNC
14
synchronizing
signal
16k
R14
D2
Fig.4 SYNC pin circuit (2)
CT pin voltage
t
Synchronizing
signal
Fig.5 shows timing chart of synchronized operation.
t
Note that diode D2 in Fig.2 is required so that no
negative voltage will be applied to SYNC pin while in
the discharge period of capacitor Csy in the
differentiating circuit. Considering the rated voltage of
SYNC pin, use a Schottky diode of a low forward
voltage.
SYNC pin
voltage
t
OUT pin
voltage
t
Unless the external synchronization function is used,
connect SYNC pin to GND pin to avoid a malfunction.
Fig.5 Timing chart of synchronized operation
13
Quality is our message
FA5502P/M
(2) Voltage error amplifier and overvoltage
limiting circuit
(3) Current error amplifier and overcurrent
limiter circuit
ER.AMP is an error amplifier which constitutes a
voltage feedback loop for keeping the output voltage
constant. The non-inverting input is internally
connected to reference voltage Vr of 1.55V (typ.).
Fig.6 shows the connection. The output voltage is
determined by:
CUR.AMP is an error amplifier which constitutes a
current loop to control the line current to a sinusoidal
waveform. As shown in Fig.7, to IIN- pin (pin 2), a
multiplier output is connected via resistor RA as a
current reference signal. Inductor current is monitored
by IDET pin (pin 16). The IDET pin should be used
within the voltage range from 0V to –1.0V in normal
operation. RC network for loop compensation is
connected between IFB pin and IIN- pin. According to
the circuit in Fig.7, the characteristics of voltage gain
AV are as shown in Fig.8. Where,
R1 + R2
× Vr • • • • • (1)
R1
VO =
The error amplifier output is pinned out at VFB pin
(pin 5). Between VFB pin and VIN- pin, RC network
are connected for loop compensation. The voltage
gain Av is expressed by
AV =
R4
• • • • • (2)
R3(1 + jωC1× R 4 )
Z=
1
• • • • • (5)
2πR5 × C3
P=
1
2πR5 × C
Cutoff frequency fc is expressed by:
fC =
Voltage gain (G1) between Z and P (gain between
IDET pin and IFB pin) in Fig.8 is:
1
• • • • • (3)
2πC1× R 4
If 100Hz or 120Hz ripples appear at the error
amplifier output, the PFC converter will not operate
stably. Therefore, determine C1 and R4 so that voltage
gain Av at 100 Hz or 120 Hz will be small enough. Also
set fc to approximately 1Hz to ensure a stable
operation. Practically, the optimum value should be
determined by evaluation in the actual circuit.
To limit the output voltage when it has risen above
the normal voltage, overvoltage limiting comparator
OVP.COMP is incorporated. Its threshold voltage Vp is
as follows:
VP = α × Vr (α=1.058(typ)) • • • • • (4)

 R5

G1 = 20 log 0.75
+ 1  • • • • • (7)
RA



Select C2 and C3 so that P/Z will be about 10 for
adequate phase margin. The output of current error
amplifier is input to PWM comparator.
The optimum value of loop compensation should be
determined by evaluation in actual circuit referring to
application circuit, etc.
To limit the overcurrent, overcurrent limiting
comparator OCP.COMP is provided. The threshold
voltage at IDET pin is -1.10V (typ.). If a noise is picked
up at IDET pin, suppress it by connecting Rn and Cn.
Rn must be lower than 27 Ω.
According to the connection in Fig.6, therefore, the
output overvoltage is limited to 1.058 times (typ.) the
normal output voltage.
MUL
R5
Vo
C1
R2
5
R4
6
C2 × C3
• • • • • (6)
C2 + C3
C=
1
C3
VFB
C2
VIN- ER.AMP
MUL
R3
2
Vm
IFB
IIN-
RA
11k
PWM
comparator
IDET RC
R1
CUR.AMP
RB
16
4.85k
Vr
=1.55V(typ.)
4
Rn
Cn
REF
5V
15k
OCP.COMP
F.F.
OVP OVP.COMP
F.F.
Vp
=1.058Vr(typ.)
currnet
detection
0.39V
Fig.7 Current error amplifier and overcurrent limiting
circuit
Fig.6 Voltage error amplifier and overvoltage limiting
circuit
14
Quality is our message
FA5502P/M
voltage gain[dB]
Normal operation
VIFB
VCT
G1
VCS
Z
P
frequency
t
OUT
pin
t
Fig.8 Voltage gain of CUR.AMP
Operation with Dmax
(4) PWM comparator
Fig.9 shows the configuration of PWM comparator.
Oscillator output VCT and current error amplifier output
VIFB are compared. While VCT < VIFB, PWM
comparator output goes High and OUT pin also goes
High. Note that, during the oscillator discharge period,
OUT pin is forced to be Low, thereby determining the
maximum duty cycle. (see characteristics curve).
CS pin (pin 11) is a soft start pin. When start up, an
internal constant current (11µA (typ.)) charges
capacitor C4 for soft start. Priority is given to V CS or
VIFB whichever is lower. Fig.10 shows PWM
comparator timing chart.
CUR.AMP output
(IFB pin)
VCT
Oscillator output
(CT pin)
Output
circuit
PWM.COMP
VIFB
CS
11
C4
VCS
7.5V
11µA
VCS
VIFB
VCT
t
OUT
pin
t
Fig.10 PWM comparator timing chart
(5) Multiplier
The multiplier generates a current reference signal.
The rectified line voltage is divided down by resistor
and monitored by VDET pin (pin 3). Considering the
dynamic range of multiplier, design the R6 and R7 in
Fig.11 so that the peak voltage at VDET pin within a
range from 0.65V to 2.4V over the entire range of line
voltage. VFB pin is normally above 1.55V and, at this
status, multiplier output voltage Vm is approximately
expressed by:
Vm = 1.25 − K × ( VVFB − 1.55) × VVDET • • • • • (8)
Where
K: Output voltage factor (multiplier section)
Fig.9 PWM comparator circuit
When VFB pin is lower than 1.55V, compensation
circuit for light load operates.
As shown in Fig.7, Vm is applied via a resistor of
11 kΩ to inverting input (IIN-) of current error amplifier
CUR. AMP. (For input/output characteristics of
multiplier, see characteristics curve.)
VIN
VVFB
R7
3
VDET
VVDET
MUL
ER.AMP output
(VFB pin)
Vm
R6
Fig.11 Multiplier circuit
15
Quality is our message
FA5502P/M
(6) ON/OFF control circuit
VCC
Fig.12 shows the configuration of the ON/OFF
control circuit. The ON/OFF control circuit consists of a
comparator with hysteresis. To turn the IC from OFF
mode to operating mode, pull up the ON/OFF pin
voltage to 3.95V (typ.) or higher. On the other hand, to
turn the IC from operating mode to OFF mode, pull
down the ON/OFF pin to 2.80V (typ.) or lower.
In the OFF mode, the reference (REF) voltage is cut
off, and the CS pin and OUT pin go approximately 0V.
IC consumption current during OFF mode is 200µA
(max.) which is much smaller than at an operating
mode.
The input current at ON/OFF pin is a very small
value of 500nA.
In the case that external signal is applied to ON/OFF
pin, the ON/OFF pin voltage must not exceed the VCC
pin voltage, even when start up or stop operation.
If ON/OFF operation is not made by external signal,
the ON/OFF pin is normally pulled up to Vcc pin
through 10kΩ to 1MΩ. Then ON/OFF pin voltage goes
to approximately Vcc voltage.
ON/OFF
12
REF circuit
Output circuit
3.95/2.80V
Fig.12 ON/OFF control circuit
10
VC
OUT
Rg1
C5
9
8
Rg2
GND
7
Shottky
diode
Fig.13 Output circuit
(8) Undervoltage lockout circuit
This IC contains an undervoltage lockout circuit to
prevent malfunction when the Vcc voltage drops.
When the Vcc voltage rises from 0V, this IC starts
operation at 16.5V (typ.). If the Vcc voltage drops after
the IC starts up, this IC stops operation at 8.9V(typ.).
When IC stops operation by undervoltage lockout
circuit, OUT pin and CS pin is kept low
(9) Compensation circuit for light load
If the output of multiplier and the input of current
error amplifier do not have offset voltage, the input
current to the converter is approximately zero under
condition that the PFC converter operates in no load.
But an actual multiplier and current error amplifier may
have offset voltage. If the offset voltage is negative,
the input current, which corresponds to the offset
voltage, flows into the converter even when the PFC
converter operates in no load. In this case, the PFC
output voltage rises abnormally because of too much
input current.
(7) Output circuit
As shown in Fig.13, VC pin (pin 9) is configured as
the high power terminal, independent of the IC power
terminal (VCC pin). This pin allows an independent
drive resistance when the power MOSFET is ON and
OFF. Suppose the drive resistance when ON and OFF
are Rg (on) and Rg (off),
Rg(on)=Rg1+Rg2 • • • • • (9)
Rg(off)=Rg2 • • • • • (10)
At standby, the OUT pin is kept Low.
If the drain voltage of power MOSFET oscillates, a
parasitic capacitance between gate and drain may
swing the OUT pin (pin 8) of IC below 0V. If OUT pin
voltage falls below -0.3V, a current may flow to the
parasitic element in IC, whereby the IC may
malfunction. In such a case, Schottky diode must be
connected between OUT pin and GND so as not to
allow a parasitic current to flow to IC.
To avoid these, this IC has an automatic offset
correction circuit for light load. The output voltage of
error amplifier is approximately 1.55V or higher in
normal operation.
If the output voltage drops below 1.55V, this circuit
operates. If there is a negative offset voltage, the
output voltage of error amplifier falls below 1.55V in
the case that the PFC converter operates in no load or
light load. Then, the offset voltage is corrected in the
multiplier circuit. Because of this operation, even
under no load or light load, the PFC output voltage
does not rise abnormally, but is always kept stable.
The amount of correction changes linearly according
to the output of error amplifier, which can make
operation stable.
Fig.14 shows the outline of the effect of this circuit.
If VC pin is fed with a source which is independent
of VCC pin, the voltage of VC pin must not exceed that
of VCC pin even start up or stop operation.
16
Quality is our message
FA5502P/M
AC line current
Without compensation
full load
no-load
offset current
0
t
1/2 of line frequency
AC line current
With compensation
full load
result of compensation
no-load
0
t
1/2 of line frequency
PFC output voltage
Without compensation
With compensation
0
PFC output power
Fig.14 Operation outline of compensation circuit
for light load
17
Quality is our message
FA5502P/M
9. Design advice
(1) Vcc circuit
Vcc voltage can be supplied from an auxiliary
winding of the inductor. An example circuit is shown in
Fig.15.
L
Vac
D1
(sub)
Even after PFC starts up, Vcc may fall due to step
changes of the load or inputs. To prevent the IC from
stopping in those cases, the circuit shown in Fig.17 is
effective to prolong the hold time of the Vcc voltage.
After the PFC converter starts up, Vcc is supplied
through C6. Therefore, you can prolong the hold time
of Vcc by using a large capacity for C6.
Co
R8
Q1
D3
VCC
Rs
VCC
FA5502
C5
C5
10
GND
In this circuit, R8 is a start up resistor. The start up
resistor R8 should be satisfied the following formula in
order to supply with at least 30µA of IC start up
current.
2 × Vac (min) − 17.5
30 × 10
−6
D4
C6
sub
Fig.17 Vcc circuit (2)
7
Fig.15 Vcc circuit (1)
R8 <
R8
D3
In some case, the Vcc voltage cannot be supplied
enough in light load condition. In this case, the circuit
shown in Fig.18 may be effective to improve the Vcc.
The appropriate value of C7 and R9 should be
determined by evaluation in actual circuit because
they depend on each circuit.
VCC
• • • • • (11)
Note that this formula is a minimum condition for
starting the IC. Practically, determine the value upon
taking into account the start up time required for
converter. The start up time must be determined upon
measurement at actual circuit operation.
R8
D3
C5
C7 R9
D5
sub
Fig.18 Vcc circuit (3)
(2) Supplying Vcc from external power supply
In steady state, Vcc is supplied from the auxiliary
winding (sub) of inductor. When the IC is just starting
up, however, it takes time for the voltage from auxiliary
winding to rise enough. The value of capacitor C5
connected to Vcc pin should be determined to prevent
Vcc from falling below the OFF threshold voltage of
UVLO during this period. The capacity of C5 should be
determined by evaluation in the actual circuit because
the time lag is different in each circuit.
Vcc
UVLO
ON
UVLO
OFF
Vcc must not drop
below UVLO OFF.
If Vcc is not supplied from the auxiliary winding of
inductor but from an external power supply, pay
attention to the followings.
• In order to start up the IC, Vcc must be above the ON
threshold voltage VTHUON (17.5V (max.)) of
undervoltage lockout circuit (UVLO). When starting
up, apply at least this VTHUON. After starting up,
the operation is available within the recommended
range of 10 to 28V.
• If a noise is applied to Vcc pin, it may cause
malfunction. To avoid a noise, connect a capacitor
near VCC pin even when Vcc is supplied from an
external power supply. To prevent a malfunction,
suppress the noise below about ±0.6V. And, make
sure there is no malfunction attributable to noise.
Auxiliary winding voltage
t
Fig.16 Vcc voltage at start up
18
Quality is our message
FA5502P/M
(3) Designing a boost converter
Fig.19 shows a basic circuit of boost converter used
as an PFC converter. The following describes how to
determine each values of the circuit.
Q
Vin
Co
(3-1) Output voltage
Set the output voltage of boost converter at least
10V higher than the peak value of maximum input
voltage to ensure a stable operation. When it is used
as PFC converter, the input voltage has a sinusoidal
waveform. Therefore, set the output voltage Vo by:
Vin (max) : Maximu AC input voltage [ Vrms]
Vo( t ) = Vo −
Where,
Vin: AC input voltage [Vrms]
γ: Ratio of ripple content to peak input current.
(Set to approx. 0.2, see Fig.20)
fs: Switching frequency [Hz]
Pin: Maximum input power [W]
Therefore, output ripple voltage Vrp (p-p) is:
Vrp =
Vrp
Vo
Ir
2xfac
line current
Fig.21 Output ripple voltage
t
Fig.20 Outline of inductor and AC line current
(3-3) Current detecting resistance Rs
Rs is a resistor which allows to detect an inductor
current to control the line current into sinusoidal.
Because the threshold voltage for overcurrent limiting
circuit is -1.1V (typ.), peak inductor current limit Ip is
calculated by:
Ip =
Io
• • • • • (17)
ω0 × Co
Using formula (17), determine the necessary value.
The overvoltage limiting circuit of FA5502 monitors the
instantaneous output voltage. Therefore, determine
the capacitance of smoothing capacitor Co so that the
instantaneous output voltage including the ripple at a
normal operation will not reach the overvoltage limit.
γ = Ir / Iac(peak )
Iac(peak)
Io
× sin(2ω0 × t ) • • • • • (16)
2ω0 × Co
Where,
Io: Output current [A]
ω0 = 2πf0 (f0: AC line frequency [Hz])
Co: Output smoothing capacitance [F]
• • • • • (13)
Inductor current
[Ω] • • • • • (15)
(3-4) Smoothing capacitor
PFC converter output contains ripple voltage of
twice the line frequency as shown in Fig.21.
Instantaneous value Vo(t) of output voltage is
approximated by:
• • (12)
(3-2) Inductor
When PFC converter operates in the continuous
current mode, select an approximate inductance
considering the ratio of inductor ripple current to the
peak input current by:
)
2 × Pin (max)
As a matter of fact, the peak current changes with
switching ripple current contained in the inductor
current, circuit efficiency, etc. Definitely determine it by
evaluation on a actual circuit.
Fig.19 Boost converter circuit
Vo ≥ 2 × Vin (max) + 10 [ V ]
Vin (min)
Where,
Vin (min): Minimum AC input voltage [Vrms]
Pin (max): Maximum input position [W]
Vo
Rs
(
RS ≤
D
L
Vin2 Vo − 2 × Vin
L≥
γ × fs × Pin × Vo
So that the voltage inputted to IDET pin will not be
beyond -1V, whereby the overcurrent limiting circuit
will not operate at a normal operation, calculate Rs by:
1 .1
[ A ] • • • • • (14)
RS
19
Quality is our message
FA5502P/M
(4) Output overvoltage at light load
(6) Improvement of output voltage regulation
A compensation circuit for light load is incorporated
for preventing an overvoltage when light or no load.
Though, according to the condition, this circuit may not
compensate enough and overvoltage may occur. To
prevent overvoltage, the following condition must be
satisfied.
- Noise filter resistor Rn connected to IDET pin (pin
16) must be below 27Ω.
- As shown in Fig.22, DC gain limiting resistor R10
for current error amplifier must not be connected
between IFB pin (pin 1) and IIN- pin (pin 2).
As stated in “9-(5)”, the output voltage may change
with input voltage or load current on the circuit in Fig.6
in "8-(2)", thereby causing a problem in some case. In
such a case, the circuit in Fig.24 may improve the
regulation.
Vo
R13
5
C8
R2
6
R3
R5 C2
VINMUL
C9
R1
2 IIN-
R10
VFB
Vr
=1.55V(typ.)
FA5502
1 IFB
C3
Fig.24 ER.AMP circuit for improvement of regulation
Fig.22 Prevention of overvoltage at light load
Voltage gainAv2 of this circuit is expressed by:
(5) Notes for setting the output voltage and
overvoltage limit
In the actual circuit, the output voltage drops
depending on the line voltage or load current.
Therefore, the output voltage may be lower than the
voltage calculated by expression (1) in "8-(2)". When
setting the output voltage, sufficiently evaluate it on an
actual circuit.
A V2 =
1 + jωC9 × R13
• • • (18)
jω((C8 + C9) + jωC8 × C9 × R13 )R3
Optimum values depend on an each circuit.
Referring the following relations or the example
applied to “10 Example of application circuit”, adjust
the values on actual circuit.
On the circuit shown in Fig.6 in "8-(2)", the
overvoltage setting is fixed at 1.058 times the output
voltage setting.
For setting the overvoltage independently of the
output voltage setting, connect voltage divider
additionally to OVP pin as shown in Fig.23.
- Set the voltage gain Av2 at 100 or 120 Hz almost
the same as before changing the compensation
circuit.
On the circuit in Fig.23, even if the voltage divider
for setting the output voltage has troubled, the
overvoltage limiting circuit operates properly, thereby
preventing the output voltage from rising excessively.
• Set fz determined by the following expression to
several Hz to several ten Hz.
- Determine C8, C9 and R13 so as to satisfy the
following relations.
fZ =
Vo
C1
R2
5
R4
6
• Set fp determined by the following expression so
that the fp/fz ratio is about 10.
VFB
fp =
VIN- ER.AMP
MUL
R3
Vr
=1.55V(typ.)
4
OVP OVP.COMP
F.F.
R11
Vp
=1.058Vr(typ.)
Fig.23 Independent setting of OVP limit
1
2πC × R13
C=
C8 × C9
• • • • • (20)
C8 + C9
*Example of values applied to “10 Example of
application circuit”
C8=0.033µF, C9=0.15µF,
R13=330kΩ, R3=100kΩ
(These values are given as references and not
intended for guaranteeing the operation in any
circuit.)
R1
R12
1
• • • • • (19)
2πC9 × R13
In this circuit, not only the output voltage
characteristics at a steady status but also transient
response to line voltage and load current may change.
Before determining the circuit values, evaluate
sufficiently.
20
Quality is our message
FA5502P/M
(7) Prevention of intermittent switching of low
frequency
(9) Oscillator setting and maximum duty
cycle
An intermittent switching below 10 Hz may occur in
some application. It may be avoided by the following
methods. They are given as typical preventions of
intermittent switching and may not be effective for
certain circuits. They may also affect the
characteristics of PFC converter. Sufficiently check the
operation on a actual circuit.
The maximum duty cycle is determined by forcing
the OUT pin to be Low during the oscillator discharge
period. The oscillator discharge period changes with
RT and CT connected to CT pin. On a network of CT
and RT providing the same oscillation frequency, the
discharge period shortens and the maximum duty
cycle increases by minimizing CT and maximizing RT.
(See characteristics curve.) The maximum duty cycle
may affect the input current waveform, particularly at
zero crossing. Therefore, sufficiently test CT and RT
before determining them. Too small CT could not give
a stable oscillation on account of noise, etc. It should
be 330pF or more according to the recommended
condition.
(7-1) Lowering the dc gain of voltage error amplifier
Lower the dc gain of the voltage error amplifier.
Concretely, reduce the resistance of R4 on the circuit
in Fig.6 in "8-(2)". Note that, in this case, the line and
load regulation will be lowerd.
(7-2) Connection of Rofst
Adjust the offset of the current error amplifier.
Concretely, connect a resistor Rofst of 1MΩ or higher
between REF pin and IIN- pin as shown in Fig.25.
Note that, in this case, the input current will be
distorted and the power factor will be slightly lowered.
13 REF
Rofst
FA5502
2 IIN-
R5
C2
C3
1 IFB
Fig.25 Connection of Rofst
(7-3) Change of compensation network of voltage
error amplifier
Replace the compensation network connected to the
voltage error amplifier with the circuit in Fig.24 in
"9-(6)”. Note that, in this case, the transient response
may be different from that before the change.
(8) Improvement of operation around zero
crossing
(10) Npte in use of SYNC pin
If the external synchronizing signal is not a square
waveform or if has a trapezoid shape, a differentiating
circuit of RC network may not satisfy the waveform
condition shown in Fig.3 in “8-(1)”. In such a case,
convert the external synchronizing signal into a square
waveform by means of comparator or the like before
inputting it to a differentiating circuit of RC network.
(See "8-(1) Oscillator section".)
(11) Prevention of malfunction by noise
Noise applied to each pin may cause malfunction of
IC. If noise causes malfunction, see the notes
summarized below and confirm in actual circuit to
prevent malfunction.
Capacitor for noise suppressing should be
connected as close to IC as possible so as to
suppress noise effectively.
(11-1) REF pin
REF pin voltage is supplied to each components of
IC as voltage source and reference voltage. A noise
applied to this pin may cause a malfunction of IC. To
suppress a malfunction by noise, connect a capacitor
of 0.1 µF or more between REF pin and GND.
In some application, surge current may appear on
the line current around zero crossing. This surge
current may cause harmonic current especially in high
order. In such a case, the following method may
suppress this surge current.
(11-2) IDET pin
If a noise is applied to IDET pin which detects
induvtor current, the overcurrent limiting circuit may
suffer from a malfunction. In such a case, insert an RC
filter at IDET pin.
(8-1) Connection of Rofst
As shown in Fig.25, connect resistor Rofst between
REF pin and IIN- pin. Use a resistor of about 1MΩ or
higher.
(11-3) OVP pin
If a noise applied to OVP pin causes a malfunction,
connect a noise suppressing capacitor between OVP
and GND pins.
(8-2) Increase of Dmax
Increase the maximum duty cycle. Concretely, select
such a network of RT and CT for the same frequency
that CT is a smaller and RT a larger.
(See (9) Oscillator setting and maximum duty cycle.)
(11-4) CT pin
A noise applied to CT pin, which is an oscillator
output, may disturb the oscillation frequency or OUT
pulses. The wiring between oscillator timing capacitor
CT and IC must be as short as possible so as to
suppress the noise to CT pin. Pay utmost attention to
21
Quality is our message
FA5502P/M
GND wiring so as not to generate a common
impedance with other wires.
(11-5) VCC pin
A noise applied to VCC pin may cause a malfunction.
To suppress this noise, connect a capacitor near VCC
pin even if IC is energized by another power supply.
Determine the capacitance so that the noise generated
at VCC pin will be within about ±0.6V . Then, make
sure no malfunction occurs by noise.
(13) Prevention of malfunction by negative
voltage of each pin
IDET pin is so designed as to input a negative
voltage. In the case of other pins, however, if large
negative voltage is applied, parasitic elements in IC
may operate and it may cause a malfunction. Pay
attention so that the voltage applied to pins other than
IDET pin will not be lower than -0.3V.
(12) Voltage rating of IDET pin
The voltage rating of IDET pin, which monitors an
inductor current, is -10V. In case of a general boost
circuit, a inrush current for charging the output
smoothing capacitor Co flows at the instant when an
AC input voltage is connected. This current may be by
far greater than the input current at a normal operation.
As a result, a voltage much higher than normal may be
applied to IDET pin. Pay attention so that a voltage
beyond the maximum voltage rating of -10V will not be
applied to IDET pin even at an instant when an AC
input voltage has been connected. If there are cases
where a voltage higher than rating is applied to IDET
pin, insert a limiting circuit for inrush current, or add a
Zener diode as shown in Fig.26 or 27 to suppress the
voltage applied to IDET pin.
D
L
Co
Q
ZD
Rs
7
Rn
GND
FA5502
Cn
16
IDET
Fig.26 IDET pin protection (1)
D
L
Co
Q
Rs
7
Rn
ZD
GND
Cn
16
FA5502
IDET
Fig.27 IDET pin protection (2)
22
Quality is our message
FA5502P/M
10. Example of application circuit
L1
1mH
D2-D5
ERD03-06
F1
5A
AC IN
85 - 264V
C11
0.1µF
L2
D1
YG962S6
Vout
385V
200W
R8
240k
C12
0.47µ
Rg2
4.7
R7
240k
Q1
2SK3520
C13
220µ
D6
Rs
0.22
ON/OFF
0V
ERA81-004
Rn
27
Cn
0.01µ
CT
330p
RT
C4
0.15µ
R25
100k
Vcc
18V
CREF
0.1µ
Rg1
390
22k
IDET
CT
SYNC REF ON/OFF CS
VCC
VC
FA5502
IFB
R6
C3
2.7k 470p
GND
IIN- VDET OVP
C2
68p
R5
10k
VFB
C1
0.15µ
C5
0.022µ
Cv
100µ
R9
220k
R16
270k
R2
150k
R17
240k
R1
1.5k
R18
2k
VIN- GND OUT
R4
470k
R3
33k
Note
This application circuit exemplifies the use of IC for your reference only. Parts tolerance, parts characteristics,
influence of noise, etc. are not defined in this application circuit. When design an actual circuit for a product, you must
determine parts tolerance, parts characteristics, influence of noise, etc. for safe and economical operation. Neither Fuji
nor its agents shall be liable for any injury caused by any use of this circuit.
23