FIN1108 — LVDS 8-Port, High-Speed Repeater Features Descriptions Greater than 800Mbps Data Rate This eight-port repeater is designed for high-speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. Wide Rail-to-Rail Common Mode Range Ultra-low Power Consumption 48-Lead TSSOP Package 3.3V Power Supply Operation 3.5ps Maximum Random Jitter and 135ps Maximum Deterministic Jitter LVDS Receiver Inputs Accept LVPECL, HSTL, and SSTL-2 Directly The FIN1108 accepts and outputs LVDS levels with a typical differential output swing of 330mV, which provides low EMI at ultra-low power dissipation even at high frequencies. The FIN1108 provides a VBB reference for AC coupling on the inputs. In addition, the FIN1108 can directly accept LVPECL, HSTL, and SSTL-2 for translation to LVDS. 20ps Typical Channel-to-Channel Skew Power-Off Protection 7.5kV HBM ESD Protection Meets or Exceeds the TIA/EIA-644-A LVDS Standard Open-Circuit Fail-Safe Protection VBB Reference Output Ordering Information Operating Temperature Range Package Packing Method FIN1108MTD -40 to +85°C 48-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Tube FIN1108MTDX -40 to +85°C 48-Lead, Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Part Number © 2002 Fairchild Semiconductor Corporation FIN1108 • Rev. 1.0.4 Tape and Reel www.fairchildsemi.com FIN1108 — LVDS 8-Port, High-Speed Repeater September 2010 FIN1108 — LVDS 8-Port, High-Speed Repeater Pin Configuration Figure 1. Pin Configuration Pin Definitions Pin # Name Description 1,2,23,37,36 GND Ground. 3 /EN12 Inverting driver enable for DOUT1 and DOUT2. 4,7,8,11,14,17,18,21 RIN1-,RIN2-,RIN3-,RIN5-RIN6-,RIN7-,RIN8- 5,6,9,10,15,16,19,20 RIN1+,RIN2+,RIN3+,RIN5+RIN6+,RIN7+,RIN8+ 12,25,26,47,48 VCC 13 EN 22 /EN34 24 VBB 27 /EN56 28,31,32,35,38,41,42,45 DOUT8-,DOUT7-,DOUT6-,DOUT5-DOUT4,DOUT3-,DOUT2-,DOUT1- 29,30,33,34,39,40,43,44 DOUT8+,DOUT7+,DOUT6+,DOUT5+DOUT4+, DOUT3+,DOUT2+,DOUT1+ 46 /EN78 © 2002 Fairchild Semiconductor Corporation FIN1108 • Rev. 1.0.4 Inverting LVDS input. Non-inverting LVDS input. Power supply pin. Driver enable for all outputs. Inverting driver enable for DOUT3 and DOUT4. Reference voltage output. Inverting driver enable for DOUT5 and DOUT6. Inverting drive output. Non-inverting drive output. Inverting driver enable for DOUT7 and DOUT8. www.fairchildsemi.com 2 FIN1108 — LVDS 8-Port, High-Speed Repeater Functional Diagram Figure 2. Functional Diagram Table 1. Function Table Inputs Outputs EN /ENXX DIN+ HIGH LOW HIGH LOW HIGH LOW Don’t Care HIGH Don’t Care LOW Don’t Care Don’t Care © 2002 Fairchild Semiconductor Corporation FIN1108 • Rev. 1.0.4 DIN- DOUT+ HIGH LOW HIGH LOW LOW HIGH LOW HIGH HIGH LOW Don’t Care High Impedance High Impedance Don’t Care High Impedance High Impedance Fail-Safe DOUT- www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VIN Parameter Min. Max. Unit Supply Voltage -0.5 +4.6 V LVDS DC Input Voltage -0.5 +4.6 V VOUT LVDS DC Output Voltage -0.5 +4.6 V IOSD Driver Short-Circuit Current Continuous 10 mA TSTG Storage Temperature Range +150 °C TJ Junction Temperature +150 °C TL Lead Temperature, Soldering, 10 seconds +260 °C Human Body Model, JESD22-A114 7500 Machine Model, JEDEC: JESD22-A115 400 ESD -65 V FIN1108 — LVDS 8-Port, High-Speed Repeater Absolute Maximum Ratings Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC ⏐VID⏐ Parameter Min. Max. Unit Supply Voltage 3.0 3.6 V Magnitude of Differential Voltage 100 mV to VCC V (0V + ⏐VID⏐/2) (VCC - ⏐VID⏐/2) V -40 +85 °C VIC Common Mode Voltage Range TA Operating Temperature © 2002 Fairchild Semiconductor Corporation FIN1108 • Rev. 1.0.4 www.fairchildsemi.com 4 Typical values are at TA=25°C with VCC=3.3V. Symbol Parameter Conditions Min. Typ. Max. Units 100 mV VTH Differential Input Threshold HIGH VIC=+0.05V, + 1.2V, or VCC - 0.05V Figure 3 VTL Differential Input Threshold LOW VIC=+0.05V, + 1.2V, or VCC - 0.05V Figure 3 VIH Input HIGH Voltage (EN or /EN) 2.0 VCC V VIL Input LOW Voltage (EN or /EN) GND 0.8 V VOD Output Differential Voltage 250 450 mV 25 mV 1.375 V 25 mV ΔVOD VOS ΔVOS IOS VOD Magnitude Change from Differential LOW-to-HIGH Offset Voltage RL=100Ω, Driver Enabled, Figure 4 -100 1.125 mV 330 1.230 Offset Magnitude Change from Differential LOW-to-HIGH Short-Circuit Output Current DOUT+=0V and DOUT-=0V, Driver Enabled -3.4 -6.0 mA VOD=0V, Driver Enabled ±3.4 ±6.0 mA Input Current (EN, /EN, DINx+, DINx-) VIN=0V to VCC, Other Input=VCC or 0V for Differential Input ±20 µA IOFF Power-off Input or Output Current VCC=0V, VIN or VOUT=0V to 3.6V ±20 µA ICCZ Disabled Power Supply Current Drivers Disabled 20 mA ICC Power Supply Current Drivers Enabled, Any Valid Input Condition 80 mA IOZ Disabled Output Leakage Current Driver Disabled, DOUT+=0V, to 3.6V or DOUT-=0V to 3.6V ±20 µA VIC Common Mode Voltage Range VCC(VID/2) V CIN Input Capacitance IIN COUT Output Capacitance VBB Output Reference Voltage © 2002 Fairchild Semiconductor Corporation FIN1108 • Rev. 1.0.4 VID/2 Enable Input 3 LVDS Input 3 pF 3 VCC=3.3V, IBB=0 to -275μA 1.125 1.200 FIN1108 — LVDS 8-Port, High-Speed Repeater DC Electrical Characteristics pF 1.375 V www.fairchildsemi.com 5 Typical values are at TA=25°C with VCC=3.3V. Symbol Parameter Conditions Min. Typ. Max. Units tPLHD Differential Output Propagation Delay LOW-to-HIGH 0.75 1.10 1.75 ns tPHLD Differential Output Propagation Delay HIGH-to-LOW 0.75 1.10 1.75 ns tTLHD Differential Output Rise Time (20% to 80%) 0.29 0.40 0.58 ns tTHLD Differential Output Fall Time (80% to 20%) 0.29 0.40 0.58 ns tSK(P) Pulse Skew |tPLH - tPHL| 0.02 0.20 ns tSK(LH) tSK(HL) Channel-to-Channel (1) Skew tSK(PP) Part-to-Part Skew RL=100Ω, CL=5pF VID=200mV to 450mV, VIC= VID/2 to VCC – (VID/2) Duty Cycle=50% Figure 3 0.02 0.15 0.02 0.15 (2) 0.5 (3)(4) fMAX Maximum Frequency tPZHD Differential Output Enable Time from Z to HIGH tPZLD Differential Output Enable Time from Z to LOW 400 ns ns >630 MHz 3.0 5.0 ns 3.1 5.0 ns 2.2 5.0 ns 2.5 5.0 ns FIN1108 — LVDS 8-Port, High-Speed Repeater AC Electrical Characteristics RL=100Ω, CL=5pF Figure 4, Figure 5 tPHZD Differential Output Disable Time from HIGH to Z tPLZD Differential Output Disable Time from LOW to Z tDJ LVDS Data Jitter, Deterministic VID=300mV, PRBS=2 -1, VIC=1.2V at 800Mbps 80 135 ps tRJ LVDS Clock Jitter, Random (RMS) VID=300mV VIC=1.2V at 400Mbps 1.9 3.5 ps 23 Notes: 1. tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. 2. tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. 3. Passing criteria for maximum frequency is the output VOD >250mV and the duty cycle is better than 45% / 55% with all channels switching. 4. Output loading is transmission-line environment only; CL is <1pF of stray test fixture capacitance. © 2002 Fairchild Semiconductor Corporation FIN1108 • Rev. 1.0.4 www.fairchildsemi.com 6 Figure 3. Differential Receiver Voltage Definitions Figure 4. Differential Driver DC Test Circuit FIN1108 — LVDS 8-Port, High-Speed Repeater Test Diagrams Notes: All LVDS input pulses have frequency=10MHz, tR or tF<0.5ns. CL includes all probe and jig capacitance. Figure 5. Differential Driver Propagation Delay and Transition Time Test Circuit Figure 6. AC Waveform Notes: All LVTTL input pulses have frequency=10MHz, tR or tF<2ns. CL includes all probe and jig capacitance. Figure 7. Differential Driver Enable and Disable Circuit © 2002 Fairchild Semiconductor Corporation FIN1108 • Rev. 1.0.4 Figure 8. Enable and Disable AC Waveforms www.fairchildsemi.com 7 FIN1108 — LVDS 8-Port, High-Speed Repeater Physical Dimensions Figure 9. 48-Lead, Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ © 2002 Fairchild Semiconductor Corporation FIN1108 • Rev. 1.0.4 www.fairchildsemi.com 8 FIN1108 — LVDS 8-Port, High-Speed Repeater © 2002 Fairchild Semiconductor Corporation FIN1108 • Rev. 1.0.4 www.fairchildsemi.com 9