AMI FS6377-01G

FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
1.0 Features
• One PLL and two mux/post-divider combinations can
be modified by SEL_CD input
• Tristate outputs for board testing
• 5V to 3.3V operation
• Accepts 5MHz to 27MHz crystal resonators
• Commercial (FS6377-01) and industrial (FS6377-01i)
temperature ranges
• Three on-chip PLLs with programmable reference
and feedback dividers
• Four independently programmable muxes and post
dividers
• I2C™-bus serial interface
• Programmable power-down of all PLLs and output
clock drivers
2.0 Description
The FS6377 is a CMOS clock generator IC designed to
minimize cost and component count in a variety of
electronic systems. Three I2C-programmable phase-
1
16
SCL
2
15
CLK_A
PD
3
14
VDD
VSS
4
13
CLK_B
XIN
5
12
CLK_C
XOUT
6
11
VSS
OE
7
10
CLK_D
VDD
8
9
FS6377
SDA
SEL_CD
locked loops feeding four programmable muxes and post
dividers provide a high degree of flexibility.
ADDR
16-pin (0.150") SOIC
Figure 1: Pin Configuration
XIN
XOUT
PD
Reference
Oscillator
Mux A
Post
Divider A
CLK_A
Mux B
Post
Divider B
CLK_B
Mux C
Post
Divider C
CLK_C
Mux D
Post
Divider D
CLK_D
PLL A
Power Down
Control
PLL B
SCL
SDA
ADDR
I2C-bus
Interface
PLL C
SEL_CD
OE
FS6377
Figure 2: Block Diagram
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1
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
Table 1. Pin Descriptions
Pin
Type
Name
Description
1
DIuO
SDA
Serial interface data input/output
2
DI
SEL_CD
Selects one of two PLL C, mux D/C and post divider C/D combinations
3
DIu
PD
Power-down input
4
P
VSS
Ground
5
AI
XIN
Crystal oscillator input
6
AO
XOUT
Crystal oscillator output
7
DI
OE
Output enable input
8
P
VDD
Power supply (5V to 3.3V)
9
DI
ADDR
Address select
10
DO
CLK_D
D clock output
11
P
VSS
Ground
12
DO
CLK_C
C clock output
13
DO
CLK_B
B clock output
14
P
VDD
Power supply (5V to 3.3V)
15
DO
CLK_A
A clock output
16
DIu
SCL
Serial interface clock input
u
u
u
U
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI = Input With Internal Pull-Up; DID = Input With Internal Pull-Down; DIO = Digital Input/Output;
DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
3.0 Functional Block Description
3.1 Phase Locked Loops
LFTC
Each of the three on-chip phase-locked loops (PLLs) is a
standard phase- and frequency-locked loop architecture
that multiplies a reference frequency to a desired
frequency by a ratio of integers. This frequency
multiplication is exact.
CP
fREF Reference
Divider
PhaseFrequency
Detector
(NR)
As shown in Figure 3, each PLL consists of a reference
divider, a phase-frequency detector (PFD), a charge
pump, an internal loop filter, a voltage-controlled oscillator
(VCO), and a feedback divider.
fPD
UP
Charge
Pump
DOWN
Voltage
Controlled
Oscillator
fVCO
FBKDIV[10:0]
Feedback
Divider (NF)
During operation, the reference frequency (fREF), generated
by the on-board crystal oscillator, is first reduced by the
reference divider. The divider value is called the
"modulus," and is denoted as NR for the reference divider.
The divided reference is then fed into the PFD.
Figure 3: PLL Diagram
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
frquency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference
frequency and the VCO frequency is:
The PFD controls the frequency of the VCO (fVCO) through
the charge pump and loop filter. The VCO provides a highspeed, low noise, continuously variable frequency clock
source for the PLL. The output of the VCO is fed back to
the PFD through the feedback divider (the modulus is
denoted by NF) to close the loop.
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Loop
Filter
REFDIV[7:0]
f VCO = f REF
2
( )
NF
NR
.
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
3.1.1 Reference Divider
The reference divider is designed for low phase jitter. The
divider accepts the output of the reference oscillator and
provides a divided-down frequency to the PFD. The
reference divider is an 8-bit divider, and can be
programmed for any modulus from 1 to 255 by
programming the equivalent binary value. A divide-by-256
can also be achieved by programming the eight bits to
00h.
3.1.2 Feedback Divider
The feedback divider is based on a dual-modulus prescaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the
programmable feedback divider because of the high
speeds at which the VCO can operate. The dual-modulus
technique insures reliable operation at any speed that the
VCO can achieve and reduces the overall power
consumption of the divider.
To understand the operation, refer to Figure 4. The Mcounter (with a modulus always equal to M) is cascaded
with the dual-modulus prescaler. The A-counter controls
the modulus of the prescaler. If the value programmed into
the A-counter is A, the prescaler will be set to divide by
N+1 for A prescaler outputs. Thereafter, the prescaler
divides by N until the M-counter output resets the Acounter, and the cycle begins again. Note that N=8 and A
and M are binary numbers.
Suppose that the A-counter is programmed to zero. The
modulus of the prescaler will always be fixed at N; and the
entire modulus of the feedback divider becomes MxN.
For example, a fixed divide-by-eight could be used in the
feedback divider. Unfortunately, a divide-by-eight would
limit the effective modulus of the entire feedback divider to
multiples of eight. This limitation would restrict the ability of
the PLL to achieve a desired input-frequency-to-outputfrequency ratio without making both the reference and
feedback divider values comparatively large.
Next, suppose that the A-counter is programmed to a one.
This causes the prescaler to switch to a divide-by-N+1 for
its first divide cycle and then revert to a divide-by-N. In
effect, the A-counter absorbs (or "swallows") one extra
clock during the entire cycle of the feedback divider. The
overall modulus is now seen to be equal to MxN+1.
A large feedback modulus means that the divided VCO
frequency is relatively low, requiring a wide loop bandwidth to permit the low frequencies. A narrow loop bandwidth tuned to high frequencies is essential to minimizing
jitter; therefore, divider moduli should always be as small
as possible.
fVCO
Dual
Modulus
Prescaler
M
Counter
FBKDIV[2:0]
FBKDIV[10:3]
This example can be extended to show that the feedback
divider modulus is equal to MxN+A, where A<M.
fPD
A
Counter
Figure 4: Feedback Divider
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
3.1.3 Feedback Divider Programming
For proper operation of the feedback divider, the A-counter
must be programmed only for values that are less than or
equal to the M-counter. Therefore, not all divider moduli
below 56 are available for use. The selection of divider
values is listed in Table 2.
Above a modulus of 56, the feedback divider can be
programmed to any value up to 2047.
Table 2. Feedback Divider Modulus Under 56
M-Counter:
FBKDIV[10:3]
A-Counter: FBKDIV[2:0]
000
001
010
011
100
101
110
00000001
8
9
00000010
16
17
18
00000011
24
25
26
27
00000100
32
33
34
35
36
00000101
40
41
42
43
44
45
00000110
48
49
50
51
52
53
54
00000111
56
57
58
59
60
61
62
111
63
Feedback Divider Modulus
3.2 Post Divider Muxes
As shown in Figure 2, an input mux in front of each post
divider stage can select from any one of the PLL
frequencies or the reference frequency. The frequency selection is done via the I2C-bus.
The input frequency on two of the four muxes (mux C and
D in Figure 2) can be changed without reprogramming by
a logic-level input on the SEL_CD pin.
3.3 Post Dividers
The post divider performs several useful functions. First, it
allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it changes
the basic PLL equation to
f CLK = f REF
divider moduli respectively, and fCLK and fREF are the output
and reference oscillator frequencies. The extra integer in
the denominator permits more flexibility in the
programming of the loop for many applications where
frequencies must be achieved exactly.
( )( )
NF
NR
1
NP
The modulus on two of the four post dividers muxes (post
dividers C and D in Figure 2) can be altered without
reprogramming by a logic level on the SEL_CD pin.
where NF, NR and NP are the feedback, reference and post
4.0 Device Operation
Control of the reference, feedback and post dividers is
detailed in Table 5. Selection of these dividers directly
controls how fast the VCO will run. The maximum VCO
speed is noted in Table 13.
The FS6377 powers up with all internal registers cleared to
zero, delivering the crystal frequency to all outputs. For
operation to occur, the registers must be loaded in a mostsignificant-bit (MSB) to least-significant-bit (LSB) order.
The register mapping of the FS6377 is shown in Table 3,
and I2C-bus programming information is detailed in Section
5.0.
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
4.1 SEL_CD Input
The SEL_CD pin provides a way to alter the operation of
PLL C, muxes C and D and post dividers C and D without
having to reprogram the device. A logic-low on the
SEL_CD pin selects the control bits with a "C1" or "D1"
notation, per Table 3. A logic-high on the SEL_CD pin
selects the control bits with "C2" or "D2" notation, per
Data Sheet
Table 3.
Note that changing between two running frequencies using the SEL_CD pin may produce glitches in the output,
especially if the post-divider(s) is/are altered.
4.2 Power-Down and Output Enable
A logic-high on the PD pin powers down only those
portions of the FS6377 which have their respective
powerdown control bits enabled. Note that the PD pin has
an internal pull-up.
dividers are powered down the crystal oscillator is also
powered down. The XIN pin is forced low, and the XOUT
pin is pulled high.
A logic-low on the OE pin tristates all output clocks. Note
that this pin has an internal pull-up.
When a post divider is powered down, the associated
output driver is forced low. When all PLLs and post
4.3 Oscillator Overdrive
For applications where an external reference clock is
provided (and the crystal oscillator is not required), the
reference clock should be connected to XOUT and XIN
should be left unconnected (float).
rise and fall times and can swing rail-to-rail.
If the reference clock is not a rail-to-rail signal, the reference must be AC coupled to XOUT through a 0.01mF or
0.1mF capacitor. A minimum 1V peak-to-peak signal is
required to drive the internal differential oscillator buffer.
For best results, make sure the reference clock signal is
as jitter-free as possible, can drive a 40pF load with fast
5.0 I2C-bus Control Interface
determines which mode is activated. A device that sends
data onto the bus is defined as the transmitter, and a
device receiving data as the receiver.
This device is a read/write slave device
meeting all Philips I2C-bus specifications
except a "general call." The bus has to be
controlled by a master device that generates
the serial clock SCL, controls bus access and
generates the START and STOP conditions while the
device works as a slave. Both master and slave can
operate as a transmitter or receiver, but the master device
I2C-bus logic levels noted herein are based on a
percentage of the power supply (VDD). A logic-one
corresponds to a nominal voltage of VDD, while a logic-zero
corresponds to ground (VSS).
5.1 Bus Conditions
Data transfer on the bus can only be initiated when the bus
is not busy. During the data transfer, the data line (SDA)
must remain stable whenever the clock line (SCL) is high.
Changes in the data line while the clock line is high will be
interpreted by the device as a START or STOP condition.
The following bus conditions are defined by the I2C-bus
protocol.
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
5.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL input
is high indicates a START condition. All commands to the
device must be preceded by a START condition.
5.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
5.1.4 Data Valid
The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the SDA
line must be changed only during the low period of the
SCL signal. There is one clock pulse per data bit.
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions is
determined by the master device, and can continue
indefinitely. However, data that is overwritten to the device
after the first sixteen bytes will overflow into the first
register, then the second, and so on, in a first-in, firstoverwritten fashion.
Each data transfer is initiated by a START condition and
5.1.5 Acknowledge
When addressed, the receiving device is required to
generate an acknowledge after each byte is received. The
master device must generate an extra clock pulse to
coincide with the acknowledge bit. The acknowledging
device must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to enable the master
to generate a STOP condition.
5.2 I2C-bus Operation
All programmable registers can be accessed randomly or
sequentially via this bi-directional two wire digital interface.
The device accepts the following I2C-bus commands.
5.2.1 Slave Address
After generating a START condition, the bus master
broadcasts a seven-bit slave address followed by a R/W
bit. The address of the device is:
A6
A5
A4
A3
A2
A1
A0
1
0
1
1
X
0
0
where X is controlled by the logic level at the ADDR pin.
The variable ADDR bit allows two different devices to exist
on the same bus. Note that every device on an I2C-bus
must have a unique address to avoid bus conflicts. The
default address sets A2 to one via the pull-up on the ADDR
pin.
5.2.2 Random Register Write Procedure
Random write operations allow the master to directly write
to any register. To initiate a write procedure, the R/W bit
that is transmitted after the seven-bit device address is a
logic-low. This indicates to the addressed slave device that
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a register address will follow after the slave device
acknowledges its device address. The register address is
written into the slave's address pointer. Following an
acknowledge by the slave, the master is allowed to write
6
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
If either a STOP or a repeated START condition occurs
during a register write, the data that has been transferred
is ignored.
eight bits of data into the addressed register. A final
acknowledge is returned by the device, and the master
generates a STOP condition.
5.2.3 Random Register Read Procedure
Random read operations allow the master to directly read
from any register. To perform a read procedure, the R/W
bit that is transmitted after the seven-bit address is a logiclow, as in the register write procedure. This indicates to the
addressed slave device that a register address will follow
after the slave device acknowledges its device address.
The register address is then written into the slave's
address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START
terminates the write procedure, but not until after the
slave's address pointer is set. The slave address is then
resent, with the R/W bit set this time to a logic-high,
indicating to the slave that data will be read. The slave will
acknowledge the device address, and then transmits the
eight-bit word. The master does not acknowledge the
transfer but does generate a STOP condition.
5.2.4 Sequential Register Write Procedure
Sequential write operations allow the master to write to
each register in order. The register pointer is automatically
incremented after each write. This procedure is more
efficient than the random register write if several registers
must be written.
slave, the master is allowed to write up to sixteen bytes of
data into the addressed register before the register
address pointer overflows back to the beginning address.
An acknowledge by the device between each byte of data
must occur before the next data byte is sent.
Registers are updated every time the device sends an
acknowledge to the host. The register update does not
wait for the STOP condition to occur. Registers are
therefore updated at different times during a sequential
register write.
To initiate a write procedure, the R/W bit that is transmitted
after the seven-bit device address is a logic-low. This
indicates to the addressed slave device that a register
address will follow after the slave device acknowledges its
device address. The register address is written into the
slave's address pointer. Following an acknowledge by the
5.2.5 Sequential Register Read Procedure
Sequential read operations allow the master to read from
each register in order. The register pointer is automatically
incremented by one after each read. This procedure is
more efficient than the random register read if several
registers must be read.
Following an acknowledge by the slave, the master
generates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave's address pointer is set. The slave address is
then resent, with the R/W bit set this time to a logic-high,
indicating to the slave that data will be read. The slave will
acknowledge the device address, and then transmits all
16 bytes of data starting with the initial addressed register.
The register address pointer will overflow if the initial
register address is larger than zero. After the last byte of
data, the master does not acknowledge the transfer but
does generate a STOP condition.
To perform a read procedure, the R/W bit that is
transmitted after the seven-bit address is a logic-low, as in
the register write procedure. This indicates to the
addressed slave device that a register address will follow
after the slave device acknowledges its device address.
The register address is then written into the slave's
address pointer.
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Data Sheet
7
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
S
DEVICE ADDRESS
W A
7-bit Receive
Device Address
REGISTER ADDRESS
A
Register Address
A P
Data
Acknowledge
Acknowledge
START
Command
DATA
STOP Condition
Acknowledge
WRITE Command
From bus host
to device
Data Sheet
From device
to bus host
Figure 5: Random Register Write Procedure
S
DEVICE ADDRESS
W A
7-bit Receive
Device Address
REGISTER ADDRESS
A S
DATA
A P
Data
STOP Condition
Acknowledge
Repeat START
Acknowledge
WRITE Command
From bus host
to device
R A
7-bit Receive
Device Address
Register Address
Acknowledge
START
Command
DEVICE ADDRESS
NO Acknowledge
READ Command
From device
to bus host
Figure 6: Random Register Read Procedure
S
DEVICE ADDRESS
W A
7-bit Receive
Device Address
REGISTER ADDRESS
DATA
Register Address
Acknowledge
START
Command
A
A
DATA
A
DATA
Data
Data
Acknowledge
Acknowledge
Data
Acknowledge
Acknowledge
STOP Command
WRITE Command
From bus host
to device
A P
From device
to bus host
Figure 7: Sequential Register Write Procedure
S
DEVICE ADDRESS
7-bit Receive
Device Address
W A
REGISTER ADDRESS
Register Address
Acknowledge
START
Command
WRITE Command
From bus host
to device
A S
DEVICE ADDRESS
7-bit Receive
Device Address
Repeat START
Acknowledge
R A
DATA
Acknowledge
READ Command
From device
to bus host
8
DATA
A P
Data
Data
Figure 8: Sequential Register Read Procedure
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A
Acknowledge
NO Acknowledge
STOP Command
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
6.0 Programming Information
Table 3. Register Map
ADDRESS
BYTE 15
BIT 7
BIT 6
MUX_D2[1:0]
(selected via SEL_CD = 1)
BIT 5
BIT 4
MUX_C2[1:0]
(selected via SEL_CD = 1)
BIT 3
BIT 2
PDPOST_D
PDPOST_C
BIT 1
PDPOST_B PDPOST_A
BYTE 14
POST_D2[3:0]
(selected via SEL_CD = 1)
POST_C2[3:0]
(selected via SEL_CD = 1)
BYTE 13
POST_D1[3:0]
(selected via SEL_CD = 0)
POST_C1[3:0]
(selected via SEL_CD = 0)
BYTE 12
POST_B[3:0]
POST_A[3:0]
BYTE 11
MUX_D1[1:0]
(selected via SEL_CD = 0)
Reserved (0)
MUX_C1[1:0]
(selected via SEL_CD = 0)
PDPLL_C
LFTC_C1
(SEL_CD=0)
CP_C1
(SEL_CD=0)
FBKDIV_C1[10:8] M-Counter
(selected via SEL_CD = 0)
FBKDIV_C1[2:0] A-Counter
(selected via SEL_CD = 1)
REFDIV_C1[7:0]
(selected via SEL_CD = 0)
BYTE 6
MUX_B[1:0]
BYTE 4
PDPLL_B
LFTC_B
CP_B
FBKDIV_B[7:3] M-Counter
BYTE 3
BYTE 1
FBKDIV_C2[2:0] A-Counter
(selected via SEL_CD pin = 1)
FBKDIV_C1[7:3] M-Counter
(selected via SEL_CD = 0)
BYTE 7
BYTE 2
FBKDIV_D2[10:8] M-Counter
(selected via SEL_CD pin = 1)
REFDIV_C2[7:0]
(selected via SEL_CD pin = 1)
BYTE 9
BYTE 5
CP_C2
(SEL_CD=1)
FBKDIV_C2[7:3] M-Counter
(selected via SEL_CD pin = 1)
BYTE 10
BYTE 8
LFTC_C2
(SEL_CD=1)
BIT 0
FBKDIV_B[10:8] M-Counter
FBKDIV_B[2:0] A-Counter
REFDIV_B[7:0]
MUX_A[1:0]
PDPLL_A
LFTC_A
CP_A
FBKDIV_A[7:3] M-Counter
BYTE 0
FBKDIV_A[10:8] M-Counter
FBKDIV_A[2:0] A-Counter
REFDIV_A[7:0]
(Note: All register bits are cleared to zero on power-up)
6.1 Control Bit Assignment
If any PLL control bit is altered during device operation,
including those bits controlling the reference and feedback
dividers, the output frequency will slew smoothly (in a
glitch-free manner) to the new frequency. The slew rate is
related to the programmed loop filter time constant.
However, any programming changes to any mux or post
divider control bits will cause a glitch on an operating clock
output.
6.1.1 Power Down
All power-down functions are controlled by enable bits.
The bits select which portions of the device to power-down
when the PD input is asserted.
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Table 4. Power-Down Bits
Table 5. Divider Control Bits
Name
Name
Description
REFDIV_A[7:0]
(Bits 7-0)
REFDIV_B[7:0]
(Bits 31-24)
Reference Divider A (NR)
PDPLL_A
(Bit 21)
PDPLL_B
(Bit 45)
PDPLL_C
(Bit 69)
Reserved (0)
(Bit 69)
PDPOSTA
(Bit 120)
PDPOSTB
(Bit 121)
PDPOSTC
(Bit 122)
PDPOSTD
(Bit 123)
Description
Power-Down PLL A
Bit = 0
Power on
Bit = 1
Power off
Power-Down PLL B
Bit = 0
Power on
Bit = 1
Power off
Power-Down PLL C
Bit = 0
Power on
Bit = 1
Power off
REFDIV_C1[7:0]
(Bits 55-48)
REFDIV_C2[7:0]
(Bits 79-72)
FBKDIV_A[10:0]
(Bits 18-8)
POST divider A
Power on
Power off
POST divider B
Power on
Power off
POST divider C
Power on
Power off
POST divider D
Power on
Power off
FBKDIV_B[10:0]
(Bits 42-32)
POST_A[3:0]
(Bits 99-96)
POST divider A (see Table 7)
POST_B[3:0]
(Bits 103-100)
POST divider B (see Table 7)
POST_C1[3:0]
(Bits 107-104)
POST divider C1 (see Table 7)
selected when the SEL_CD pin = 0
POST_C2[3:0]
(Bits 115-112)
POST divider C2 (see Table 7)
selected when the SEL_CD pin = 1
POST_D1[3:0]
(Bits 111-108)
POST divider D1 (see Table 7)
selected when the SEL_CD pin = 0
POST_D2[3:0]
(Bits 119-116)
POST divider D2 (see Table 7)
selected when the SEL_CD pin = 1
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FBKDIV_A[2:0]
A-Counter value
FBKDIV_A[10:3]
M-Counter value
FBKDIV_B[2:0]
A-Counter value
FBKDIV_B[10:3]
M-Counter value
Feedback Divider C1 (NF)
selected when the SEL-CD pin = 0
FBKDIV_C1[10:0]
(Bits 66-56)
FBKDIV_C1[2:0]
A-Counter value
FBKDIV_C1[10:3]
M-Counter value
Feedback DividerC2 (NF)
selected when the SEL-CD pin = 1
Table 6. Divider Control Bits
Description
Reference Divider C1 (NR)
selected when the SEL-CD pin = 0
Reference Divider C2 (NR)
selected when the SEL-CD pin = 1
Feedback Divider B (NF)
FBKDIV_C2[10:0]
(Bits 90-80)
Name
Reference Divider B (NR)
Feedback Divider A (NF)
Set these reserved bits to zero (0)
Power-Down
Bit = 0
Bit = 1
Power-Down
Bit = 0
Bit = 1
Power-Down
Bit = 0
Bit = 1
Power-Down
Bit = 0
Bit = 1
Data Sheet
FBKDIV_C2[2:0]
A-Counter value
FBKDIV_C2[10:3]
M-Counter value
Table 7. Post Divider Modulus
BIT [3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
10
BIT [2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
BIT [1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BIT [0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DIVIDE BY
1
2
3
4
5
6
8
9
10
12
15
16
18
20
25
50
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Table 8. PLL Tuning Bits
Table 9. Mux Select Bits
Name
Name
Description
Loop Filter Time Constant A
LFTC_A
(Bit 20)
Bit = 0
Short time constant: 7ms
Bit = 1
Long time constant: 20ms
LFTC_C1
(Bit 68)
Bit = 0
MUX_A[1:0]
(Bits 23-22)
Short time constant: 7ms
Long time constant: 20ms
Bit = 1
Loop Filter Time Constant C1
selected when the SEL_CD pin = 0
Short time constant: 7ms
Bit = 0
Bit = 1
Long time constant: 20ms
MUX_B[1:0]
(Bits 47-46)
Reference frequency
1
PLL A frequency
1
0
PLL B frequency
1
1
PLL C frequency
Bit 47
Bit 46
0
0
Reference frequency
0
1
PLL A frequency
1
0
PLL B frequency
Long time constant: 20ms
1
1
PLL C frequency
Bit = 0
Current = 2mA
Bit = 1
Current = 10mA
MUX C1 Frequency Select
selected when the SEL_CD pin = 0
Bit = 0
Current = 2mA
Bit = 1
Current = 10mA
MUX_C1[1:0]
(Bits 71-70)
Bit = 0
Current = 2mA
Bit = 1
Current = 10mA
Bit = 0
Current = 2mA
Bit = 1
Current = 10mA
Bit 71
Bit 70
0
0
Reference frequency
0
1
PLL A frequency
1
0
PLL B frequency
1
1
PLL C frequency
MUX C2 Frequency Select
selected when the SEL_CD pin = 1
Charge Pump C2
selected when the SEL_CD pin = 1
CP_C2
(Bit 91)
0
0
Short time constant: 7ms
Charge Pump C1
selected when the SEL_CD pin = 0
CP_C1
(Bit 67)
0
Bit = 1
Charge Pump B
CP_B
(Bit 43)
Bit 22
Bit = 0
Charge Pump A
CP_A
(Bit 19)
Bit 23
MUX B Frequency Select
Loop Filter Time Constant C2
selected when the SEL_CD pin = 1
LFTC_C2
(Bit 92)
Description
MUX A Frequency Select
Loop Filter Time Constant B
LFTC_B
(Bit 44)
Data Sheet
MUX_C2[1:0]
(Bits 125-124)
Bit 125
Bit 124
0
0
Reference frequency
0
1
PLL A frequency
1
0
PLL B frequency
1
1
PLL C frequency
MUX D1 Frequency Select
selected when the SEL_CD pin = 0
MUX_D1[1:0]
(Bits 95-94)
Bit 95
Bit 94
0
0
Reference frequency
0
1
PLL A frequency
1
0
PLL B frequency
1
1
PLL C frequency
MUX D2 Frequency Select
selected when the SEL_CD pin = 1
MUX_D2[1:0]
(Bits 127-126)
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Bit 127
Bit 126
0
0
Reference frequency
0
1
PLL A frequency
1
0
PLL B frequency
1
1
PLL C frequency
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
7.0 Electrical Specifications
Table 10. Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Supply Voltage, dc (VSS = ground)
VDD
VSS-0.5
7
V
Input Voltage, dc
V1
VSS-0.5
VDD+0.5
V
Output Voltage, dc
V
V -0.5
V +0.5
V
Input Clamp Current, dc (VI < 0 or VI > VDD)
IIK
-50
50
mA
Output Clamp Current, dc (VI < 0 or VI > VDD)
IOK
-50
50
mA
Storage Temperature Range (non-condensing)
TS
-65
150
°C
Ambient Temperature Range, Under Bias
TA
-55
125
°C
Junction Temperature
TJ
O
SS
DD
150
°C
Per IPC/JEDEC
J-STD-020B
Reflow Solder Profile
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
2
kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the
device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect
device performance, functionality and reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a
high-energy electrostatic discharge.
Table 11. Operating Conditions
Parameter
Symbol
Supply Voltage
VDD
Ambient Operating Temperature Range
TA
Crystal Resonator Frequency
fXIN
Crystal Resonator Load Capacitance
CXL
Serial Data Transfer Rate
Output Driver Load Capacitance
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Conditions/Description
Min.
Typ.
Max.
4.5
5
5.5
3.3V ± 10%
3
3.3
3.6
Commercial
0
70
-40
85
5
27
MHz
100
kb/s
15
pF
5V ± 10%
Industrial
Parallel resonant, AT cut
Standard mode
CL
12
18
10
Units
V
°C
pF
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
Table 12. DC Electrical Specifications
Parameter
Symbol
Conditions/Description
Overall
Supply Current, Dynamic, With
Loaded Outputs
Supply Current, Static
IDD
VDD = 5.5V, fCLK = 50MHz, CL = 15pF
See Figure 10 for more information
43
mA
VDD = 5.5V, device powered down
0.3
mA
IDDL
Power-Down, Output Enable Pins (PD, OE)
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
Hysteresis Voltage
Vhys
High-Level Input Current
IIH
Low-Level Input Current (pull-up)
IIL
Min.
Typ.
Max.
VDD = 5.5V
3.85
VDD+0.3
VDD = 3.6V
2.52
VDD = 5.5V
VSS-0.3
VDD+0.3
1.65
VDD = 3.6V
VSS-0.3
1.08
VDD = 5.5V
2.20
VDD = 3.6V
1.44
-1
-36
Units
V
V
V
1
mA
-80
mA
VIL = 0V
-20
VDD = 5.5V
3.85
VDD+0.3
VDD = 3.6V
2.52
VDD = 5.5V
VSS-0.3
VDD+0.3
1.65
VDD = 3.6V
VSS-0.3
1.08
Serial Interface I/O (SCL, SDA)
High-Level Input Voltage
VIH
Low-Level Input Voltage
VIL
Hysteresis Voltage
Vhys
High-Level Input Current
IIH
Low-Level Input Current (pull-up)
IIL
VDD = 5.5V
2.20
VDD = 3.6V
1.44
-1
-20
VIL = 0V
Low-Level Output Sink Current (SDA)
-80
26
IOL
VOL = 0.4V, VDD = 5.5V
Mode and Frequency Select Inputs (ADDR, SEL_CD)
2.4
VDD+0.3
VDD = 3.6V
2.0
VDD = 5.5V
VSS-0.3
VDD+0.3
0.8
VDD = 3.6V
IIH
VSS-0.3
-1
IIL
-20
VIH
Low-Level Input Voltage
VIL
High-Level Input Current
Low-Level Input Current (pull-up)
0.8
-36
mA
mA
mA
VDD = 5.5V
High-Level Input Voltage
V
V
1
-36
V
V
V
1
mA
-80
mA
Crystal Oscillator Feedback (XIN)
VDD = 5.5V
2.9
VDD = 3.6V
1.7
Threshold Bias Voltage
VTH
High-Level Input Current
IIH
Low-Level Input Current
IIL
VDD = 5.5V
Crystal Loading Capacitance*
CL(xtal)
As seen by an external crystal connected to XIN and XOUT
18
pF
Input Loading Capacitance*
CL(XIN)
As seen by an external clock driver on XOUT; XIN unconnected
36
pF
IOH
VDD = V(XIN) = 5.5V, VO = 0V
10
21
30
mA
VDD = 5.5V, V(XIN) = 0V, VO = 5.5V
-10
-21
-30
mA
mA
54
VDD = 5.5V
VDD = 5.5V, oscillator powered down
V
5
-25
-54
15
mA
-75
mA
Crystal Oscillator Drive (XOUT)
High-Level Output Source Current
Low-Level Output Sink Current
IOL
Clock Outputs (CLK_A, CLK_B, CLK_C, CLK_D)
High-Level Output Source Current
Low-Level Output Sink Current
Output Impedance
VO = 2.4V
-125
mA
IOL
VO = 0.4V
23
mA
ZOH
VO = 0.5VDD; output driving high
29
ZOL
VO = 0.5VDD; output driving low
27
IOH
W
mA
Tristate Output Current
IZ
Short Circuit Source Current*
ISCH
VDD = 5.5V, VO = 0V; shorted for 30s, max.
-150
mA
Short Circuit Sink Current*
ISCL
VDD = VO = 5.5V, shorted for 30s, max.
123
mA
-10
10
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3s from typical. Negative currents indicate current flows out of
the device.
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13
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Voltage Low Drive Current (mA) Voltage High Drive Current (mA)
(V)
(V)
Min.
Typ.
Max.
Min.
Typ.
Max.
0
0
0
0
-87
-112
-150
0.2
9
11
12
0.5
-85
-110
-147
0.5
22
25
29
1
-83
-108
-144
0.7
29
34
40
1.5
-80
-104
-139
1
39
46
55
2
-74
-97
-131
1.2
44
52
64
2.5
-65
-88
-121
1.5
51
61
76
2.7
-61
-84
-116
1.7
55
66
83
3
-53
-77
-108
2
60
73
92
3.2
-48
-71
-102
2.2
62
77
97
3.5
-39
-62
-92
2.5
65
81
104
3.7
-32
-55
-85
2.7
65
83
108
4
-21
-44
-74
3
66
85
112
4.2
-13
-36
-65
3.5
67
87
117
4.5
0
-24
-52
4
68
88
119
4.7
-15
-43
4.5
69
89
120
5
0
-28
91
121
5.2
-11
123
5.5
0
5
5.5
150
100
50
Output Current (mA)
0
0
-
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
-50
-100
-150
MIN
14
TYP
-200
Output Voltage (V)
MAX
The data in this table represents nominal charaterization data only.
Figure 9: CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs
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Data Sheet
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
110
All outputs at the same frequency
100
All outputs at the same
frequency, CL = OpF
Dynamic Current (mA)
90
80
70
All outputs at 200MHz
except output under test
60
All outputs at 4MHz
except output under test
50
All outputs off except output under test
40
30
20
All outputs off except output under test, CL = OpF
10
0
0
10
20
30
40
50
60
70
80
90 100 110 120 130 140 150 160 170 180 190 200
Output Frequency (MHz)
VDD = 5.0V; Reference Frequency = 27.00MHz; VCO Frequency = 200MHz, CL = 17pF except where noted
45
All outputs at the same frequency
40
Dynamic Current (mA)
35
All outputs at the same
frequency, CL = OpF
30
25
All outputs at 100MHz
except output under test
All outputs at 2MHz
except output under test
20
15
All outputs off except
output under test
10
All outputs off except output under test, CL = OpF
5
0
0
10
20
30
40
50
60
70
80
90
Output Frequency (MHz)
VDD = 3.3V; Reference Frequency = 27.00MHz; VCO Frequency = 100MHz, CL = 17pF except where noted
Figure 10: Dynamic Current vs. Output Frequency
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100
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
Table 13. AC Timing Specifications
Parameter
Symbol
Conditions/Description
Clock
(MHz)
Min.
Typ.
Max.
Units
Overall
Output Frequency*
fO
VCO Frequency*
fVCO
VCO Gain*
AVCO
Loop Filter Time Constant*
Rise Time*
tr
Fall Time*
tr
Tristate Enable Delay*
tPZL, tPZH
Tristate Disable Delay*
tPZL, tPZH
Clock Stabilization Time*
tSTB
VDD = 5.5V
0.8
150
VDD = 3.6V
0.8
100
VDD = 5.5V
40
230
VDD = 3.6V
40
170
400
LFTC bit = 0
7
LFTC bit = 1
20
VO = 0.5V to 4.5V; CL = 15pF
1.9
VO = 0.3V to 3.0V; CL = 15pF
1.6
VO = 4.5V to 0.5V; CL = 15pF
1.8
VO = 3.0V to 0.3V; CL = 15pF
1.5
1
MHz
MHz/V
ms
ns
ns
8
1
Output active from power-up, via PD pin
MHz
8
ns
ms
100
After last register is written
ns
1
ms
Divider Modulus
Feedback Divider
NF
Reference Divider
NR
Post Divider
NP
See also Table 2
See also Table 8
8
2047
1
255
1
50
45
55
Clock Outputs (PLL A clock via CLK_A pin)
Ratio of pulse width (as measured from rising edge to
next falling edge at 2.5V) to one clock period
On rising edges 500ms apart at 2.5V relative to an
ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,
NPX=50, no other PLLs active
Duty Cycle*
Jitter, Long Term (sy(t))*
Jitter, Period (peak-peak)*
tj(LT)
tj(DP)
100
100
45
On rising edges 500ms apart at 2.5V relative to an
ideal clock, CL=15pF, fXIN=14.318MHz, NF=220, NR=63,
NPX=50, all other PLLs active (B=60MHz, C=40MHz,
D=14.318MHz)
50
165
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, no
other PLLs active
100
110
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPX=50, all
other PLLs active (B=60MHz, C=40MHz,
D=14.318MHz)
50
390
ps
ps
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3s from typical.
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
Table 13. AC Timing Specifications, Continued
Parameter
Symbol
Clock
(MHz)
Min.
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
100
45
On rising edges 500ms apart at 2.5V relative to an
ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPx=50, no other PLLs active
100
45
On rising edges 500ms apart at 2.5V relative to an
ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPx=50, all other PLLs active (A=50MHz,
C=40MHz, D=14.318MHz)
60
75
100
120
60
400
Conditions/Description
Typ.
Max.
Units
55
%
Clock Outputs (PLL B clock via CLK_B pin)
Duty Cycle*
Jitter, Long Term (sy(t))*
Jitter, Period (peak-peak)*
tj(LT)
tj(DP)
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,
no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,
all other PLLs active (A=50MHz, C=40MHz,
D=14.318MHz)
ps
ps
Clock Outputs (PLL_C clock via CLK_C pin)
Duty Cycle*
Jitter, Long Term (sy(t))*
Jitter, Period (peak-peak)*
tj(LT)
tj(DP)
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
100
On rising edges 500ms apart at 2.5V relative to an
ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPx=50, no other PLLs active
100
45
40
105
100
120
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,
all other PLLs active (A=50MHz, B=60MHz,
D=14.318MHz)
40
440
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
14.318
On rising edges 500ms apart at 2.5V relative to an
ideal clock, CL=15pF, fXIN=14.318MHz, NF=220,
NR=63, NPx=50, all other PLLs active (A=50MHz,
B=60MHz, D=14.318MHz)
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, NF=220, NR=63, NPx=50,
no other PLLs active
45
55
%
ps
ps
Clock Outputs (Crystal Oscillator via CLK_D pin)
Duty Cycle*
Jitter, Long Term (sy(t))*
Jitter, Period (peak-peak)*
tj(LT
tj(DP)
On rising edges 500ms apart at 2.5V relative to an
ideal clock, CL=15pF, fXIN=14.318MHz, no other
PLLs active
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, all other PLLs active
(A=50MHz, B=60MHz, C=40MHz)
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, no other PLLs active
From rising edge to the next rising edge at 2.5V,
CL=15pF, fXIN=14.318MHz, all other PLLs active
(A=50MHz, B=60MHz, C=40MHz)
45
55
14.318
20
14.318
40
14.318
90
14.318
450
ps
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3s from typical.
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%
ps
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
Table 14. Serial Interface Timing Specifications
Parameter
Symbol
Conditions/Description
Clock Frequency
fSCL
SCL
Standard Mode
Bus Free Time Between STOP and START tBUF
Min.
Max.
0
100
Units
kHz
4.7
ms
Set-up Time, START (repeated)
tsu:STA
4.7
ms
Hold Time, START
tnd:STA
4.0
ms
Set-up Time, Data Input
tsu:DAT
SDA
250
ns
Hold Time, Data Input
thd:DAT
SDA
0
ms
Output Data Valid From Clock
tAA
Minimum delay to bridge undefined region of the falling edge of
SCL to avoid unintended START or STOP
3.5
ms
Rise Time, Data and Clock
tR
SDA, SCL
1000
ns
Fall Time, Data and Clock
tF
SDA, SCL
300
ns
High Time, Clock
tHI
SCL
4.0
ms
Low Time, Clock
tLO
SCL
4.7
ms
Set-up Time, STOP
tsu:STO
4.0
ms
Unless otherwise stated, all power supplies = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent
nominal characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3s from typical.
~
~
SCL
~
~
thd:STA
tsu:STA
tsu:STO
SDA
DATA CAN
CHANGE
~
~
ADDRESS OR
DATA VALID
START
STOP
Figure 11: Bus Timing Data
tHI
SCL
tR
~
~
tF
tLO
tsu:STA
thd:STA
tsu:DAT
tAA
tAA
SDA
OUT
Figure 12: Data Transfer Sequence
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~
~
SDA
IN
tsu:STO
~
~
thd:DAT
tBUF
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
8.0 Package Information - For Both ‘Green’ and ‘Non-Green’
Table 15. 16-pin SOIC (0.150”) Package Dimensions
Dimensions
Inches
Millimeters
Min.
Max.
Min.
Max.
A
0.061
0.068
1.55
1.73
A1
0.004
0.0098
0.102
0.249
A2
0.055
0.061
1.40
1.55
B
0.013
0.019
0.33
0.49
C
0.0075
0.0098
0.191
0.249
D
0.386
0.393
9.80
9.98
E
0.150
0.157
3.81
3.99
e
0.050 BSC
1.27 BSC
H
0.230
0.244
5.84
6.20
h
0.010
0.016
0.25
0.41
L
0.016
0.035
0.41
0.89
Q
0°
8°
0°
8°
Table 16. 16-pin SOIC (0.150”) Package Characteristics
Parameter
Symbol
Conditions/Description
Typ.
Units
Thermal Impedance, Junction to Free-Air
16-pin 0.150" SOIC
QJA
Air flow = 0 m/s
110
°C/W
Lead Inductance, Self
L11
Corner lead
4.0
Center lead
3.0
Lead Inductance, Mutual
L12
Any lead to any adjacent lead
0.4
nH
Lead Capacitance, Bulk
C11
Any lead to VSS
0.5
pF
nH
9.0 Ordering Information
9.1 Device Ordering Codes
Ordering Code
Device Number
Package Type
Operating
Temperature Range
Shipping
Configuration
11486-801
FS6377-01
16-pin (0.150") SOIC
(Small Outline Package)
0°C to 70°C (Commercial)
Tape-and-Reel
11486-912
FS6377-01g
16-pin (0.150") SOIC
0°C to 70°C (Commercial)
(Small Outline Package)
'Green' or lead-free packaging
Tape-and-Reel
11486-901
FS6377-01i
16-pin (0.150") SOIC
(Small Outline Package)
Tape-and-Reel
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-40°C to 85°C (Industrial)
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Data Sheet
10.0 Demonstration Software
Windows 3.1x/95/98-based software is available from AMI
Semiconductor that illustrates the capabilities of the
FS6377. The software can operate under Windows NT.
Contact your local sales representative or the company
directly for more information.
10.1 Software Requirements
· PC running MS Windows 3.1x or 95/98. Software
runs on Windows NT in a calculation mode only.
· 1.8MB available space on hard drive C
10.2 Software Installation Instructions
At the appropriate disk drive prompt (A:\) unzip the
compressed demo files to a directory of your choice. Run
setup.exe to install the software.
10.3 Demo Program Operation
just the calculation features of this program?" Clicking OK
starts the program for calculation only.
Launch the fs6377.exe program. Note that the parallel port
can not be accessed if your machine is running Windows
NT. A warning message will appear stating: "This version
of the demo program cannot communicate with the
FS6377 hardware when running on a Windows NT
operating system. Do you want to continue anyway, using
FS6377 demo hardware is no longer supported.
The opening screen is shown in Figure 13.
Figure 13: Opening Screen
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FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
10.3.1 Example Programming
Data Sheet
and mux D are also affected by the logic level on the
SEL_CD pin, as are the post dividers C and D.
Type a value for the crystal resonator frequency in MHz in
the reference crystal box. This frequency provides the
basis for all of the PLL calculations that follow.
Next, click on the PLL A box. A pop-up screen similar to
Figure 14 should appear. Type in a desired output clock
frequency in MHz, set the operating voltage (3.3V or 5V)
and the desired maximum output frequency error.
Figure 15:
Post Divider Menu
Click on PLL C1 to open the PLL screen. Set a desired
frequency, however, now choose the post divider B as the
output divider. Notice the post divider box has split in two
(as shown in Figure 15). The post divider B box now
shows that the divider is dependent on the setting of the
SEL_CD pin for as long as mux B is the PLL C output.
Figure 14: PLL Screen
Pressing calculate solutions generates several possible
divider and VCO-speed combinations.
For a 100MHz output, the VCO should ideally operate at a
higher frequency, and the reference and feedback dividers
should be as small as possible. In this example, highlight
Solution #7. Notice the VCO operates at 200MHz with a
post divider of two to obtain an optimal 50 percent duty
cycle.
Clicking on post divider A reveals a pull-down menu
provided to permit adjustment of the post divider value
independently of the PLL screen. A typical menu is shown
in Figure 15. The range of possible post divider values is
also given in Table 7.
Now choose which mux and post divider to use (that is,
choose an output pin for the 100MHz output). Selecting A
places the PostDiv value in Solution #7 into post divider A
and switches mux A to take the output of PLL A.
The register settings are shown to the left in the screen
shown in Figure 13. Clicking on a register location
displays a screen shown in Figure 16. Individual bits can
be poked, or the entire register value can be changed.
The PLL screen should disappear, and now the value in
the PLL A box is the new VCO frequency chosen in
Solution #7. Also note that mux A has been switched to
PLL A and the post pivider A has the chosen 100MHz
output displayed.
Repeat the steps for PLL B.
PLL C supports two different output frequencies
depending on the setting of the SEL_CD pin. Both mux C
Figure 16: Register Screen
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© 2004 AMI Semiconductor, Inc.
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