FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet 1.0 Features 2.0 Description • Extremely flexible and low-jitter phase-locked loop (PLL) frequency synthesis • No external loop filter components needed • 150MHz CMOS or 340MHz PECL outputs • Completely configurable via I2C™-bus • Up to four FS7140 or FS7145 can be used on a single I2C-bus • 3.3V operation • Independent on-chip crystal oscillator and external reference input • Very low "cumulative" jitter The FS7140 / FS7145 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of electronic systems. Via the I2Cbus interface, the FS714x can be adapted to many clock generation requirements. The length of the reference and feedback dividers, their fine granularity, and the flexibility of the post divider make the FS714x the most flexible stand-alone phase-locked loop (PLL) clock generator available. 3.0 Applications 16 CLKN SCL 1 16 CLKN 2 15 CLKP SDA 2 15 CLKP ADDR0 3 14 VDD ADDR0 3 14 VDD VSS 4 13 n/c VSS 4 13 SYNC XIN 5 12 REF XIN 5 12 REF XOUT 6 11 VSS XOUT 6 11 VSS ADDR1 7 10 n/c ADDR1 7 10 n/c VDD 8 9 IPRG VDD 8 9 IPRG FS7145 1 FS7140 SCL SDA • • • • Precision frequency synthesis Low-frequency clock multiplication Video line-locked clock generation Laser beam printers (FS7145) Figure 1: Pin Configuration: 16-pin (0.150”) SOIC, 16-pin (5.3mm) SSOP Sync Control SYNC (FS7145 only) IPRG XIN XOUT Loop Filter Crystal Oscillator Reference Divider REF (NR) SDA UP Charge Pump DOWN Voltage Controlled Oscillator CLKP Post Divider (NPx) CLKN CMOS/PECL Output ADDR[1:0] SCL PhaseFrequency Detector Feedback Divider (NF) I2C Interface Registers FS7140 / FS7145 Figure 2: Device Block Diagram AMI Semiconductor - Rev. 3.0 www.amis.com 1 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Table 1: FS7140 Pin Descriptions Pin Type Name Description 1 DI SCL 2 SDA 3 DIO DID Serial Interface Clock (requires an external pull-up) ADDR0 4 P VSS Ground Crystal Oscillator Feedback Serial Interface Data Input/Output (requires an external pull-up) Address Select Bit "0" 5 AI XIN 6 AO DID XOUT Crystal Oscillator Drive ADDR1 Address Select Bit "1" 7 8 P VDD Power Supply (+3.3V nominal) 9 AI IPRG PECL Current Drive Programming 10 - n/c 11 P VSS No Connection 12 DIU REF 13 - n/c Ground Reference Frequency Input No Connection 14 P VDD Power Supply (+3.3V nominal) 15 DO CLKP Clock Output 16 DO CLKN Inverted Clock Output Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; U DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin Table 2: FS7145 Pin Descriptions Pin Type Name 1 DI SCL 2 DIO DID ADDR0 4 P VSS Ground 5 AI XIN Crystal Oscillator Feedback 6 AO DID XOUT Crystal Oscillator Drive ADDR1 Address Select Bit "1" 3 7 Description Serial Interface Clock (requires an external pull-up) SDA Serial Interface Data Input/Output (requires an external pull-up) Address Select Bit "0" 8 P VDD Power Supply (+3.3V nominal) 9 AI IPRG PECL Current Drive Programming 10 - n/c 11 P VSS No Connection 12 DIU REF 13 DIU SYNC Ground Reference Frequency Input Synchronization Input 14 P VDD Power Supply (+3.3V nominal) 15 DO CLKP Clock Output 16 DO CLKN Inverted Clock Output Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DI = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; U DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin AMI Semiconductor - Rev. 3.0 www.amis.com 2 Data Sheet FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator 4.0 Functional Block Description modulus. Selected moduli below 12 are also permitted. Moduli of: 4, 5, 8, 9, and 10 are also allowed (4 and 5 are not available on date codes prior to 0108). 4.1 Phase Locked Loop (PLL) The phase locked loop is a standard phase- and frequencylocked loop architecture. The PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled oscillator (VCO), a feedback divider, and a post divider. 4.1.3 Post Divider The post divider consists of three individually programmable dividers, as shown in Figure 3. The reference frequency (generated by either the on-board crystal oscillator or an external frequency source), is first reduced by the Reference Divider. The integer value that the frequency is divided by is called the modulus and is denoted as NR for the reference divider. This divided reference is then fed into the PFD. f VCO POST1[3:0] POST2[3:0] POST3[1:0] Post Divider 1 (N P1 ) Post Divider 2 (N P2) Post Divider 3 (N P3) POST DIVIDER (N The VCO frequency is fed back to the PFD through the feedback divider (the modulus is denoted by NF). N Px = N P1 ´ N P 2 ´ N P 3 The post divider performs several useful functions. First, it allows the VCO to be operated in a narrower range of speeds compared to the variety of output clock speeds that the device is required to generate. Second, the extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly. This basic PLL equation can be rewritten as ö ÷÷ ø A post-divider (actually a series combination of three post dividers) follows the PLL and the final equation for device output frequency is: f CLK öæ 1 ÷÷çç øè N Px Note that a nominal 50/50 duty factor is always preserved (even for selections which have an odd modulus). See Table 8 for additional information. ö ÷÷ ø 4.1.4 Crystal Oscillator The FS7140 is equipped with a Pierce-type crystal oscillator. The crystal is operated in parallel resonant mode. Internal load capacitance is provided for the crystal. While a recommended load capacitance for the crystal is specified, crystals for other standard load capacitances may be used if great precision of the reference frequency (100ppm or less) is not required. 4.1.1 Reference Divider The reference divider is designed for low phase jitter. The divider accepts the output of either the crystal oscillator circuit or an external reference frequency. The reference divider is a 12 bit divider, and can be programmed for any modulus from 1 to 4095 (divide by 1 not available on date codes prior to 0108). 4.1.5 Reference Divider Source MUX 4.1.2 Feedback Divider The source of frequency for the reference divider can be chosen to be the device crystal oscillator or the REF pin by the REFDSRC bit. The feedback divider is based on a dual-modulus divider (also called dual-modulus prescaler) technique. It permits division by any integer value between 12 and 16383. Simply program the FBKDIV register with the binary equivalent of the desired AMI Semiconductor - Rev. 3.0 www.amis.com ) Px The moduli of the individual dividers are denoted as NP1, NP2 and NP3, and together they make up the array modulus NPx. fVCO f = REF NF NR æN = f REF çç F è NR fCLK Figure 3: Post Divider The PFD will drive the VCO up or down in frequency until the divided reference frequency and the divided VCO frequency appearing at the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is then: æN fVCO = f REF çç F è NR Data Sheet When not using the crystal oscillator, it is preferred to connect 3 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator XIN to VSS. Do not connect to XOUT. Then: When not using the REF input, it is preferred to leave it floating or connected to VDD. R1 (from CLKP and CLKN output to VDD) = RLOAD * VDD / VHI = 75 * 3.3 / 2.4 = 103 ohms 4.1.6 Feedback Divider Source MUX The source of frequency for the feedback divider may be selected to be either the output of the post divider or the output of the VCO by the FBKDSRC bit. R2 (from CLKP and CLKN output to GND) = RLOAD * VDD / (VDD - VHI) = 75 * 3.3 / (3.3 - 2.4) = 275 ohms Ordinarily, for frequency synthesis, the output of the VCO is used. Use the output of the post divider only where a deterministic phase relationship between the output clock and reference clock are desired (line-locked mode, for example). Rprgm (from VDD to IPRG pin) = 26 * (VDD * RLOAD) / (VHI - VLO) / 3 = 26 * (3.3 * 75) / (2.4 - 1.6) / 3 = 2.68 Kohms 4.1.7 Device Shutdown Two bits are provided to effect shutdown of the device if desired, when it is not active. SHUT1 disables most externally observable device functions. SHUT2 reduces device quiescent current to absolute minimum values. Normally, both bits should be set or cleared together. 4.3 SYNC Circuitry The FS7145 supports nearly instantaneous adjustment of the output CLK phase by the SYNC input. Either edge direction of SYNC (positive-going or negative-going) is supported. Serial communications capability is not disabled by either SHUT1 or SHUT2. Example (positive-going SYNC selected): Upon the negative edge of SYNC input, a sequence begins to stop the CLK output. Upon the positive edge, CLK resumes operation, synchronized to the phase of the SYNC input (plus a deterministic delay). This is performed by control of the device post-divider. Phase resolution equal to ½ of the VCO period can be achieved (approximately down to 2ns). 4.2 Differential Output Stage The differential output stage supports both CMOS and pseudoECL (PECL) signals. The desired output interface is chosen via the programming registers. 5.0 I2C-bus Control Interface If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output stage can only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. The ratio of output sink current to IPRG current is 13:1. Source current for the CLKx pins is provided by the pull-up resistors that are part of the Thévenin termination. This device is a read/write slave device meeting all Philips I2C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter, and a device receiving data as the receiver. 4.2.1 Example Assume that it is desired to connect a PECL-type fanout buffer right next to the FS7140. Further assume: · VDD = 3.3V · desired VHI = 2.4V · desired VLO = 1.6V · equivalent RLOAD = 75 ohms AMI Semiconductor - Rev. 3.0 www.amis.com Data Sheet I2C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS). 4 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet 5.1 Bus Conditions 5.2 I2C-bus Operation Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined by the I2C-bus protocol. All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal oscillator does not have to run for communication to occur. 5.1.1 Not Busy 5.2.1 Slave Address Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy. After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the device is: The device accepts the following I2C-bus commands: 5.1.2 START Data Transfer A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition. A5 A4 A3 A2 A1 A0 1 0 1 1 0 X X where X is controlled by the logic level at the ADDR pins. The selectable ADDR bits allow four different FS7140 devices to exist on the same bus. Note that every device on an I2C-bus must have a unique address to avoid pos-sible bus conflicts. 5.1.3 STOP Data Transfer A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition. 5.2.2 Random Register Write Procedure Random write operations allow the master to directly write to any register. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. 5.1.4 Data Valid The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, first-overwritten fashion. If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored. 5.2.3 Random Register Read Procedure Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. 5.1.5 Acknowledge When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not The master must signal an end of data to the slave by not generating and acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition. AMI Semiconductor - Rev. 3.0 www.amis.com A6 5 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator 5.2.5 Sequential Register Read Procedure acknowledge the transfer but does generate a STOP condition. Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one after each read. This procedure is more efficient than the random register read if several registers must be read. 5.2.4 Sequential Register Write Procedure Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the random register write if several registers must be written. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to eight bytes of data into the addressed register before the register address pointer overflows back to the beginning address. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all eight bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP condition to occur. Registers are therefore updated at different times during a sequential register write. AMI Semiconductor - Rev. 3.0 www.amis.com Data Sheet 6 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator S DEVICE ADDRESS W A REGISTER ADDRESS 7-bit Receive Device Address A Register Address A P Data Acknowledge Acknowledge START Command DATA STOP Condition Acknowledge WRITE Command From bus host to device From device to bus host Figure 4: Random Register Write Procedure S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS A S DATA A P Data STOP Condition Acknowledge Repeat START Acknowledge WRITE Command From bus host to device R A 7-bit Receive Device Address Register Address Acknowledge START Command DEVICE ADDRESS NO Acknowledge READ Command From device to bus host Figure 5: Random Register Read Procedure S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS DATA Register Address Acknowledge START Command A A DATA DATA Data Data Acknowledge A Acknowledge Data Acknowledge Acknowledge STOP Command WRITE Command From bus host to device A P From device to bus host Figure 6: Sequential Register Write Procedure S DEVICE ADDRESS W A 7-bit Receive Device Address REGISTER ADDRESS Register Address Acknowledge START Command WRITE Command From bus host to device A S DEVICE ADDRESS R A 7-bit Receive Device Address Acknowledge READ Command From device to bus host Figure 7: Sequential Register Read Procedure AMI Semiconductor - Rev. 3.0 www.amis.com A DATA 7 A P Data Data Repeat START Acknowledge DATA Acknowledge NO Acknowledge STOP Command Data Sheet FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet 6.0 Programming Information All register bits are cleared to zero on power-up. All register bits may be read back as written. Table 3: FS7140 Register Map ADDRESS BYTE 7 BYTE 6 BYTE 5 BYTE 4 BYTE 3 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED (Bit 63) (Bit 62) (Bit 61) (Bit 60) (Bit 59) (Bit 58) (Bit 57) (Bit 56) Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” RESERVED RESERVED SHUT2 RESERVED RESERVED RESERVED RESERVED RESERVED (Bit 55) (Bit 54) (Bit 53) (Bit 52) (Bit 51) (Bit 50) (Bit 49) (Bit 48) Must be set to “0” Must be set to “0” 0 = Normal 1 = Powered Down Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” RESERVED LC LR[1] LR[0] RESERVED RESERVED CP[1] CP[0] (Bit 47) (Bit 46) (Bit 45) (Bit 44) (Bit 43) (Bit 42) (Bit 41) (Bit 40) Must be set to “0” Loop Filter Cap Select Must be set to “0” Must be set to “0” CMOS FBKDSRC FBKDIV[13] FBKDIV[12] FBKDIV[11] FBKDIV[10] FBKDIV[9] FBKDIV[8] (Bit 39) (Bit 38) (Bit 37) (Bit 36) (Bit 35) (Bit 34) (Bit 33) (Bit 32) 0 = PECL 1 = CMOS 0 = VCO Output 1 = Post Divider Output 8192 4096 2048 1024 512 256 FBKDIV[7] FBKDIV[6] FBKDIV[5] FBKDIV[4] FBKDIV[3] FBKDIV[2] FBKDIV[1] FBKDIV[0] (Bit 31) (Bit 30) (Bit 29) (Bit 28) (Bit 27) (Bit 26) (Bit 25) (Bit 24) 128 64 32 16 8 4 2 1 Loop Filter Resistor Select Charge Pump Current Select See Section 4.1.2 for disallowed FBKDIV values See Section 4.1.2 for disallowed FBKDIV values BYTE 2 POST2[3] POST2[2] POST2[1] POST2[0] POST1[3] POST1[2] POST1[1] POST1[0] (Bit 23) (Bit 22) (Bit 21) (Bit 20) (Bit 19) (Bit 18) (Bit 17) (Bit 16) Modulus = N+1 (N=0 to 11) See Table 8 BYTE 1 POST3[1] POST3[0] SHUT1 REFDSRC REFDIV[11] REFDIV[10] REFDIV[9] REFDIV[8] (Bit 15) (Bit 14) (Bit 13) (Bit 12) (Bit 11) (Bit 10) (Bit 9) (Bit 8) 0 = Normal 1 = Powered Down 0 = Crystal Oscillator 1 = REF Pin 2048 1024 512 256 Modulus = 1, 2, 4, or 8 See Table 8 BYTE 0 Modulus = N+1 (N=0 to 11) See Table 8 REFDIV[7] REFDIV[6] REFDIV[5] REFDIV[4] REFDIV[3] REFDIV[2] REFDIV[1] REFDIV[0] (Bit 7) (Bit 6) (Bit 5) (Bit 4) (Bit 3) (Bit 2) (Bit 1) (Bit 0) 128 64 32 16 8 4 2 1 AMI Semiconductor - Rev. 3.0 www.amis.com 8 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet Table 4: FS7145 Register Map ADDRESS BYTE 7 BYTE 6 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED (Bit 63) (Bit 62) (Bit 61) (Bit 60) (Bit 59) (Bit 58) (Bit 57) (Bit 56) Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” Must be set to “0” RESERVED RESERVED SHUT2 RESERVED RESERVED RESERVED SYNCPOL SYNCEN (Bit 55) (Bit 54) (Bit 53) (Bit 52) (Bit 51) (Bit 50) (Bit 49) (Bit 48) Must be set to “0” 0 = Normal 1 = Powered Down “0” = negative “1” = positive Must be set to “0” BYTE 5 BYTE 4 BYTE 3 Must be set to “0” Must be set to “0” Must be set to “0” “0” = negative “1” = positive RESERVED LC LR[1] LR[0] RESERVED RESERVED CP[1] CP[0] (Bit 47) (Bit 46) (Bit 45) (Bit 44) (Bit 43) (Bit 42) (Bit 41) (Bit 40) Must be set to “0” Loop Filter Cap Select Must be set to “0” Must be set to “0” CMOS FBKDSRC FBKDIV[13] FBKDIV[12] FBKDIV[11] FBKDIV[10] FBKDIV[9] FBKDIV[8] (Bit 39) (Bit 38) (Bit 37) (Bit 36) (Bit 35) (Bit 34) (Bit 33) (Bit 32) 0 = PECL 1 = CMOS 0 = VCO Output 1 = Post Divider Output 8192 4096 2048 1024 512 256 FBKDIV[7] FBKDIV[6] FBKDIV[5] FBKDIV[4] FBKDIV[3] FBKDIV[2] FBKDIV[1] FBKDIV[0] (Bit 31) (Bit 30) (Bit 29) (Bit 28) (Bit 27) (Bit 26) (Bit 25) (Bit 24) 128 64 32 16 8 4 2 1 Loop Filter Resistor Select Charge Pump Current Select See Section 4.1.2 for disallowed FBKDIV values See Section 4.1.2 for disallowed FBKDIV values BYTE 2 POST2[3] POST2[2] POST2[1] POST2[0] POST1[3] POST1[2] POST1[1] POST1[0] (Bit 23) (Bit 22) (Bit 21) (Bit 20) (Bit 19) (Bit 18) (Bit 17) (Bit 16) Modulus = N+1 (N=0 to 11) See Table 8 BYTE 1 POST3[1] POST3[0] SHUT1 REFDSRC REFDIV[11] REFDIV[10] REFDIV[9] REFDIV[8] (Bit 15) (Bit 14) (Bit 13) (Bit 12) (Bit 11) (Bit 10) (Bit 9) (Bit 8) 0 = Normal 1 = Powered Down 0 = Crystal Oscillator 1 = REF Pin 2048 1024 512 256 Modulus = 1, 2, 4, or 8 See Table 8 BYTE 0 Modulus = N+1 (N=0 to 11) See Table 8 REFDIV[7] REFDIV[6] REFDIV[5] REFDIV[4] REFDIV[3] REFDIV[2] REFDIV[1] REFDIV[0] (Bit 7) (Bit 6) (Bit 5) (Bit 4) (Bit 3) (Bit 2) (Bit 1) (Bit 0) 128 64 32 16 8 4 2 1 AMI Semiconductor - Rev. 3.0 www.amis.com 9 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Table 5: Device Configuration Bits Table 9: Post Divider Control Bits Name Name Description POST1[3:0] POST Divider #1 (NP1) Modulus [0000] 1 [0001] 2 [0010] 3 [0011] 4 [0100] 5 [0101] 6 [0110] 7 [0111] 8 [1000] 9 [1001] 10 [1010] 11 [1011] 12 [1100] [1101] Do not use [1110] [1111] POST2[3:0] POST Divider #2 (NP2) Modulus [0000] 1 [0001] 2 [0010] 3 [0011] 4 [0100] 5 [0101] 6 [0110] 7 [0111] 8 [1000] 9 [1001] 10 [1010] 11 [1011] 12 [1100] [1101] Do not use [1110] [1111] REFDSRC FBKDSRC SHUT1 SHUT2 CMOS Description REFerence Divider SouRCe [0] = Crystal Oscillator / [1] = REF Pin FeedB ack Divider SouRCe [0] = VCO Output / [1] = Post Divider Output SHUTdown1 [0] = Normal / [1] = Powered Down SHUTdown2 [0] = Normal / [1] = Powered Down CLKP/CLKN Output Mode [0] = PECL Output / [1] CMOS Output Table 6: Main Loop Tuning Bits Name CP[1:0] LR[1:0] LC Description Charge Pump Current [00] [01] [10] [11] Loop Filter Resistor Select [00] [01] [10] [11] Loop Filter Capacitor Select [0] [1] 2.0mA 4.5mA 11.0mA 22.5mA 400KW 133KW 30KW 12KW 185pF 500pF Table 7: PLL Divider Control Bits NAME DESCRIPTION REFDIV[11:0] REFerence DIVider (NR) FBKDIV[13:0] FeedBacK DIVider (NR) POST3[1:0] Table 8: SYNC Control Bits (FS7145 only) Name SYNCEN SYNCPOL Description SYNC Enable [0] = Disabled / [1] = Enabled SYNC POLarity [0] = Negative Edge / [1] = Positive Edge AMI Semiconductor - Rev. 3.0 www.amis.com 10 POST Divider #3 (NP3) [00] [01] [10] [11] Modulus 1 2 4 8 Data Sheet FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet 7.0 Electrical Specifications Table 10: Absolute Maximum Ratings Parameter Symbol Min. Max. Units VDD VSS-0.5 4.5 V Input Voltage, dc V1 VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Supply Voltage, dc (V SS = ground) IIK -50 50 mA IOK -50 50 mA TS -65 150 °C Ambient Temperature Range, Under Bias TA -55 125 °C Junction Temperature TJ Input Clamp Current, dc (V I Output Clamp Current, dc (V < 0 or V I > V DD) I < 0 or V I > V DD) Storage Temperature Range (non-condensing) 150 °C Per IPC/JEDEC J-STD-020B Reflow Solder Profile Input Static Discharge Voltage Protection 2 (MIL-STD 883E, Method 3015.7) kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality and reliability . CAUTION: ELECTROST ATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 11: Operating Conditions Parameter Symbol Supply Voltage Ambient Operating Temperature Range AMI Semiconductor - Rev. 3.0 www.amis.com Min. Typ. Max. Units VDD Conditions/Description 3.0 3.3 3.6 V TA 0 70 °C 11 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet Table 12: DC Electrical Specifications Parameter Symbol Conditions/Description Min. Typ. Max. Units Overall Supply Current, Dynamic IDD CMOS mode; FXTAL = 15MHz; FVCO = 400MHz; FCLK = 200MHx; does not include load current 35 Supply Current, Static IDDL SHUT1, SHUT2 bit both “1” 400 mA 700 mA Serial Communication I/O (SDA, SCL) High-Level Input Voltage VIH Low-Level Input Voltage VIL Hysteresis Voltage Vhys Input Leakage Current II Low-Level Output Sink Current (SDA) IOL 0.8*VDD V 0.2*VDD V 0.33*VDD SDA, SCL in read condition SDA in acknowledge condition; VSDA = 0.4V -10 5 V +10 14 mA mA Address Select Input (ADDR0, ADDR1) High-Level Input Voltage VIH VVDD-1.0 Low-Level Input Voltage V High-Level Input Current (pull-down) IIH VADDRx = VDD Low-Level Input Current IIL VADDRx = 0V V 0.8 IL -1 V mA 30 1 mA Reference Frequency Input (REF) High-Level Input Voltage VIH VVDD-1.0 Low-Level Input Voltage VIL High-Level Input Current IIH VREF = VDD Low-Level Input Current (pull-down) IIL VREF = 0V V -1 0.8 V 1 mA mA -30 Sync Control Input (SYNC) High-Level Input Voltage VIH Low-Level Input Voltage VIL VVDD-1.0 High-Level Input Current IIH VREF = VDD Low-Level Input Current (pull-down) IIL VREF = 0V V -1 0.8 V 1 mA -30 mA Crystal Oscillator Input (XIN) Threshold Bias Voltage VTH VDD/2 V High-Level Input Current IIH VXIN = VDD 40 mA Low-Level input Current IIL VXIN = GND -40 Crystal Frequency FX Fundamental mode Recommended Crystal Load Capacitance* CL(XTAL) mA 35 MHz For best matching with internal crystal oscillator load 16-18 pF Crystal Oscillator Output (XOUT) High-Level Output Source Current IOH VXOUT = 0 -8.5 mA Low-Level Output Sink Current IOL VXOUT = VDD 11 mA IIL VIPRG = 0V; PECL Mode High-Level Output Source Current IOH VO = 2.0V 19 mA Low-Level Output Sink Current IOL VO = 0.4V -35 mA IPRG Bias Voltage VIPRG VDD/3 V IPRG Bias Current IIPRG VIPRG will be clamped to this level when a resistor is connected from VDD to IPRG IIPRG - (VVDD - VIPRG) / RSET PECL Current Program I/O (IPRG) Low-Level Input Current -10 10 mA Clock Outputs, CMOS Mode (CLKN, CLKP) Clock Outputs, PECL Mode (CLKN, CLKP) Sink Current to IPRG Current Ratio Tristate Output Current 3.5 mA 10 mA 13 IZ -10 Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3s from typical. Negative currents indicate current flows out of the device. AMI Semiconductor - Rev. 3.0 www.amis.com 12 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet Table 13: AC Timing Specifications Parameter Symbol Clock (MHz) Conditions/Description Min. Typ. Max. Units Overall Output Frequency* fO(max) VCO Frequency* fVCO CMOS outputs 0 150 PECL outputs 0 300 40 400 MHz MHz CMOS Mode Rise Time* tr CL = 7pF 1 ns CMOS Mode Fall Time* tf CL = 7pF 1 ns PECL Mode Rise Time* tr CL = 7pF; RL = 65 ohm 1 ns PECL Mode Fall Time* tf CL = 7pF; RL = 65 ohm 1 ns Reference Frequency Input (REF) Input Frequency FREF Reference High Time tREHF 3 ns Reference Low Time tREFL 3 ns 80 MHz Sync Control Input (SYNC) Sync High Time tSYNCH Sync Low Time tSYNCL for orderly CLK stop/start for orderly CLK stop/start 3 TCLK 3 TCLK Clock Output (CLKP, CLKN) Duty Cycle (CMOS Mode)* Measured at 1.4V Measured at zero crossings of (VCLKP-VCLKN) Duty Cycle (PECL Mode)* Jitter, Long Term (sg(t))* Jitter, Period (peak-peak)* tj(LT) tj(DP) 50 % 50 % For valid programming solutions. Long-term (or cumulative) jitter specified is RMS position error of any edge compared with an ideal clock generated from the same reference frequency. It is measured with a time interval analyzer using a 500 microsecond window, using statistics gathered over 1000 samples. ps ps FREF/NREF > 1000kHz 25 FREF/NREF ~= 500kHz 50 ps FREF/NREF ~= 250kHz 100 ps FREF/NREF ~= 125kHz 190 ps FREF/NREF ~= 62.5kHz 240 ps FREF/NREF ~= 31.5kHz 300 ps 40MHz < VCO Frequency < 100MHz 75 ps VCO Frequency > 100MHz 50 ps Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3s from typical. Table 14: Serial Interface Timing Specifications Fast Mode Parameter Symbol Conditions/Description Clock Frequency fSCL SCL Bus Free Time Between STOP and START tBUF 1300 Setup Time, START (repeated) tsu:STA 600 ns Hold Time, START thd:STA 600 ns ns Min. Max. 0 400 Units kHz ns Setup Time, Data Input tsu:DAT SDA 100 Hold Time, Data Input thd:DAT SDA 0 Output Data Valid From Clock tAA Rise Time, Data and Clock tR Fall Time, Data and Clock tF High Time, Clock tHI SCL 600 Low Time, Clock tLO SCL 1300 ns Setupt Time, STOP tsu:STO 600 ns ns 900 ns SDA, SCL 300 ns SDA, SCL 300 ns ns Unless otherwise stated, VDD = 3.3V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3s from typical. AMI Semiconductor - Rev. 3.0 www.amis.com 13 FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet ~ ~ SCL tsu:STO ~ ~ thd:STA tsu:STA SDA ~ ~ ADDRESS OR DATA VALID START DATA CAN CHANGE STOP Figure 8: Bus Timing Data tHI tR ~ ~ tF tLO SCL tsu:STA thd:STA ~ ~ tBUF ~ ~ SDA IN tAA tsu:STO tsu:DAT thd:DAT tAA SDA OUT Figure 9: Data Transfer Sequence 8.0 Package Information for ‘Green’ (FS7140) and ‘Non-Green’ (FS7140 & FS7145) Table 15: 16-pin SOIC (0.150”) Package Dimensions Dimensions Inches 16 Millimeters Min. Max. Min. Max. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 B 0.013 0.019 0.33 0.49 C 0.0075 0.0098 0.191 0.249 D 0.386 0.393 9.80 9.98 E 0.150 0.157 3.81 3.99 e 0.050 BSC 1 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0.89 Q 0° 8° 0° 8° H ALL RADII: 0.005" TO 0.01" B e 1.27 BSC H AMI Semiconductor - Rev. 3.0 www.amis.com E A2 D BASE PLANE A1 SEATING PLANE 14 A h x 45° 7° typ. C L q FS7140-01 / FS7140-01g / FS7145 Programmable Phase-Locked Loop Clock Generator Data Sheet Table 16: 16-pin SOIC (0.150”) Package Characteristics Parameter Symbol QJA Thermal Impedance, Junction to Free-Air L11 Lead Inductance, Self Conditions/Description Typ. Units Air flow = 0 ft./min. 108 °CW Corner lead 2.5 nH Center lead 1.2 nH Table 17: 16-pin 5.3mm (0.209”) SSOP Package Dimensions 16 Dimensions Inches Millimeters Min. Max. Min. Max. A 0.068 0.078 1.73 1.99 A1 0.002 0.008 0.05 0.21 A2 0.066 0.070 1.68 1.78 B 0.010 0.015 0.25 0.38 C 0.005 0.008 0.13 0.20 E D 0.239 0.249 6.07 6.33 1 E 0.205 0.212 5.20 5.38 B e 0.0256 BSC e 0.65 BSC H 0.301 0.311 7.65 7.90 L 0.022 0.037 0.55 0.95 Q 0 8 0 8 H A2 D BASE PLANE C A L A1 q SEATING PLANE Table 18: 16-pin 5.3mm (0.208”) SSOP Package Characteristics Parameter Thermal Impedance, Junction to Free-Air 16-pin 0.150” SOIC Symbol QJA L11 Lead Inductance, Self Conditions/Description TYP. UNITS Air flow = 0ms 90 °C/W Corner lead 2.3 nH Center lead 1 nH 9.0 Ordering Information Ordering Code Device Number Package Type Operating Temperature Range 13715-802-XTP (or - XTD) FS7140-01 16-pin (0.150”) SOIC 0°C to 70°C (commercial) 13715-201-XTP (or -XTD) FS7140-01 16-pin (5.3mm) SSOP 0°C to 70°C (commercial) 13715-102-XTP (or -XTD) FS7145 16-pin (0.150”) SOIC 0°C to 70°C (commercial) 13715-202-XTP (or -XTD) FS7145 16-pin (5.3mm) SSOP 0°C to 70°C (commercial) 13715-805-XTP (or -XTD) FS7140-01g 13715-806-XTP (or -XTD) FS7140-01g 16-pin (5.3mm) SSOP ‘green’ or lead-free packaging 16-pin (0.150”) SOIC ‘green’ or lead-free packaging 0°C to 70°C (commercial) 0°C to 70°C (commercial) Shipping Configuration -XTP -XTD -XTP -XTD -XTP -XTD -XTP -XTD -XTP -XTD -XTP -XTD XTP - Tape & Reel XTD - Tube/Tray AMI Semiconductor - Rev. 3.0 www.amis.com 15 Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes no warranty of merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMIS for such applications. Copyright ©2006 AMI Semiconductor, Inc.