ETC UCC28063

UCC28063
SLUSAO7 – SEPTEMBER 2011
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Natural Interleaving™ Transition-Mode PFC Controller
with Improved Audible Noise Immunity
Check for Samples: UCC28063
NATURAL INTERLEAVING FEATURES
SYSTEM FEATURES
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1
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Input Filter and Output Capacitor
Ripple-Current Cancellation
– Reduced current ripple for higher system
reliability and smaller bulk capacitor
– Reduced EMI filter size
Phase Management Capability
FailSafe OVP with Dual Paths Prevents Output
Over-Voltage Conditions by Voltage-Sensing
Failures
Sensorless Current-Shaping Simplifies Board
Layout and Improves Efficiency
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APPLICATIONS
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100-W to 800-W Power Supplies
Gaming
D-to-A Set-Top Boxes
Adapters
LCD, Plasma and DLP™ TVs
Home Audio Systems
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Advanced Audible Noise Performance
Non-linear Error-Amplifier Gain
Soft Recovery on Overvoltage
Integrated Brownout and Dropout Handling
Reduced Bias Currents
Improved Efficiency and Design Flexibility
over Traditional Single-Phase Continuous
Conduction Mode (CCM)
Inrush-Safe Current Limiting:
– Prevents MOSFET conduction during
inrush
– Eliminates reverse recovery events in
output rectifiers
Enables Use of Low-Cost Diodes without
Extensive Snubber Circuitry
Improved Light-Load Efficiency
Fast, Smooth Transient Response
Expanded System-Level Protections
1-A Source/1.8-A Sink Gate Drivers
-40°C to 125°C Operating Temperature Range
in a 16-lead SOIC package
Typical Application Diagram
Ripple Current Reduction
400 VDC
EMI
Filter
–
+
5
UCC28063
12 VCC
10 CS
7
3
ZCDA 16
GDA 14
VINAC
TSET
ZCDB
1
GDB 11
PWMCNTL
9
VSENSE
2
PHB
4
COMP
5
Power Good to
Down Stream
Converter
Phase Management
15 VREF
HVSEN
AGND
PGND
6
13
8
Capacitor ripple current (A)
85 VAC to 265 VAC
POUT = 600 W
VOUT = 400 V
4
1-phase TM
3
1-phase CCM
2
2-phase TM Interleave
1
70
120
170
220
Input Voltage (V)
270
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
UCC28063
SLUSAO7 – SEPTEMBER 2011
www.ti.com
CONTENTS
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Electrical Characteristics 5
Device Information 9
Functional Block Diagram 12
Typical Characteristics 13
Application Information 19
Design Example 33
Additional References 41
DESCRIPTION
Optimized for consumer applications concerned with audible noise elimination, this solution extends the
advantages of transition mode – high efficiency with low-cost components – to higher power ratings than
previously possible. By utilizing a Natural Interleaving™ technique, both channels operate as masters (that is,
there is no slave channel) synchronized to the same frequency. This approach delivers inherently strong
matching, faster responses, and ensures that each channel operates in transition mode.
Expanded system level protections feature input brownout and dropout recovery, output over-voltage, open-loop,
overload, soft-start, phase-fail detection, and thermal shutdown. The additional FailSafe over-voltage protection
(OVP) feature protects against shorts to an intermediate voltage that, if undetected, could lead to catastrophic
device failure. Advanced non-linear gain results in rapid, yet smoother response to line and load transient events.
Reduced bias currents improve stand-by power efficiency. Special line-dropout handling avoids significant current
disruption and minimizes audible-noise generation.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
(1)
(2)
2
PART NUMBER
PACKAGE (2)
OPERATING TEMPERATURE RANGE, TA
UCC28063D
SOIC 16-Pin (D)
-40°C to +125°C
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
SOIC (D) package is available taped and reeled by adding R to the above part number. Reeled quantities for UCC28063DR are 2,500
devices per reel.
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ABSOLUTE MAXIMUM RATINGS (1)
All voltages are with respect to GND, −40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified
terminal, unless otherwise noted.
MIN
Continuous input voltage range
Continuous input current
Peak input current
Output current
Continuous gate current
Junction Temperature, TJ
Lead Temperature, TSOL
21
PWMCNTL
−0.5
20
COMP (3), PHB, HVSEN (4), VINAC (4), VSENSE (4)
−0.5
7
ZCDA, ZCDB
−0.5
4
CS (5)
−0.5
3
VCC
20
PWMCNTL
10
ZCDA, ZCDB
±5
CS
−30
VREF
−10
GDA, GDB (6)
±25
Operating
−40
125
Storage
−65
150
Soldering, 10s
(3)
(4)
(5)
(6)
V
mA
°C
260
2,000
Charged Device Model (CDM)
(2)
UNIT
−0.5
Human Body Model (HBM)
(1)
MAX
VCC (2)
500
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those included under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.
Voltage on VCC is internally clamped. VCC may exceed the continuous absolute maximum input voltage rating if the source is current
limited below the absolute maximum continuous VCC input current level.
In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.
In normal use, VINAC, VSENSE, and HVSEN are connected to high-value resistors and are internally limited in negative-voltage swing.
Although not recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as -10mA from negative
voltage sources, and input currents as high as +0.5mA from positive voltage sources.
In normal use, CS is connected to a series resistor to limit peak input current during brief system line-inrush conditions. In these
situations, negative voltage on CS may exceed the continuous absolute maximum rating.
No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to
damp resonant ringing due to stray inductance.
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RECOMMENDED OPERATING CONDITIONS
All voltages are with respect to GND, −40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified
terminal, unless otherwise noted.
MIN
MAX
VCC input voltage from a low-impedance source
PARAMETER
14
21
VCC input current from a high-impedance source
8
18
VREF load current
0
−2
VINAC input voltage
ZCDA, ZCDB series resistor
TSET resistor to program PWM on-time
HVSEN input voltage
0
6
20
80
66.5
400
0.8
4.5
UNIT
V
mA
V
kΩ
V
THERMAL INFORMATION
UCC28063
THERMAL METRIC (1)
SOIC (D)
UNITS
16 PINS
θJA
Junction-to-ambient thermal resistance (2)
91.6
θJCtop
Junction-to-case (top) thermal resistance (3)
52.1
(4)
θJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter (5)
14.9
ψJB
Junction-to-board characterization parameter (6)
48.3
(1)
(2)
(3)
(4)
(5)
(6)
4
48.6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
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ELECTRICAL CHARACTERISTICS
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VCC Bias Supply
VCCSHUNT
VCC shunt voltage (1)
IVCC = 10 mA
IVCC(ULVO)
VCC current, UVLO
VCC = 11.4 V prior to turn-on
IVCC(stby)
VCC current, disabled
VSENSE = 0 V
IVCC(on)
VCC current, enabled
VSENSE = 2 V
5
8
22
24
26
95
200
100
200
V
µA
mA
Undervoltage Lockout (UVLO)
VCCON
VCC turn-on threshold
VCC rising
11.5
12.6
13.5
VCCOFF
VCC turn-off threshold
VCC falling
9.5
10.35
11.5
1.85
2.15
2.45
UVLO Hysteresis
V
Reference
VREF
VREF output voltage, no load
IVREF = 0 mA
5.82
6.00
6.18
VREF change with load
0 mA ≤ IVREF ≤ −2 mA
-
−1
−6
VREF change with VCC
12 V ≤ VCC ≤ 20 V
-
+2
+10
5.85
6.00
6.15
5.82
6.00
6.18
50
100
150
1.15
1.25
1.35
0.02
0.07
0.15
4.70
4.95
5.10
0.03
0.125
40
55
70
3.25%
5%
6.75%
−3.25%
−5%
−6.75%
V
mV
Error Amplifier
VSENSEreg25 VSENSE input regulation
voltage
VSENSEreg
VSENSE input regulation
voltage
IVSENSE
VSENSE input bias current
VENAB
VSENSE enable threshold,
rising
TA = 25°C
V
In regulation
VSENSE enable hysteresis
VCOMPCLMP
gM
COMP high voltage, clamped
VSENSE = VSENSEreg – 0.3 V
COMP low voltage, saturated
VSENSE = VSENSEreg + 0.3 V
VSENSE to COMP
transconductance, small signal
0.99(VSENSEreg) < VSENSE <
1.01(VSENSEreg), COMP = 3 V
VSENSE high-going threshold
to enable COMP large signal
gain, percent
Relative to VSENSEreg, COMP = 3 V
VSENSE low-going threshold to Relative to VSENSEreg, COMP = 3 V
enable COMP large signal gain,
percent
nA
V
µS
VSENSE to COMP
transconductance, large signal
VSENSE = VSENSEreg – 0.4 V ,
COMP = 3 V
210
290
370
VSENSE to COMP
transconductance, large signal
VSENSE = VSENSEreg + 0.4 V,
COMP = 3 V
210
290
370
−80
−125
−170
µA
COMP maximum source current VSENSE = 5.0 V, COMP = 3 V
RCOMPDCHG
COMP discharge resistance
1.6
2.0
2.4
kΩ
IDODCHG
COMP discharge current during VSENSE = 5.0 V, VINAC = 0.3 V
Dropout
3.2
4
4.8
µA
VLOW_OV
VSENSE over-voltage
threshold, rising
Relative to VSENSEreg
7%
+8%
10%
VSENSE over-voltage
hysteresis
Relative to VLOW_OV
−1.5%
−2%
−3%
VSENSE 2nd over-voltage
threshold, rising
Relative to VSENSEreg
10.5%
11.3%
14%
VHIGH_OV
(1)
HVSEN = 5.2 V, COMP = 3 V
µS
Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply.
If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended.
See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Soft Start
VSSTHR
COMP Soft-Start threshold,
falling
VSENSE = 1.5 V
ISS,FAST
COMP Soft-Start current, fast
SS-state, VENAB < VSENSE < VREF/2
ISS,SLOW
COMP Soft-Start current, slow
SS-state, VREF/2 < VSENSE < 0.88VREF
KEOSS
VSENSE End-of-Soft-Start
threshold factor
Percent of VSENSEreg
15
23
30
−80
−125
−170
−11.5
−16
−20
96.5%
98.3%
99.8%
2.35
2.50
2.65
±0.03
±0.5
9.2
11.4
14.0
4.64
4.87
5.10
4.45
4.67
4.80
0.21
0.225
0.25
mV
µA
Output Monitoring
VPWMCNTL
HVSEN threshold to PWMCNTL HVSEN rising
IHVSEN
HVSEN input bias current, high
HVSEN = 3 V
IHV_HYS
HVSEN hysteresis bias current,
low
HVSEN = 2 V
VHV_OV_FLT
HVSEN threshold to
over-voltage fault
HVSEN rising
VHV_OV_CLR
HVSEN threshold to
over-voltage clear
HVSEN falling
VCOMP_PHFOFF
Phase Fail monitoring-disable
threshold
COMP falling
VCOMP_PHFHYS
Phase Fail monitoring
hysteresis
COMP rising
PWMCNTL output voltage low
HVSEN = 3 V, IPWMCNTL = 5 mA,
COMP = 0 V
tPHFDLY
Phase Fail filter time to
PWMCNTL high
PHB = 5 V, ZCDA switching,
ZCDB = 0.5 V, COMP = 3 V
IPWMCNTL_LEAK
PWMCNTL leakage current,
high
HVSEN = 2 V, PWMCNTL = 15 V
6
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V
µA
V
0.051
7.9
0.2
0.5
12
17
ms
±0.03
±0.5
µA
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
Gate Drive (2)
GDA, GDB output voltage, high
IGDA, IGDB = −100 mA
GDA, GDB on-resistance, high
IGDA, IGDB = −100 mA
GDA, GDB output voltage, low
IGDA, IGDB = 100 mA
GDA, GDB on-resistance, low
IGDA, IGDB = 100 mA
GDA, GDB output voltage high,
clamped
VCC = 20 V, IGDA, IGDB = −5 mA
GDA, GDB output voltage high,
low VCC
VCC = 12 V, IGDA, IGDB = −5 mA
Rise time
Fall time
GDA, GDB output voltage,
UVLO
VCC = 3.0 V, IGDA, IGDB = 2.5 mA
11.5
12.4
15
V
8.8
14
Ω
0.18
0.32
V
2
3.2
Ω
12
13.5
15
10
10.5
11.5
1 V to 9 V, CLOAD = 1 nF
18
30
9 V to 1 V, CLOAD = 1 nF
12
25
100
200
V
ns
mV
Zero Current Detector
ZCDA, ZCDB voltage threshold,
falling
0.8
1.0
1.2
ZCDA, ZCDB voltage threshold,
rising
1.5
1.7
1.9
ZCDA, ZCDB clamp, high
IZCDA = +2 mA, IZCDB = +2 mA
2.6
3.0
3.4
ZCDA, ZCDB clamp, low
IZCDA = −2 mA, IZCDB = −2 mA
0
−0.2
−0.4
ZCDA, ZCDB input bias current
ZCDA = 1.4 V, ZCDB = 1.4 V
±0.03
±0.5
ZCDA, ZCDB delay to GDA,
GDB outputs (2)
From ZCDx input falling to 1 V to
respective gate drive output rising 10%
50
100
ZCDA blanking time (3)
From GDA rising and GDA falling
100
ZCDB blanking time (3)
From GDB rising and GDB falling
100
CS input bias current,
dual-phase
At rising threshold
V
µA
ns
Current Sense
(2)
(3)
−120
−166
−200
CS current-limit rising threshold, PHB = 5 V
dual-phase
−0.180
−0.200
−0.220
CS current-limit rising threshold, PHB = 0 V
single-phase
−0.149
−0.166
−0.183
CS current-limit reset falling
threshold
−0.003
−0.015
−0.025
60
100
CS current-limit response
time (2)
From CS exceeding threshold−0.05 V to
GDx dropping 10%
CS blanking time
From GDx rising and falling edges
µA
V
ns
100
Refer to Figure 13, Figure 14, Figure 15, and Figure 16 of the Typical Characteristics for typical gate drive waveforms.
ZCD blanking times are ensured by design.
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ELECTRICAL CHARACTERISTICS (continued)
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages
are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of
the specified terminal, unless otherwise noted.
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
VINAC Input
IVINAC
VINAC input bias current,
above brownout
VINAC = 2 V
VBODET
VINAC brownout detection
threshold
VINAC falling
tBODLY
VINAC brownout filter time
VINAC below the brownout detection
threshold for the brownout filter time
VBOHYS
VINAC brownout threshold
hysteresis
VINAC rising
IBOHYS
VINAC brownout hysteresis
current
VINAC = 1 V for > tBODLY
VDODET
VINAC dropout detection
threshold
VINAC falling
tDODLY
VINAC dropout filter time
VINAC below the dropout detection
threshold for the dropout filter time
VDOCLR
VINAC dropout clear threshold
VINAC rising
±0.03
±0.5
µA
1.33
1.39
1.44
V
340
440
540
ms
30
62
75
mV
1.6
2
2.5
µA
0.315
0.35
0.38
V
3.5
5
7.0
ms
0.67
0.71
0.75
V
Pulse-Width Modulator
KT
On-time factor, phases A and B
VSENSE = 5.8 V (4)
3.6
4.0
4.4
KTS
On-time factor, single-phase, A
VSENSE = 5.8 V, PHB = 0 V (4)
7.2
8.0
8.9
Phase B to phase A on-time
matching error
VSENSE = 5.8 V
±2%
±6%
Zero-crossing distortion
correction additional on time
COMP = 0.25 V, VINAC = 1 V
VPHBF
PHB threshold falling, to
single-phase operation
To GDB output shutdown, VINAC = 1.5 V
VPHBR
PHB threshold rising, to
two-phase operation
To GDB output running, VINAC = 1.5 V
TMIN
Minimum switching period
RTSET = 133 kΩ (4)
1.7
2.2
3.0
TSTART
PWM restart time
ZCDA = ZCDB = 2 V (5)
165
210
265
COMP = 0.25 V, VINAC = 0.1 V
1.2
2
2.8
12.6
20
29
0.7
0.8
0.9
0.9
1.0
1.1
µs/V
µs
V
µs
Thermal Shutdown
TJ
Thermal shutdown temperature
Temperature rising (6)
160
TJ
Thermal restart temperature
Temperature falling (6)
140
(4)
(5)
(6)
8
°C
Gate drive on-time is proportional to (VCOMP – 0.125 V). The on-time proportionality factor, KT, scales linearly with the value of RTSET
and is different in two-phase and single-phase modes. The minimum switching period is proportional to RTSET.
An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart
time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.
Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating
temperature is not specified or assured.
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DEVICE INFORMATION
UCC28063D
SOIC 16-Pin (D)
ZCDB
1
16
ZCDA
VSENSE
2
15
VREF
TSET
3
14
GDA
PHB
4
13
PGND
COMP
5
12
VCC
AGND
6
11
GDB
VINAC
7
10
CS
HVSEN
8
9
PWMCNTL
TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
6
-
Analog Ground
COMP
5
O
Error Amplifier Output
CS
10
I
Current Sense Input
GDA
14
O
GDB
11
O
HVSEN
8
I
High Voltage Output Sense
PHB
4
I
Phase-B Enable/Disable
PWMCNTL
9
O
PWM-Control Output
Channel A and Channel B Gate Drive Output
TSET
3
I
Timing Set
VCC
12
-
Bias Supply Input
VINAC
7
I
Input AC Voltage Sense
VREF
15
O
Voltage Reference Output
VSENSE
2
I
Output DC Voltage Sense
ZCDA
16
I
ZCDB
1
I
Zero Current Detection Inputs
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Detailed Pin Description
Analog Ground: Connect analog signal bypass capacitors, compensation components, and analog signal
returns to this pin. Connect the analog and power grounds at a single point to isolate high-current noise signals
of the power components from interference with the low-current analog circuits.
Error Amplifier Output: The error amplifier is a transconductance amplifier, so this output is a high-impedance
current source. Connect voltage-regulation loop-compensation components from this pin to AGND. The on-time
seen at the gate-drive outputs is proportional to the voltage at this pin minus an offset of approximately 125 mV.
During normal operation, the error amplifier maintains a transconductance of 55 μS for small-signal disturbances
on VSENSE, and shifts to ~290 μS when VSENSE deviates more than +/-5% from VSENSEreg. During an
AC-line Dropout condition, the error amplifier output is disabled and an internal 4-μA source discharges COMP
for the duration of the Dropout condition. During a VSENSE-based OV event, an internal 2-kΩ resistor is applied
from COMP to GND until the OV condition clears. During soft-start triggering events (UVLO, Disable, Brownout,
HVSEN over-voltage, TSET-Fault, CS open-circuit, or Thermal Shutdown), the error-amp output is disabled and
COMP is pulled low by an internal 2-kΩ resistor. The soft-start condition begins only after the triggering event
clears and COMP has been discharged below 20 mV, ensuring that the circuit restarts with a low COMP voltage
and a short on-time. (Do not connect COMP to a low-impedance source that would interfere with COMP falling
below 20 mV.) During Soft-Start, the error amplifier high transconductance is enabled and COMP current is -125
μA as long as VSENSE < VREF/2. Once VSENSE exceeds VREF/2, the high gain is disabled and only the
small-signal gain capability is available with a maximum COMP current of approximately -16 μA. Normal
operation resumes once VSENSE > 0.983VREF (~5.9 V).
Current Sense Input: Connect the current-sense resistor and the negative terminal of the diode bridge to this
pin. Connect the return of the current sense resistor to the AGND pin with a separate trace. As input current
increases, the voltage on CS will go more negative. This cycle-by-cycle over-current protection limits input
current by turning off both gate driver outputs (GDx) when CS is more negative than the CS rising threshold
(approximately -200 mV in two-phase operation and approximately -167 mV in single-phase and phase-fail
condition). The gate drive outputs will remain low until CS falls to the CS falling threshold (approx. -15 mV).
Current sense is blanked for approximately 100 ns following the rising and falling edge of either GDx output. This
filters noise that may occur from gate-drive current or when inductor current switches from a power FET to a
boost diode. In most cases, no additional current sense filtering is required. If external filtering is deemed
necessary, or to prevent excessive negative voltage on the CS pin during AC-inrush conditions, a series resistor
is recommended to connect the current sensing resistor to the CS pin. Due to the CS bias current, this external
resistor should be less than 100 Ω to maintain accuracy. If the CS pin becomes open-circuited, the voltage on
CS floats up to about +1.5 V. This condition is detected and treated as a soft-start-triggering fault condition (CS
open-circuit).
Channel A and Channel B Gate Drive Output: Connect these pins to the gate of the power FET for each
phase through the shortest connection practicable. If it is necessary to use a trace longer than 0.5 inch (12.6
mm) for this connection, some ringing may occur due to trace series inductance. This ringing can be damped by
adding a low-value resistor in series with GDA and GDB.
High Voltage Output Sense: The UCC28063 incorporates FailSafe OVP so that any single failure does not
allow the output to boost above safe levels. Output over-voltage is monitored by both VSENSE and HVSEN but
their actions are different if either pin exceeds their respective over-voltage thresholds. Using two pins to monitor
for over-voltage provides redundant protection and fault tolerance. When HVSEN exceeds its over-voltage
threshold, it triggers a full soft-start of the controller. HVSEN can also be used to enable a downstream power
converter when the voltage on HVSEN is within the operating region. When HVSEN is greater than 2.5 V, the
PWMCNTL output may be driven Low (provided no other fault exists). When HVSEN falls below 2.5 V, the
PWMCNTL output becomes high-impedance. Select the HVSEN divider ratio for the desired over-voltage and
power-good thresholds. Select the HVSEN divider impedance for the desired power-good hysteresis based on
the hysteresis current. During operation, HVSEN must never fall below 0.8 V. Dropping HVSEN below 0.8 V puts
the UCC28063 into a special test mode, used only for factory testing. A bypass capacitor from HVSEN to AGND
is recommended to filter noise and avoid false over-voltage shutdown.
Phase-B Enable/Disable: When the voltage applied to this pin is below the Phase-B enable threshold, Phase B
of the boost converter and the Phase Fail detector are disabled. The commanded on-time for Phase A is
immediately doubled when Phase B is disabled, which helps keep COMP voltage constant during the
phase-management transient. The PHB pin allows the user to add external phase-management control circuitry,
if desired. To disable phase-management, connect the PHB pin to the VREF pin.
10
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PWM-Control Output: This open-drain output goes low when HVSEN is within the HVSEN-good region (HVSEN
> 2.5 V), there is no FailSafe OV, and there is no Phase-Fail condition when operating in two-phase mode (see
PHB pin). Otherwise, PWMCNTL is high-impedance.
Timing Set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the on-time versus
COMP voltage and the minimum switching period at the gate-drive outputs. Protection circuits prevent the
controller from operating if the TSET input is in an open-circuit or short-circuit condition. As long as this pin is
open-circuited, it triggers a full soft-start condition. If this pin becomes shorted to GND, its current is limited and
also triggers a soft-start condition.
Bias Supply Input: Connect this pin to a controlled bias supply of between 14 V and 21 V. Also connect a
0.1-μF or larger ceramic bypass capacitor from this pin to PGND with the shortest possible board trace. This bias
supply powers all circuits within the device and must be capable of delivering the steady-state dc current plus the
transient power-MOSFET gate-charging current. Input bias current is very low during undervoltage-lockout
(UVLO) or stand-by conditions (VSENSE < 1.25 V).
Input AC Voltage Sense: For normal operation, connect this pin to a voltage divider across the rectified input
power mains. When the voltage on VINAC remains below the brownout threshold for longer than the brownout
filter time, the device enters a brownout mode, both output drivers are disabled and a full soft-start is triggered.
Select the input voltage divider ratio for the desired brownout threshold. Select the divider impedance for the
desired brownout hysteresis based on the hysteresis current. A dropout condition is triggered when VINAC
remains below the dropout threshold for longer than the dropout filter time. The error amplifier is disabled and an
internal 4-μA current source discharges COMP for the duration of the dropout condition. The dropout condition is
immediately cleared and normal operation resumes when VINAC exceeds the dropout-clear threshold.
Voltage Reference Output: Connect a 0.1-μF or larger ceramic bypass capacitor from this pin to AGND. VREF
turns off during UVLO and VSENSE-disable to save bias current and increase stand-by efficiency. This reference
output can be used to bias other circuits requiring less than a few milliamperes of non-pulsing total supply
current.
Output DC Voltage Sense: Connect this pin to a voltage divider across the output of the power converter. In a
closed-loop system, the voltage at VSENSE is regulated to the error amplifier reference voltage. Select the
output voltage divider ratio for the desired output voltage. Connect the ground side of this divider to analog
ground (AGND) through a separate short trace for best output regulation accuracy and noise immunity. Controller
operation may be enabled when VSENSE voltage exceeds the 1.25-V enable threshold. VSENSE can be pulled
low by an open-drain logic output, or >6-V logic output in series with a low-leakage diode, to disable the outputs
and reduce VCC current. Two levels of output overvoltage are detected at this input. If VSENSE exceeds the
first-level overvoltage protection threshold VLOW_OV, an internal 2-kΩ resistor is applied to COMP to quickly
reduce gate-drive on-time. If VSENSE continues to rise past the second-level threshold VHIGH_OV, GDA and GDB
are immediately latched off. This latch is cleared when VSENSE falls below the OV-clear threshold. If VSENSE
becomes disconnected, open-loop protection provides an internal current source to pull VSENSE low, which
disables the controller and triggers a soft-start condition.
Zero Current Detection Inputs: These inputs are used to detect a negative-going edge when the boost inductor
current in each respective phase goes to zero. The inputs are clamped between 0 V and 3 V. Connect each pin
through a current limiting resistor to the zero-crossing detection (ZCD) winding of the corresponding boost
inductor. The resistor value should be chosen to limit the clamping currents to less than ±3 mA. The inductor
winding polarity must be arranged so that this ZCD voltage falls when the inductor current decays to zero. When
the inductor current falls to zero, the ZCD input must drop below the falling threshold (approximately 1 V) to
cause the gate drive output to rise. Subsequently, when the power-MOSFET turns off, the ZCD input must rise
above the rising threshold (approximately 1.7 V) to arm the logic for another falling ZCD edge.
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Functional Block Diagram
Overcurrent
+
100ns
Blanking
Open
Detection
CS_OPEN
VINAC
BROWNOUT
HVSEN_OV
UVLO
EN
OC
TSET_FLT
CS_OPEN
TSD
Brownout Detection
7
440ms Delay
50mV
R
Q
STOP_GDA
S
Q
STOP_GDB
OC
HIGH _OV
PHASE_B_OFF
12 VCC
UVLO
12.6V /
10.35V
+
BROWNOUT
+
1.4V
COMP_DSCHG
6.00V
Reg.
-0.200 V /
-0.015V
CS 10
DSCHG _RST
1-PHASE
VGD
Reg.
-0.167 V /
-0.015V
24V
Thermal ShutDown
5ms Delay
PHASE_B_OFF
TSET_FLT
Trigger
+
100ns
Blanking
Crossover
Notch
Reduction
Trigger
DROPOUT
DSCHG_RST
+
20mV
VCC
+
EA Gain Control
for Soft-Start
and Dropout
EN
50mV
+
1.25V
ZCA
LOW_OV
120mV
6.48V
TON Modulation
Phase B
On-Time Control
HIGH_OV
6.67V
DIS_EA
DIS_High_Gain
ZCB
PhaseFail
VSENSE
2
VREF
272mV /
222 mV
+g
M
50μS /
250μS
100nA
1.0V /
0.8V
13.5V
11 GDB
STOP_GDB
13 PGND
HVSEN_OV
+
8
HVSEN
9
PWMCNTL
4.87V /
4.67V
+
2.5V
12μA
+
+
PHASE_B_OFF
4.95V
12
PGND
Interleave
Control
LOW_OV
COMP_DSCHG
2k
4μA
+
14 GDA
ZCB
100ns
Blanking
TON Basis
1
Clamping
ZCDB
+
TON Modulation
STOP_GDA
ZCA
VINAC
1.7V /
1.0V
VREF
PWMB
1.7V /
1.0V
15 VREF
UVLO
EN
13.5V
Phase Fail Detector
and
12ms Filter
ZCDA 16
Open/Short
Detection
13.5V
Phase A
On-Time Control
1-PHASE
3
Clamping
TSET
TJ
160°C /
140 °C
DROPOUT
+
TON Basis
0.70V /
0.35V
+
TSD
PWMA
Dropout Detection
2μA
6
5
4
AGND
COMP
PHB
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TYPICAL CHARACTERISTICS
At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ;
all voltages are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and
negative out of the specified terminal, unless otherwise noted.
BIAS SUPPLY CURRENT
vs
BIAS SUPPLY VOLTAGE
BIAS SUPPLY CURRENT
vs
TEMPERATURE
10
10
Enabled
IVCC − Bias Supply Current (mA)
IVCC − Bias Supply Current (mA)
Enabled
1
VCC Turn OFF
VCC Turn ON
0.1
Disabled
0.01
0
2
4
6
8
10
12
14
16
VCC − Bias Supply Voltage (V)
18
1
0.1
Disabled
0.01
−40
20
−20
0
20
40
60
80
TJ − Temperature (°C)
100
G000
G001
Figure 1.
Figure 2.
REFERENCE VOLTAGE
vs
TEMPERATURE
VSENSE INPUT BIAS CURRENT
vs
INPUT VOLTAGE
150
6.10
6.08
IVREF = 0 to −2 mA
125
IVSENSE − Input Bias Current (nA)
6.06
VREF Reference Voltage (V)
120
6.04
6.02
6.00
5.98
5.96
5.94
100
75
50
25
5.92
5.90
−40
−20
0
20
40
60
80
TJ − Temperature (°C)
100
120
0
0
1
2
3
4
VVSENSE − Input Voltage (V)
5
G002
Figure 3.
6
G003
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
ERROR AMPLIFIER OUTPUT CURRENT
vs
INPUT VOLTAGE
ERROR AMPLIFIER TRANSCONDUCTANCE
vs
VSENSE
150
300
Soft−start Completed
250
LOW_OV
Trigger
Transconduction 54 µS
50
gM − Transconductance (µS)
ICOMP − Output Current (µA)
100
LOW_OV
Clear
0
−50
−100
200
150
100
50
−150
5.0
5.2
5.4
5.6 5.8 6.0 6.2 6.4
VVSENSE − Input Voltage (V)
6.6
6.8
0
5.0
7.0
5.2
5.4
5.6 5.8 6.0 6.2 6.4
VVSENSE − Input Voltage (V)
6.6
6.8
G004
7.0
G005
Figure 5.
Figure 6.
ERROR AMPLIFIER TRANSCONDUCTANCE
vs
TEMPERATURE
ERROR AMPLIFIER OUTPUT CURRENT
vs
OUTPUT VOLTAGE
20
60
5.9 V < VVSENSE < 6.1 V
58
15
VVSENSE = 6.2 V
10
ICOMP − Output Current (µA)
gM − Transconductance (µS)
56
54
52
50
48
46
VVSENSE = 6.1 V
5
0
VVSENSE = 5.9 V
−5
VVSENSE = 5.8 V
−10
44
−15
42
40
−40
−20
0
20
40
60
80
TJ − Temperature (°C)
100
120
−20
0
1
2
3
VCOMP − Output Voltage (V)
G006
Figure 7.
14
4
5
G007
Figure 8.
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TYPICAL CHARACTERISTICS (continued)
ON-TIME FACTOR
vs
TIME SETTING RESISTOR
10
9
9
8
RTSET = 266 kW
8
KTL
KTL - On-Time Factor - ms/V
KT - On-Time Factor - ms/V
ON-TIME FACTOR PHASE A AND B
vs
TEMPERATURE
7
6
5
4
3
2
7
6
5
RTSET = 133 kW
4
3
2
RTSET = 66 kW
1
1
0
0
60
80 100 120 140 160 180 200 220 240 260 280
-40
0
-20
RTSET - Time Setting Resistor - kW
ADDITIONAL ON TIME
vs
VINAC
RTSET = 266 kW
102
100
98
96
KT0 =
92
120
RTSET = 133 kW
RTSET = 66 kW
94
100
RTSET = 266 kW
GDB
Additional On-Time - ms
104
KT/KT0 - %
80
ON-TIME FACTOR
vs
PHASE ERROR
RTSET = 133 kW
106
60
Figure 10.
100
108
40
Figure 9.
110
GDA
20
TJ - Temperature - °C
RTSET = 66 kW
10
1
2(KTA ´ KTB)
KTA + KTB
0.1
90
150
160
170
180
190
200
210
0
Phase Shift of GDA Relative to GDB - Degrees
Figure 11.
0.5
1.0
1.5
2.0
2.5
3.0
VVINAC - Input AC Voltage Sense - V
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
GATE DRIVE RISING
vs
TIME
GATE DRIVE FALLING
vs
TIME
2.0
GD Source Current:
VCC = 20 V
VCC = 12 V
6
1.5
1.0
4
0.5
2
0
0
-2
0
50
100
150
200
250
300
10
2.0
GD Sink Current:
VCC = 20 V
VCC = 12 V
8
6
1.0
4
0.5
-0.5
0
-1.0
-2
0
GD Voltage:
VCC = 20 V
VCC = 12 V
-0.5
-1.0
0
20
40
Time - ns
60
80
100
120
140
Time - ns
Figure 13.
Figure 14.
GATE DRIVE RISING
AND DELAY FROM ZCD INPUT
vs
TIME
GATE DRIVE FALLING
AND DELAY FROM CS INPUT
vs
TIME
7
500
14
14
CLOAD = 4.7 nF
CLOAD = 4.7 nF
GD Output:
TJ = -40°C
TJ = +25°C
TJ = +125°C
4
3
400
12
10
300
10
200
8
8
6
2
4
1
2
0
0
Current Sense Input - mV
5
12
Gate Drive Output - V
6
ZCD Input - V
1.5
2
350
2.5
100
CS Input
Voltage
6
GD Output:
TJ = -40°C
TJ = +25°C
TJ = +125°C
0
-100
4
Gate Drive Output - V
8
GD Voltage:
VCC = 20 V
VCC = 12 V
Gate Drive Output - V
10
3.0
VCC = 20 V and 12 V
CLOAD = 4.7 nF
12
2.5
Gate Drive Source Current - A
12
Gate Drive Output - V
14
3.0
VCC = 20 V and 12 V
CLOAD = 4.7 nF
Gate Drive Source Current - A
14
2
0
-200
ZCD Input Voltage
-1
-2
-25 0
50
100
150
200
250
300
-300
-2
-25 0
Time - ns
Figure 15.
16
50
100
150
200
250
300
Time - ns
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
GATE DRIVE OUTPUT HIGH
vs
VCC
GATE DRIVE HIGH VOLTAGE
vs
TEMPERATURE
15
15
RLOAD = 2.7 kW
14
TJ = -40°C
13
13
TJ = +125°C
12
Gate Drive Voltage - V
Gate Drive Voltage - V
14
TJ = +25°C
11
10
Clamped VCC ³ 15 V
12
11
Unclamped VCC = 12 V
10
9
8
7
9
6
RLOAD = 2 kW
8
5
10
11
12
13
14
15
16
17
18
19
20
-40
VVCC - Bias Supply Voltage - V
-20
0
20
40
60
60
100
120
TJ - Temperature - °C
Figure 17.
Figure 18.
GATE DRIVE LOW VOLTAGE
vs
TEMPERATURE
GATE DRIVE LOW VOLTAGE IN UVLO
vs
BIAS SUPPLY VOLTAGE
2.5
320
Load = 100 mA
Load = 10 mA
280
Load = 5 mA
240
VOL − Gate Drive Voltage (V)
VOL − Gate Drive Voltage (mV)
2.0
200
160
120
1.5
1.0
Load = 2.5 mA
Load = 1.0 mA
80
0.5
40
0
−40
−20
0
20
40
60
80
TJ − Temperature (°C)
100
120
0.0
0
1
2
3
VCC − Bias Supply Voltage (V)
G008
Figure 19.
4
G009
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
VARIOUS DELAY TIMES
vs
TEMPERATURE
ZERO CURRENT DETECT CLAMP VOLTAGE
vs
INPUT CURRENT
1000
3.5
3.0
Brownout Filter Delay
2.5
VZCD − Clamp Voltage (V)
Delay Time (ms)
100
Phase−Fail Filter Delay
10
Dropout Filter Delay
1
1.5
1.0
0.5
Restart Time Delay
0.1
−40
2.0
−20
0
20
40
60
80
TJ − Temperature (°C)
0.0
100
−0.5
120
−5
−4
−3
−2
−1
0
1
2
IZCD − Input Current (mA)
3
4
G010
5
G011
Figure 21.
Figure 22.
CURRENT SENSE INPUT BIAS CURRENT
vs
TEMPERATURE
CURRENT SENSE INPUT BIAS CURRENT
vs
INPUT VOLTAGE
0
−150
VCS = −195 mV
−155
ICS − Input Current (µA)
ICS − Input Bias Current (µA)
−50
−160
−165
−170
−175
−100
−150
Single−Phase Mode
Dual−Phase Mode
−180
−200
−185
−190
−40
−20
0
20
40
60
80
TJ − Temperature (°C)
100
120
−250
−300
−250
−200
−150
−100
VCS − Input Voltage (mV)
G012
Figure 23.
18
−50
0
G013
Figure 24.
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APPLICATION INFORMATION
Principles of Operation
The UCC28063 contains the control circuits for two parallel-connected boost pulse-width modulated (PWM)
power converters. The boost PWM power converters ramp current in the boost inductors for a time period
proportional to the voltage on the error amplifier output. Each power converter then turns off the power MOSFET
until current in the boost inductor decays to zero, as sensed on the zero current detection inputs (ZCDA and
ZCDB). Once the inductor is demagnetized, the power converter starts another cycle. This on/off cycling
produces a triangle wave of current, with peak current set by the on-time and instantaneous power mains input
voltage, VIN(t), as shown in Equation 1.
V (t) ´ TON
IPEAK (t) = IN
L
(1)
The average line current is exactly equal to half of the peak line current, as shown in Equation 2.
V (t) ´ TON
IAVG (t) = IN
2´L
(2)
With TON and L being essentially constant during an AC-line period, the resulting triangular current waveform
during each switching cycle will have an average value proportional to the instantaneous value of the rectified
AC-line voltage. This architecture results in a resistive input impedance characteristic at the line frequency and a
near-unity power factor.
Natural Interleaving
Under normal operating conditions, the UCC28063 regulates the relative phasing of the channel A and channel B
inductor currents to be very close to 180°. This greatly reduces the switching-frequency ripple currents seen at
the line-filter and output capacitors, compared to the ripple current of each individual converter. This design
allows a reduction in the size and cost of input and output filtering. The phase-control function differentially
modulates the on-times of the A and B channels based on their phase and frequency relationship. The Natural
Interleaving method allows the converter to achieve 180° phase-shift and transition-mode operation for both
phases without tight requirements on boost inductor tolerance.
Ideally, the best current-sharing is achieved when both inductors are exactly the same value. Typically the
inductances are not the same, so the current-sharing of the A and B channels is proportional to the inductor
tolerance. Also, switching delays and resonances of each channel typically differ slightly, and the controller
allows some necessary phase-error deviation from 180° to maintain equal switching frequencies. Optimal phase
balance occurs if the individual power stages and the on-times are well matched. Mismatches in inductor values
do not affect the phase relationship.
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On-Time Control, Maximum Frequency Limiting, and Restart Timer
Gate-drive on-time varies proportionately with the error-amplifier output voltage by a factor called KT (in units of
μs/V), as shown in Equation 3.
TON = K T (VCOMP - 125mV )
(3)
Where:
• VCOMP is the output voltage of the error amplifier and 125 mV is a modulator offset voltage.
The maximum output of the error amplifier is limited to 4.95 V. This value, minus the 125-mV modulator offset,
limits maximum on-time as determined by Equation 4.
TON(max) = K T ´ 4.825 V
(4)
This on-time limit sets the maximum power that can be delivered by the converter at a given input voltage.
At lower power, one boost channel (phase) may be turned off to achieve efficiency benefits (see Phase
Management section, below). To provide a smooth transition between two-phase and single-phase operation, KT
increases by a factor of two in single-phase mode:
K TS = 2 ´ K T ; active during single-phase operation
(5)
The maximum switching frequency of each phase is limited by minimum-period timers. If inductor current decays
to zero before the minimum-period timer elapses, the next turn-on will be delayed, resulting in discontinuous
phase current.
A restart timer ensures starting under all circumstances by restarting both phases if the ZCD input of either
phase has not transitioned from high-to-low within approximately 200 µs. To prevent the circuit from operating in
continuous conduction mode (CCM), the restart timer does not trigger turn-on until both phase-currents return to
zero.
The on-time factors (KT, KTS) and the minimum switching period, T(MIN), are proportional to the time-setting
resistor RTSET (the resistor from the TSET pin to ground), and these factors can be calculated by Equation 5,
Equation 6 and Equation 7:
R
ms
K T = TSET ´ 4.0
133kW
volt
(6)
RTSET
T(MIN) =
´ 2.2 ms ; Minimum Switching Period
133kW
(7)
The proper value of RTSET will result in the clamped maximum on-time, TON(max), required by the converter
operating at the minimum input line voltage and maximum load.
20
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Distortion Reduction
Due to the parasitic resonance between the drain-source capacitance of the switching MOSFET and the boost
inductor, conventional transition-mode PFC circuits may not be able to absorb power from the input line when the
input voltage is near zero. This limitation increases total harmonic distortion as a result of ac-line current
waveform distortion in the form of flat spots. To help reduce line-current distortion, the UCC28063 increases
switching MOSFET on-time when the input voltage is near 0 V to improve the power absorption capability and
compensate for this effect.
Figure 12 in the Typical Characteristics section shows the increase in on-time with respect to VINAC voltage.
Excessive filtering of the VINAC signal will nullify this function.
Zero-Current Detection and Valley Switching
In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current reaches zero. Because of
the resonance between the boost inductor and the parasitic capacitance at the MOSFET drain node, part of the
energy stored in the MOSFET junction capacitor can be recovered, reducing switching losses. Furthermore,
when the rectified input voltage is less than half of the output voltage, all the energy stored in the MOSFET
junction capacitor can be recovered and zero-voltage switching (ZVS) can be realized. By adding an appropriate
delay, the MOSFET can be turned on at the valley of its resonating drain voltage (valley-switching). In this way,
the energy recovery can be maximized and switching loss is minimized.
The optimal time delay is generally derived empirically, but a good starting point is a value equal to 25% of the
resonant period of the drain circuit. The delay can be realized by a simple RC filter, as shown in Figure 25, but
the delay time increases slightly as the input voltage nears the output voltage. Because the ZCD pin is internally
clamped, a more accurate delay can also be realized by using the circuit shown in Figure 26.
ZCD
R
CT
C
Figure 25. Simple RC Delay Circuit
ZCD
R1
CT
C
R2
Figure 26. More Accurate Time Delay Circuit
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Phase Management and Light-Load Operation
Under light-load conditions, switching losses may dominate over conduction losses and efficiency may be
improved if one phase (channel) is turned off. At a certain power level, the reduction of switching losses is
greater than the increase in conduction losses. Turning off one phase at light load is especially valuable for
meeting light-load efficiency standards. This is one of the major benefits of interleaved PFC and it is especially
valuable for meeting 80+ design requirements.
The PHB input can be used to force the UCC28063 to operate in single-phase mode. When PHB is driven below
0.8 V, channel B will stop switching and channel A on-time will automatically double to compensate. The device
will resume dual-phase mode when PHB is raised above 1.0 V. For customized phase management, an external
circuit can detect the conditions for switching to single-phase operation and drive PHB accordingly. To operate
continuously in two-phase mode (normal mode) when phase management is not desired, simply connect PHB to
VREF.
As load current decreases, the error amplifier commands less ac-line input current by lowering COMP voltage. In
applications where the ac-line is limited to the low-voltage range only, it may be advantageous to connect PHB
directly to COMP to allow automatic selection of single-phase operation without additional external circuitry.
External Disable
The UCC28063 can be externally disabled by purposefully grounding the VSENSE pin with an open-drain or
open-collector driver. When disabled, the device supply current drops significantly and COMP is actively pulled
low. This disable method forces the device into standby mode and minimizes its power consumption. This is
particularly useful when standby power is a key design aspect. When VSENSE is released, the device enters
soft-start mode.
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Improved Error Amplifier
The voltage-error amplifier is a transconductance amplifier. Voltage-loop compensation is connected from the
error amplifier output, COMP, to analog ground, AGND. The recommended Type-II compensation network is
shown in Figure 27. For loop-stability purposes, the compensation network values are calculated based on
small-signal perturbations of the output voltage using the nominal transconductance (gain) of 55 μS.
VREF
+
COMP
gM
VSENSE
CZ
CP
4.95V
RZ
Figure 27. Transconductance Error Amplifier with Typical Compensation Network
To improve the transient response to large perturbations, the error amplifier gain increases by a factor of ~5X
when the error amp input deviates more than ±5% from the nominal regulation voltage, VSENSEreg. This
increase allows faster charging and discharging of the compensation components following sudden load-current
increases or decreases (also refer to Figure 5 in the Typical Characteristics).
IEA
VSENSE
VREF
Figure 28. Basic Voltage-Error Amplifier Transconductance Curve
NOTE
Basic voltage-error amplifier transconductance curve showing
large-signal gain sections, with maximum current limitations.
small-signal
and
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Soft Start
Soft-start is a process for boosting the output voltage of the PFC converter from the peak of the ac-line input
voltage to the desired regulation voltage under controlled conditions. Instead of a dedicated soft-start pin, the
UCC28063 uses the voltage error amplifier as a controlled current source to increase the PWM duty-cycle by
way of increasing the COMP voltage. To avoid excessive start-up time-delay when the ac-line voltage is low, a
higher current is applied until VSENSE exceeds 3 V at which point the current is reduced to minimize the
tendency for excess COMP voltage at no-load start-up.
The PWM gradually ramps from zero on-time to normal on-time as the compensation capacitor from COMP to
AGND charges from zero to near its final value. This process implements a soft-start, with timing set by the
output current of the error amplifier and the value of the compensation capacitors. In the event of a HVSEN
FailSafe OVP, brownout, external-disable, UVLO fault, or other protection faults, COMP is actively discharged
and the UCC28063 will soft-start after the triggering event is cleared. Even if a fault event happens very briefly,
the fault is latched into the soft-start state and soft-start is delayed until COMP is fully discharged to 20 mV and
the fault is cleared. See Figure 29 for details on the COMP current. See Figure 30 which illustrates an example
of typical system behavior during soft-start.
ICOMP
OVP1 trigger. 2k pull -down
applied to COMP .
+63μA
+15μA
OVP1 reset. 2k pull -down
removed from COMP .
1.0
2.0
3.0
4.0
5.0
-15μA
6.0
7.0
VSENSE
COMP current limit
during Soft -Start only
(high-gain disabled )
-111 μA
Figure 29. Expanded COMP Output Current Curve
NOTE
Expanded COMP output current curve including voltage-error amplifier transconductance
and modifications applicable to soft-start and over-voltage conditions.
24
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OVERSHOOT
V
VSENSEREG
VENDofSS
VSENSE
VCOMPCLMP
COMP
VSSTHR
t
I AC-LINE
ICOMP
ISS,SLOW
ISS,FAST
HIGH GAIN ENABLED
SOFTSTART
Figure 30. Soft-Start Timing with Illustrative System Behavior
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Brownout Protection
As the power line RMS voltage decreases, RMS input current must increase to maintain a constant output
voltage for a specific load. Brownout protection helps prevent excess system thermal stress (due to the higher
RMS input current) from exceeding a safe operating level. Power-line voltage is sensed at VINAC. When the
VINAC fails to exceed the brownout threshold for the brownout filter time, a brownout condition is detected and
both gate drive outputs are turned off. During brownout, COMP is actively pulled low and a soft-start condition is
initiated. Hysteresis is built into the brownout detection circuit to avoid chatter around the threshold. When VINAC
rises above the brownout threshold, the power stage soft-starts as COMP rises with controlled current.
The brownout detection threshold and its hysteresis are set by the voltage-divider ratio and resistor values.
Brownout protection is based on VINAC peak voltage; the threshold and hysteresis are also based on the line
peak voltage. Major hysteresis is provided by a 2-μA current-sink (IBOHYS) enabled whenever VINAC falls below
the brownout detection threshold. Minor hysteresis is also present in the form of a 50-mV offset (VBOHYS)
between the VINAC detection and clear thresholds. The peak VINAC voltage can be easily translated into an
RMS value. Example resistor values for the voltage divider are 8.61 MΩ ±1% from the rectified input voltage to
VINAC and 133 kΩ ±1% from VINAC to ground. These resistors set the typical thresholds for RMS line voltages,
as shown in Table 1.
Table 1. Brownout Thresholds (for conditions stated in the text)
THRESHOLD
AC-LINE VOLTAGE (RMS)
Falling
66 V
Rising
78 V
Equation 8 and Equation 9 can be used to calculate the VINAC divider-resistor values based on desired
brownout detection and brownout clear voltage levels. VAC_OK is the desired RMS turn-on voltage, VAC_BO is the
desired RMS turn-off brownout voltage, and VLOSS is total series voltage drop due to wiring, EMI-filter, and
bridge-rectifier impedances at VAC_BO. VBODET, VBOHYS and IBOHYS are found in the data-tables of this datasheet.
2(VAC _ OK - VAC _ BO ) - VBOHYS ö÷ æ VBOHYS ö
ç 1+
÷
ç
֏
IBOHYS
VBODET ø
æ
RA = ç
è
RB =
ø
(8)
RA
æ 2VAC _ BO - VLOSS
ö
ç
- 1÷
ç
÷
VBODET
è
ø
(9)
Once standard values for the VINAC divider-resistors RA and RB are selected, the actual turn-on and brownout
threshold RMS voltages for the ac-line can be back-calculated with Equation 10 and Equation 11:
æ R öV
V
VAC _ BO = ç 1 + A ÷ BODET + LOSS
R
2
2
B ø
è
(10)
VAC _ OK
= VAC _ BO +
R AIBOHYS
æ
2 ç 1+
ç
è
VBOHYS ö
÷
VBODET ÷ø
+
VBOHYS
2
(11)
An example of the timing for the brownout function is illustrated in Figure 31.
For a quick estimation of the turn-on and brownout voltages, simplify the foregoing equations by setting the VLOSS
and VBOHYS terms to zero.
26
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Dropout Detection
It is often the case that the ac-line voltage momentarily drops to zero or nearly zero, due to transient abnormal
events affecting the local ac power distribution network. Referred to as ac-line dropouts (or sometimes as
line-dips) the duration of such events usually extends to only 1 or 2 line cycles. During a dropout, the
down-stream power conversion stages depend on sufficient energy storage in the PFC output capacitance, which
is sized to provide the ride-through energy for a specified hold-up time. Typically while the PFC output voltage is
falling, the voltage-loop error amplifier output rises in an attempt to maintain regulation. As a consequence,
excess duty-cycle is commanded when the ac-line voltage returns and high peak current surges may saturate
the boost inductors with possible overstress and audible noise.
The UCC28063 incorporates a dropout detection feature which suspends the action of the error amplifier for the
duration of the dropout. If the VINAC voltage falls below 0.35 V for longer than 5 ms, a dropout condition is
detected and the error amplifier output is turned off. In addition, a 4-μA pull-down current is applied to COMP to
gently discharge the compensation network capacitors. In this way, when the ac-line voltage returns, the COMP
voltage (and corresponding duty-cycle setting) remains very near or even slightly below the level it was before
the dropout occurred. Current surges due to excess duty-cycle, and their undesired attendant effects, are
avoided. The dropout condition is cancelled and the error amplifier resumes normal operation when VINAC rises
above 0.71 V.
Based on the VINAC divider-resistor values calculated for brownout in the previous section, the input RMS
voltage thresholds for dropout detection VAC_DO and dropout clearing VDO_CLR can be determined using
Equation 12 and Equation 13, below.
æR
ö
VDODET ç A + 1÷ + VLOSS
R
è B
ø
VAC _ DO =
2
(12)
æR
ö
VDOCLR ç A + 1÷ + VLOSS
è RB
ø
VDO _ CLR =
2
(13)
Avoid excessive filtering of the VINAC signal, or dropout detection may be delayed or defeated. An RC
time-constant of ≤ 100-μs should provide good performance. An example of the timing for the dropout function is
illustrated in Figure 32.
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VSENSE
COMP
IBOHYS
ON
VINAC
VBOCLR
VBODET
0V
t
BROWNOUT
DETECT
BROWNOUT
t BODLY
Figure 31. AC-Line Brownout Timing with Illustrative System Behavior
VSENSE
VINAC
COMP
VDOCLR
VDODET
0V
t
DROPOUT
tDODLY
Figure 32. AC-Line Dropout Timing with Illustrative System Behavior
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VREF
VREF is an output which supplies a well-regulated reference voltage to circuits within the device as well as
serving as a limited source for external circuits. This output must be bypassed to GND with a low-impedance
0.1-μF or larger capacitor placed as close to the VREF and GND pins as possible. Current draw by external
circuits should not exceed a few milli-amperes and should not be pulsing.
The VREF output is disabled under the following conditions: when VCC is in UVLO, or when VSENSE is below
the Enable threshold. This output can only source current and is unable to accept current into the pin.
VCC
VCC is usually connected to a bias supply of between 13 V and 21 V. To minimize switching ripple voltage on
VCC, it should be by-passed with a low-impedance capacitor as close to the VCC and GND pins as possible.
The capacitance should be sized to adequately decouple the peak currents due to gate-drive switching at the
highest operating frequency. When powered from a poorly-regulated low-impedance supply, an external zener
diode is recommended to prevent excessive current into VCC.
The undervoltage-lockout (UVLO) condition is when VCC voltage has not yet reached the turn-on threshold or
has fallen below the turn-off threshold, having already been turned on. While in UVLO, the VREF output and
most circuits within the device are disabled and VCC current falls significantly below the normal operating level.
The same situation applies when VSENSE is below its Enable threshold. This helps minimize power loss during
pre-powerup and standby conditions.
Control of Downstream Converter
In the UCC28063, the PWMCNTL pin can be used to coordinate the PFC stage with a downstream converter.
Through the HVSEN pin, the PFC output voltage is monitored. A 12-μA current source (IHV_HYS) is enabled as
long as the output voltage remains below a programmed threshold. When the output voltage exceeds that
threshold, PWMCNTL pin is pulled to ground internally and can be used to enable a downstream converter. At
the same time the current source is disabled, providing hysteresis for a lower threshold at which the downstream
converter should be turned off. The enable/disable hysteresis is adjusted through the HVSEN voltage-divider
ratio and resistor values. The HVSEN pin is also used for the FailSafe over-voltage protection (OVP). When
designing the voltage divider, make sure this FailSafe OVP level is set above normal VSENSE OVP levels.
Because there are two thresholds associated with the HVSEN input detected through a single resistor divider,
the PWMCNTL turn-off voltage, VPWM-OFF, is linked to the FailSafe OVP voltage, VFLSF_OV, as shown by
Equation 14:
VPWM-OFF VFLSF _ OV
=
2.5 V
4.87 V
(14)
Choosing either one first arbitrarily determines the other, so a trade-off may be necessary. The PWMCNTL
turn-on voltage, VPWM-ON, is programmed by choosing the upper divider resistor value in consideration with the
HVSEN hysteresis current, as shown in Equation 15 and Equation 16. The lower divider resistor is then
calculated as shown in Equation 17.
VPWM-ON = VPWM-OFF + IHV _ HYSRHV _ UPPER
(15)
V
- VPWM-OFF
RHV _ UPPER = PWM-ON
IHV _ HYS
RHV _ LOWER =
(16)
RHV _ UPPER
æ VPWM-OFF
ö
- 1÷
ç
è 2.5 V
ø
(17)
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SYSTEM LEVEL PROTECTIONS
FailSafe OVP - Output Over-Voltage Protection
FailSafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths
for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is
implemented through two independent paths: VSENSE and HVSEN. The converter shuts down if either input
senses a severe over-voltage condition. The output voltage can still remain below a safe limit if either sense path
fails. The device is re-enabled when both sense inputs fall back into their normal ranges. At that time, the gate
drive outputs will resume switching under PWM control. A low-level over-voltage on VSENSE does not trigger
soft-start, but the COMP pin is discharged by an internal 2-kΩ resistance until the output voltage falls below the
2% hysteresis OV-clear threshold. A higher-level over-voltage on VSENSE additionally shuts off the gate-drive
outputs until the OV clears, but still does not trigger a soft-start. However, an overvoltage detected on HVSEN
does trigger a full soft-start and the COMP pin is fully discharged to 20 mV before the soft-start can begin.
Over-Current Protection
Under certain conditions (such as inrush, brownout-recovery, and output over-load) the PFC power stage sees
large currents. It is critical that the power devices be protected from switching during these conditions.
The conventional current-sensing method uses a shunt resistor in series with each MOSFET source leg to sense
the converter currents, resulting in multiple ground points and high power dissipation. Furthermore, since no
current information is available when the MOSFETs are off, the source-resistor current-sensing method results in
repeated turn-on of the MOSFETs during over-current (OC) conditions. Consequently, the converter may
temporarily operate in continuous conduction mode (CCM) and may experience failures induced by excessive
reverse-recovery currents in the boost diodes or other abnormal stresses.
The UCC28063 uses a single resistor to continuously sense the combined total inductor (input) current. This
way, turn-on of the MOSFETs is completely avoided when the inductor currents are excessive. The gate drive to
the MOSFETs is inhibited until total inductor current drops to near zero, precluding reverse-recovery-induced
failures (these failures are most likely to occur when the ac-line recovers from a brownout condition).
The nominal OC threshold voltage during two-phase operation is -200 mV, which helps minimize losses. This
threshold is automatically reduced to -166 mV during single-phase operation, either by detection of a phase
failure or because PHB is driven below 0.8 V. Note that the single-phase threshold is not simply 1/2 of the
dual-phase threshold, because the ratio of the single-phase peak current to the interleaved peak current is higher
than 1/2.
An OC condition immediately turns off both gate-drive outputs, but does not trigger a soft-start and does not
modify the error amplifier operation. The over-current condition is cleared when the total inductor current-sense
voltage falls below the OC-clear threshold (-15 mV).
Following an over-current condition, both MOSFETs are turned on simultaneously once the input current drops to
near zero. Because the two phase currents are temporarily operating in-phase, the current-sense resistance
should be chosen so that OC protection is not triggered with twice the maximum current peak value of either
phase in order to allow quick return to normal operation after an over-current event. Automatic phase-shift control
will re-establish interleaving within a few switching cycles.
30
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Open-Loop Protection
If the feedback loop is disconnected from the device, a 100-nA current source internal to the UCC28063 pulls the
VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device becomes disabled. When
disabled, the bias supply current decreases, both gate-drive outputs and COMP are actively pulled low, and a
soft-start condition is initiated. The device is re-enabled when VSENSE rises above 1.25 V. At that time, the gate
drive outputs will begin switching under soft-start PWM control.
If the feedback loop is disconnected from ground, the VSENSE voltage will be pulled high. When VSENSE rises
above the 2nd-level over-voltage protection threshold, both gate drive outputs are shut off and COMP is actively
pulled low. The device is re-enabled when VSENSE falls below the OV-clear threshold. The VSENSE input can
tolerate a limited amount of current into the device under abnormally high input voltage conditions. Refer to the
Absolute Maximum Ratings table near the beginning of this datasheet for details.
VCC Under-Voltage Lock-Out (UVLO) Protection
VCC must rise above the turn-on threshold for the PWM to begin functioning. If VCC drops below the UVLO
threshold during operation, both gate-drive outputs are actively pulled low, COMP is actively pulled low, and a
soft-start condition is triggered. VCC must again rise above the turn-on threshold for the PWM function to restart
in soft-start mode.
Phase-Fail Protection
The UCC28063 detects failure of either of the phases by monitoring the sequence of ZCD pulses. During normal
two-phase operation, if one ZCD input remains idle for longer than approximately 12 ms while the other ZCD
input switches normally, the over-current threshold is reduced and PWMCNTL goes to a high-impedance state,
indicating that the PFC power stage is not operating correctly. During normal single-phase operation (PHB < 0.8
V), phase failure is not monitored. Also on the UCC28063, phase failure is not monitored when COMP is below
approximately 222 mV.
CS-Open, TSET-Open & -Short Protection
In the event that the CS input becomes open-circuited, the UCC28063 detects this condition and will shutdown
the outputs and trigger a full-soft-start condition. In the event that the TSET input becomes either open-circuited
or short-circuited to GND, the UCC28063 detects these conditions and will shutdown the outputs and trigger a
full-soft-start condition. Normal operation will resume (with a soft-start) when the fault clears.
Thermal Shutdown Protection
Overloading of the gate-drive outputs and/or VREF can dissipate excess power within the device which may
raise the internal temperature of the circuits beyond a safe level. Even normal power dissipation can generate
excess heat if the thermal impedance is too high or the ambient temperature is too high. When the UCC28063
detects an internal over-temperature condition it will shutdown the outputs and trigger a full soft-start condition.
When the internal device junction temperature has cooled below the thermal hysteresis temperature, operation
will resume under soft-start control.
AC-Line Brownout and Dropout Protections
See specific discussions for each topic in previous sections (above) of this datasheet.
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Fault Logic Diagram
Figure 33 depicts the fault-handling logic involving VSENSE, COMP, and several internal states.
PHASE_B_OFF
STOP GDB
OC
STOP GDA
HIGH _OV
BROWNOUT
HVSEN_OV
UVLO
EN
TSET_FLT
CS_OPEN
TSD
HIGH_OV Latch
S Q
6.67V
COMP Discharge Latch
S Q
+
R
R
Q
Q
LOW _OV Latch
S Q
6.48V
+
+
20mV
6.36V
R
+
Q
OV-Clear
COMP
4μA
2kΩ
1.25V
EN
+
LOW_OV
DIS _EA
DROPOUT
Gain -Disable Latch
S Q
VCC
DIS _High_Gain
+
R
5.9V
VSENSE
Q
+
3.0V
Figure 33. Fault Logic with VSENSE Detections and Error Amplifier Control
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DESIGN EXAMPLE
An example of the UCC28063 PFC controller in a two-phase interleaved, transition-mode PFC pre-regulator is
shown in Figure 34.
Bridge
+
D3
CIN
–
RS
12V
CA
R
100
F1
RZA
2.2uF
CF1
1 nF
RP
50 k
VCC
RG1
5
RZB
UCC28063
VREF
CB
2.2uF
Q1
GDA
VINAC
RB
VOUT
ZCDA
PWMCNTL
PWMCNTL
CF2
D1
22pF
CS
RA
L1
20 k
CF4
RLOAD
20 k
CF5
D2
ZCDB
PHB
COMP
COUT
L2
RG2
22pF
Q2
GDB
5
RC
RE
RD
RF
HVSEN
RZ
TSET
VSENSE
CP
RT
CF3
CZ
AGND
PGND
Figure 34. Typical Interleaved Transition-Mode PFC Pre-Regulator
Design Goals
The specifications for this design were chosen based on the power requirements of a typical 300-W LCD TV.
These specifications are shown in Table 2.
Table 2. Design Specifications
PARAMETER
MIN
TYP
VIN
RMS input voltage
VOUT
Output voltage
fLINE
AC-line frequency
PF
Power factor at maximum load
0.90
η
Full-load efficiency
92%
fMIN
Minimum switching frequency
MAX
85
(VIN_MIN)
UNIT
265
(VIN_MAX)
VRMS
390
47
POUT
V
63
Hz
300
W
45
kHz
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Recommended PCB Device Layout
CF4
Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current,
allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input
and output filter capacitors should be located after the two phase currents are combined together. Similar to
other power management devices, when laying out the printed circuit board (PCB) it is important to use star
grounding techniques and keep filter capacitors as close to device ground as possible. To minimize the
interference caused by capacitive coupling from the boost inductor, the device should be located at least 1 in
(25.4 mm) away from the boost inductor. It is also recommended that the device not be placed underneath
magnetic elements. Because of the precise timing requirement, timing-setting resistor RT should be placed as
close as possible to the TSET pin and returned to the analog ground. See Figure 35 for a recommended
component placement and layout.
Figure 35. Recommended PCB Layout
NOTE
PHB and VREF pins are connected by a jumper on the back of the board.
34
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Inductor Selection
The boost inductor is selected based on the inductor ripple current requirements at the peak of low line.
Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (DPEAK_LOW_LINE),
as shown in Equation 18.
DPEAK _ LOW _ LINE =
VOUT - VIN_MIN 2
VOUT
=
390 V - 85 V 2
» 0.69
390 V
(18)
The minimum switching frequency of the converter (fMIN) under low line conditions occurs at the peak of low line
and is set between 25 kHz and 50 kHz to avoid audible noise. For this design example, fMIN is set to 45 kHz. For
a 2-phase interleaved design, L1 and L2 are determined as shown in Equation 19.
L1 = L2 =
h ´ VIN _ MIN2 ´ DPEAK _ LOW _ LINE
POUT ´ fMIN
=
0.92(85 V)2 0.69
» 340 mH
300 W ´ 45kHz
(19)
The inductor for this design would have a peak current (ILPEAK) of 5.4 A, as shown in Equation 20, and an RMS
current (ILRMS) of 2.2 A, as shown in Equation 21.
ILPEAK =
ILRMS =
POUT 2
300 W 2
=
» 5.4 Apk
VIN _ MIN ´ h 85 V ´ 0.92
ILPEAK
6
=
5.4 A
6
(20)
» 2.2 Arms
(21)
This converter uses constant on time (TON) and zero-current detection (ZCD) to set up the converter timing.
Auxiliary windings on L1 and L2 detect when the inductor currents are zero. Selecting the turns ratio using
Equation 22 ensures that there will be at least 2 V at the peak of high line to reset the ZCD comparator after
every switching cycle.
The turns-ratio of each auxiliary winding is:
NP VOUT - VIN_MAX 2 390 V - 265 V 2
=
=
»8
Ns
2V
2V
(22)
ZCD Resistor Selection (RZA, RZB)
The minimum value of the ZCD resistors is selected based on the internal clamps maximum current ratings of 3
mA, as shown in Equation 23.
V
N
390 V
R ZA = R ZB ³ OUT S =
» 16.3kW
NP ´ 3mA 8 ´ 3mA
(23)
In this design the ZCD resistors are set to 20 kΩ, as shown in Equation 24.
R ZA = R ZB = 20kW
(24)
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HVSENSE
The HVSENSE pin programs the PWMCNTL output of the UCC28063. The PWMCNTL open-drain output can be
used to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts high
impedance and pulls to ground when HVSEN increases above 2.5 V. Setting the point where PWMCNTL
becomes active requires a voltage divider from the boost voltage to the HVSEN pin to ground. Equation 25 to
Equation 30 show how to set the PWMCNTL pin to activate when the output voltage is within 90% of its nominal
value.
VOUT _ OK = VOUT ´ 0.90 » 351 V
(25)
Resistor RE sets up the high side of the voltage divider and programs the hysteresis of the PWMCNTL signal.
For this example, RE was selected to provide 99 V of hysteresis, as shown in Equation 26. Three resistors in
series were used to meet voltage requirements.
Hysteresis
99 V
RE =
=
= 8.25MW » 3 ´ 2.74MW
12 mA
12 mA
(26)
Resistor RF is used to program the PWMCNTL active threshold, as shown in Equation 27.
2.5 V
2.5 V
RF =
=
= 82.25kW
VOUT _ OK - 2.5 V
351V - 2.5 V
- 12 mA
- 12 mA
8.22MW
RE
(27)
Select a standard resistor value for RF.
RF = 82.5kW
(28)
This PWMCNTL output will remain active until a minimum output voltage (VOUT_MIN) is reached, as shown in
Equation 29.
VOUT _ MIN =
2.5 V (RE + RF ) 2.5 V (8.22MW + 82.5kW )
=
» 252 V
RF
82.5kW
(29)
According to these resistor values, the FailSafe OVP threshold will be set according to Equation 30
VOV _ FAILSAFE =
36
4.87 V (RE + RF ) 4.87 V (8.22MW + 82.5kW )
=
» 490 V
RF
82.5kW
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Output Capacitor Selection
The output capacitor (COUT) is selected based on holdup requirements, as shown in Equation 31.
POUT 1
300 W 1
2
h fLINE
0.92 47Hz
³
=
» 156 mF
2
2
VOUT - (VOUT _ MIN )
390 V 2 - (252 V)2
2
COUT
(31)
Two 100-μF capacitors were used in parallel for the output capacitor.
COUT = 200 mF
(32)
For this size capacitor, the low-frequency peak-to-peak output voltage ripple (VRIPPLE) is approximately 14 V, as
shown in Equation 33:
2 ´ POUT
1
2 ´ 300 W
VRIPPLE =
=
» 14 Vppk
VOUT ´ 4p ´ fLINE ´ COUT 0.92 ´ 390 V ´ 4p ´ 47Hz ´ 200 mF
h
(33)
In addition to holdup requirements, a capacitor must be selected so that it can withstand the low-frequency RMS
current (ICOUT_100Hz) and the high-frequency RMS current (ICOUT_HF); see Equation 34 to Equation 36.
High-voltage electrolytic capacitors generally have both a low- and a high-frequency RMS current ratings on the
product data sheets.
POUT
300 W
ICOUT _100Hz =
=
= 0.591 Arms
VOUT ´ h ´ 2 390 V ´ 0.92 ´ 2
(34)
ICOUT _ HF
æ
POUT 2 2
= ç
çç 2 ´ h ´ VIN _ MIN
è
æ 300 W ´ 2 2
ICOUT _ HF = ç
ç 2 ´ 0.92 ´ 85 V
è
2
4 2VIN _ MIN ö
÷ - I
COUT _100Hz
9pVOUT ÷÷
ø
(
2
)
(35)
2
4 2 ´ 85 V ö
÷ - (0.591A )2 » 0.966 Arms
9p ´ 390 V ÷
ø
(36)
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Selecting (RS) for Peak Current Limiting
The UCC28063 peak limit comparator senses the total input current and is used to protect the MOSFETs during
inrush and over-load conditions. For reliability, the peak current limit (IPEAK) threshold in this design is set for
120% of the nominal maximum current that will be observed during power up, as shown in Equation 37.
IPEAK =
2POUT 2(1.2) 2 ´ 300 W 2 ´ 1.2
=
» 13 A
h ´ VIN _ MIN
0.92 ´ 85 V
(37)
A standard 15-mΩ metal-film current-sense resistor will be used for current sensing, as shown in Equation 38.
The estimated power loss of the current-sense resistor (PRS) is less than 0.25 W during normal operation, as
shown in Equation 39.
RS =
200mV 200mV
=
» 15mΩ
IPEAK
13 A
2
PRS
(38)
2
æ POUT ö
æ 300 W ö
=ç
÷÷ RS = ç
÷ ´ 15mW » 0.22 W
çV
è 85 V ´ 0.92 ø
è IN_MIN ´ h ø
(39)
The most critical parameter in selecting a current-sense resistor is the surge rating. The resistor needs to
withstand a short-circuit current larger than the current required to open the fuse (F1). I2t (ampere-squaredseconds) is a measure of thermal energy resulting from current flow required to melt the fuse, where I2t is equal
to RMS current squared times the duration of the current flow in seconds. A 4-A fuse with an I2t of 14 A2s was
chosen to protect the design from a short-circuit condition. To ensure the current-sense resistor has high-enough
surge protection, a 15-mΩ, 500-mW, metal-strip resistor was chosen for the design. The resistor has a 2.5-W
surge rating for 5 seconds. This result translates into 833 A2s and has a high-enough I2t rating to survive a
short-circuit before the fuse opens, as described in Equation 40.
2.5 W
I2 t =
´ 5s = 833 A 2 s
0.015 W
(40)
Power Semiconductor Selection (Q1, Q2, D1, D2)
The selection of Q1, Q2, D1, and D2 are based on the power requirements of the design. Application note
SLUU138, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator, explains how to
select power semiconductor components for transition-mode PFC pre-regulators.
The MOSFET (Q1, Q2) pulsed-drain maximum current is shown in Equation 41:
IDM ³ IPEAK = 13 A
(41)
The MOSFET (Q1, Q2) RMS current calculation is shown in Equation 42:
IDS =
IPEAK
2
1 4 2 VIN _ MIN 13 A
=
6
9p ´ VOUT
2
1 4 2 ´ 85 V
» 2.3 A
6 9p ´ 390 V
(42)
To meet the power requirements of the design, IRFB11N50A 500-V MOSFETs were chosen for Q1 and Q2.
The boost diode (D1, D2) RMS current is shown in Equation 43:
I
ID = PEAK
2
4 2 ´ VIN _ MIN
9p ´ VOUT
=
13 A
2
4 2 ´ 85 V
» 1.4 A
9p ´ 390 V
(43)
To meet the power requirements of the design, MURS360T3, 600-V diodes were chosen for D1 and D2.
38
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Brownout Protection
Resistor RA and RB are selected to activate brownout protection at ~75% of the specified minimum-operating
input voltage. Resistor RA programs the brownout hysteresis comparator, which is selected to provide 17 V (~12
VRMS) of hysteresis. Calculations for RA and RB are shown in Equation 44 through Equation 47.
Hysteresis 17 V
RA =
=
= 8.5MW
2 mA
2 mA
(44)
To meet voltage requirements, three 2.87-MΩ resistors were used in series for RA.
R A = 3 ´ 2.87MW = 8.61MW
RB =
1.4 V ´ R A
VIN _ MIN ´ 0.75 2 - 1.4 V
=
1.4 V ´ 8.61MW
85 V ´ 0.75 2 - 1.4 V
(45)
= 135.8kW
(46)
Select a standard value for RB.
RB = 133kW
(47)
In this design example, brownout becomes active (shuts down PFC) when the input drops below 66 VRMS for
longer than 440 ms and deactivates (restarts with a full soft start) when the input reaches 78 VRMS.
Converter Timing
The maximum on-time TON depends on fMIN as determined by Equation 48. To ensure proper operation, the
timing must be set based on the highest boost inductance (L1MAX) and output power (POUT). In this design
example, the boost inductor could be as high as 390 µH. Calculate the timing resistor RT as shown in
Equation 49.
VIN _ MIN ´ 2 ö
æ
ö
÷ 0.92 ´ (85 V )2 ç 1 - 85 V ´ 2 ÷
÷
ç
÷
VOUT
390 V ø
è
ø=
è
= 39.2kHz
POUT ´ L1MAX
300 W ´ 390 mH
h ´ VIN _ MIN
(
fMIN =
2æ
) çç1 -
æ
VIN _ MIN ´ 2 ö
æ
ö
÷ 133kW ç 1 - 85 V ´ 2 ÷
133kW ç 1 ç
÷
ç
÷
Vout
390 V ø
è
ø=
è
RT =
» 121kW
4 ms
4 ms
4.85 V ´
4.85 V ´
´ fMIN
´ 39.2kHz
V
V
(48)
(49)
This result sets the maximum frequency clamp (fMAX), as shown in Equation 50, which improves efficiency at light
load.
133kW
133kW
fMAX =
=
» 550kHz
2 ms ´ RT 2 ms ´ 121kW
(50)
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Programming VOUT
Resistor RC is selected to minimize loading on the power line when the PFC is disabled. Construct resistor RC
from two or more resistors in series to meet high-voltage requirements. Resistor RD is then calculated based on
RC, the reference voltage, VREF, and the required output voltage, VOUT. Based on the values shown in
Equation 51 to Equation 54, the primary output over-voltage protection threshold should be as shown in
Equation 55:
RC = 2.74MW + 2.74MW + 3.01MW = 8.49MW
(51)
VREF = 6 V
(52)
VREF ´ RC
6 V ´ 8.49MW
RD =
=
= 132.7kW
VOUT - VREF
390 V - 6 V
(53)
Select a standard value for RD.
RD = 133kW
(54)
R + RD
8.49MW + 133kW
VOVP = 6.48 V C
= 6.48 V
= 420.1V
RD
133kW
(55)
Voltage Loop Compensation
Resistor RZ is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This
value ensures good power factor and low harmonic distortion on the input current.
The transconductance amplifier small-signal gain is shown in Equation 56:
gm = 50 mS
(56)
The voltage-divider feedback gain is shown in Equation 57:
V
6V
H = REF =
» 0.015
VOUT 390 V
(57)
The value of RZ is calculated as shown in Equation 58:
100mV
100mV
RZ =
=
= 9.52 kW
VRIPPLE ´ H ´ gm 14 V ´ 0.015 ´ 50 mS
(58)
CZ is then set to add 45° phase margin at 1/5th of the line frequency, as shown in Equation 59:
1
1
CZ =
=
= 1.78 mF
fLINE
47Hz
´ 9.52kW
2p ´
´ R Z 2p ´
5
5
(59)
CP is sized to attenuate high-frequency switching noise, as shown in Equation 60:
1
1
Cp =
=
= 770pF
f
45kHz
´ 9.52kW
2p ´ MIN ´ R Z 2p ´
2
2
(60)
Standard values should be chosen for RZ, CZ and CP, as shown in Equation 61 to Equation 63.
R Z = 9.53kW
(61)
40
CZ = 2.2 mF
(62)
CP = 820pF
(63)
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ADDITIONAL REFERENCES
Related Parts
Table 3 lists several TI parts that have characteristics similar to the UCC28063.
Table 3. TI Related Parts
DEVICE
DESCRIPTION
UCC28050/51
Transition-mode PFC controller for low to medium power applications
UCC28019
8-pin continuous-conduction-mode (ccm) pfc controller (with slew-rate correction current)
UCC28019A
8-pin continuous-conduction-mode (ccm) pfc controller (with 2-level voltage-error gain)
UCC28060
Two-phase interleaved transition-mode pfc controller (with input voltage range gain change)
UCC28061
Two-phase interleaved transition-mode pfc controller (with no input voltage gain change)
UCC28070
Two-phase interleaved ccm (average current mode) pfc controller
References
These references, design tools, and links to additional references, including design software, may be found at
www.power.ti.com
1. Evaluation Module, UCC28063EVM 300W Interleaved PFC Pre-regulator, SLUU512 from Texas Instruments
2. Application Note, UCC38050 100-W Critical Conduction Power Factor Corrected (PFC) Pre-regulator,
SLUU138 from Texas Instruments
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Sep-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
UCC28063D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
UCC28063DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
(3)
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Sep-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
UCC28063DR
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
10.3
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Sep-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
UCC28063DR
SOIC
D
16
2500
333.2
345.9
28.6
Pack Materials-Page 2
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User's Guide
SLUU512 – August 2011
UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
The UCC28063 is a dual-phase, transition-mode Power Factor Correction (PFC) pre-regulator. The
UCC28063EVM-723 is an evaluation module (EVM) with a 390-V, 300-W, dc output that operates from a
universal input of 85 VRMS to 265 VRMS and provides power-factor correction.
Throughout this document, the acronym EVM and the phrases evaluation board and evaluation module
are synonymous with the UCC28063EVM.
1
Description
The pre-regulator uses the UCC28063 PFC interleaved controller to shape the input current wave to
provide power-factor correction. This device uses TI’s Natural Interleaving ™ technology to interleave
boost phases.
This user’s guide provides the schematic, List of Materials, assembly drawing for a single-sided printed
circuit board application, and test set-up information necessary to evaluate the UCC28063 in a typical
PFC application.
2
Thermal Requirements
This evaluation module will operate up to 300 W without external cooling in ambient tempatures of 25°C.
3
Electrical Characteristics
Table 1 summarizes the electrical specifications of the UCC28063EVM-723.
Table 1. UCC28063EVM-723 Electrical Specifications
PARAMETER
CONDITIONS
RMS input voltage (ac line)
UCC28063EVM
MIN
TYP
85
Output voltage, VOUT
MAX
UNITS
265
VRMS
63
Hz
300
W
390
Line frequency
47
Power factor (PF) at maximum load
0.9
Output power
Full load efficiency
AC line = 115 V
94%
AC line = 230 V
97%
V
Natural Interleaving is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
SLUU512 – August 2011
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1
Schematics
4
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Schematics
Figure 1 and Figure 2 show the schematics for this EVM. See the List of Materials for specific values.
+
+
To evaluate inductor ripple currents, resistors R25 and R26 can be removed and replaced with current
loops.
Figure 1. Interleaved PFC Power Stage
2
UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
Copyright © 2011, Texas Instruments Incorporated
SLUU512 – August 2011
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Schematics
+
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Figure 2. Controller Circuitry
SLUU512 – August 2011
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UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
Copyright © 2011, Texas Instruments Incorporated
3
Test Setup and Power-Up/Power-Down Instructions
5
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Test Setup and Power-Up/Power-Down Instructions
WARNING
There are high voltages present on the pre-regulator. It should only
be handled by experienced power supply professionals. To
evaluate this board as safely as possible, the following test
configuration should be used:
• Connect an isolation transformer between the source and unit
• Attach a voltmeter and a resistive or electronic load to the unit
output before supplying power to the EVM.
A separate 13-V bias supply is required to power the UCC28063 control circuitry. The unit will start up
under no-load conditions. However, for safety, a load should be connected to the output of the device
before it is powered up. The unit should also never be handled while power is applied to it or when the
output voltage is above 50-V dc. Refer to Figure 3 for a recommended test setup diagram.
CAUTION
There are very high voltages on the board. Components can and will reach
temperatures greater than 100°C. Use caution when handling the EVM.
4
UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
Copyright © 2011, Texas Instruments Incorporated
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Test Setup and Power-Up/Power-Down Instructions
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VM
0 to 300W Load
TEXAS
I NSTRUMENTS
Isolation Transformer
+
13V Bias Supply
Figure 3. Test Setup
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UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
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5
Typical Performance Data
6
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Typical Performance Data
Figure 4 through Figure 7 present characteristic performance data for the UCC28063EVM-723.
Efficiency
Efficiency at Vin = 115Vrms
100.0
100.0
99.0
99.0
98.0
97.0
Efficiency (%)
Efficiency (%)
98.0
96.0
95.0
94.0
93.0
97.0
96.0
95.0
94.0
93.0
92.0
92.0
91.0
91.0
90.0
10
20
30
40
50
60
70
80
90
90.0
100
10
Output Power (%)
20
30
40
50
60
70
80
90
100
Output Power (%)
Efficiency at Vin 85Vrms
Efficiency at Vin 265Vrms
Phase Management Disabled
Figure 4. Efficiency at 85 VRMS and 265 VRMS
Figure 5. Efficiency at 115 VRMS, Without Phase
Management
Efficiency at Vin = 230Vrms
Current Harmonics
Vin = 230V RMS, Pout = 300W
100.0
1.40706
99.0
1.17256
97.0
EN61000-3-2 SPEC
96.0
Amplitude
Efficiency (%)
98.0
95.0
94.0
93.0
92.0
0.93805
0.70354
0.46904
91.0
0.23453
90.0
10
20
30
40
50
60
70
80
90
Output Power (%)
Phase Management Disabled
100
0.00002
0
3
6
9 12 15 18 21 24 27 30 33 36 39 42 45 48
Harmonic Number
Figure 6. Efficiency at 230 VRMS, Without Phase
Management
6
Figure 7. Current Harmonics
UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
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Typical Performance Data
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6.1
Output Ripple Voltage at Full Load
Figure 8 illustrates the output ripple voltage.
Figure 8. VOUT Ripple, POUT = 300 W
6.2
Input Ripple Current Cancellation
Figure 9 through Figure 14 show the input current (M1= IL1 + IL2), Inductor Ripple Current (IL1, IL2) versus
rectified line voltage. From these graphs, it can be observed that interleaving reduces the magnitude of
input ripple current caused by the inductor ripple current.
Figure 9. Inductor and Input Ripple Current at 85 VRMS Figure 10. Inductor and Input Ripple Current at 85 VRMS
at Peak of Line Voltage
Input at Half the Line Voltage
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7
Typical Performance Data
8
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Figure 11. Inductor and Input Ripple Current at 265
VRMS Input at Peak Line Voltage
Figure 12. Inductor and Input Ripple Current at 265
VRMS Input at Half Peak Line Voltage
Figure 13. Inductor and Input Ripple Current at VIN =
85 VRMS, POUT = 300 W
Figure 14. Inductor and Input Ripple Current at VIN =
265 VRMS, POUT = 300 W
UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
Copyright © 2011, Texas Instruments Incorporated
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Typical Performance Data
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6.3
Startup Characteristics
Figure 15 and Figure 16 illustrate the UCC28063EVM-723 startup characteristics.
Figure 15. Start-Up at VIN = 85 VRMS,
POUT = 300 W
6.4
Figure 16. Start-Up at VIN = 265 VRMS,
POUT = 0 W
Brownout Protection
The UCC28063 has a brownout protection that shuts down both gate drives (GDA and GDB) when the
VINAC pin detects that the RMS input voltage is too low. This EVM was designed to go into a brownout
state when the line drops below 64 VRMS. Once the UCC28063 control device has determined that the
input is in a brownout condition, a 400-ms timer starts to allow the line to recover before shutting down the
gate drivers. After 400 ms of brownout, both gate drivers turn off, as shown in Figure 17 and Figure 18.
VOUT
C3
15.2VPP
Rectified Line Voltage After the Bridge Rectifier C3
9.67VRMS
GDA
GDB
Figure 17. Brownout at 85 VRMS
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Figure 18. Brownout at 265 VRMS
UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
Copyright © 2011, Texas Instruments Incorporated
9
Typical Performance Data
6.5
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Line Transient
A line transient test was conducted with an ac source on the reference design. The line was varied from
230 VRMS to 115 VRMS to 230 VRMS and the transient response was evaluated in each case. From the
oscilloscope image in Figure 19, it can be observed that the output recovered from line transients within
300ms at full load.
Figure 19. Line Transient, POUT = 300W
10
UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
Copyright © 2011, Texas Instruments Incorporated
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Reference Design Assembly Drawing
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7
Reference Design Assembly Drawing
Figure 20 and Figure 22 show the top and bottom layers (respectively) of the UCC28063EVM-723.
NOTE: Board layouts are not to scale. These figures are intended to show how the board is laid out;
they are not intended to be used for manufacturing UCC28063EVM-723 PCBs.
TEXAS
I NSTRUMENTS
Figure 20. Top Layer Assembly
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11
Reference Design Assembly Drawing
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Figure 21. Bottom Layer Copper
12
UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
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Reference Design Assembly Drawing
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Figure 22. Bottom Layer Assembly
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UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
Copyright © 2011, Texas Instruments Incorporated
13
List of Materials
8
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List of Materials
Table 2 lists the EVM components as configured according to the schematics (see Section 4).
Table 2. List of Materials
COUNT
14
REF DES
DESCRIPTION
PART NUMBER
MFR
4
AC_LINE,
AC_NEUTRAL,
RETURN, VOUT
Terminal block, 2 pin, 15 A, 5.1 mm
ED120/2DS
OST
1
C1
Capacitor, film, 275VAC, 20±%, 0.1 μF, 0.689 x
0.236 inch
ECQU2A104BC1
Panasonic
1
C11
Capacitor, ceramic, 16 V, X7R, 10%, 220 nF,
1206
Std
Std
2
C12, C13
Capacitor, ceramic, 16 V, X7R, 10%, 2.2 μF,
0805
Std
Std
1
C14
Capacitor, aluminum, 35 V, ±20%, 22 μF, 0.200 * ECA-1VM220
0.435 inch
Panasonic
1
C15
Capacitor, ceramic, 25 V, X7R, 10%, 820 pF,
0805
Std
Std
1
C17
Capacitor, ceramic, 25 V, X7R, 10%, 10 nF,
0805
Std
Std
1
C2
Capacitor, polyester, 630 V, 10%, 0.047 μF,
0.256 x 0.650 inch
ECQ-E6473KZ
Panasonic
2
C3, C4
Capacitor, aluminum, 450 VDC, ±20% , 100 μF,
18 x 40 mm
EKXG451ELL101
MM40S
Nippon
Chemi-con
2
C5, C6
Capacitor, film, 275 VAC, 20±%, 0.47 μF, 0.236
X 0.591
ECQ-U2A474MG
Panasonic
2
C7, C10
Capacitor, ceramic, 25 V, X7R, 10%, 22 pF,
0805
Std
Std
3
C8, C9, C16
Capacitor, ceramic, 25 V, X7R, 10%, 1.2 nF,
0805
Std
Std
3
D1, D2, D4
Diode, 3000 mA, 600 V, SMC
MURS360T3
On Semi
1
D3
Diode, bridge, 6 A, 600 V, BU6
GBU6J
Vishay
2
F1
Fuse clip, 5x20 mm
0100056H
Wickmann
3
HS1, HS2, HS3
Heatsink, universal-mount TO-220, 7-345-2PP,
1.500 x 2.000 inch
7-345-2PP
IERC-CTS
1
J1
Terminal block, 2 pin, 15 A, 5.1 mm,
ED1609-ND, 0.40 x 0.35 inch
ED1609
OST
3
JP1, JP2, JP3
Jumper, 2.000 inch length, PVC insulation, AWG
22, 0.035 inch dia.
923345-20-C
3M
1
JP4
Jumper, 2.100 inch length, PVC insulation, AWG
22, 0.035 inch dia.
923345-21-C
3M
1
JP5
Jumper, 0.500 inch length, PVC insulation, AWG
22, 0.035 inch dia
923345-05-C
3M
2
JP6, JP8
Jumper, 0.700 inch length, PVC insulation, AWG
22
923345-07-C
3M
1
JP7
Jumper, 0.100 inch length, non-insulated, AWG
22
923345-01-C
3M
1
JP10
Header, 2-pin, 100-mil spacing, 0.100 inch x 2
PEC02SAAN
Sullins
1
JP9
Jumper, 1.2 inch length, PVC insulation, AWG
22, 0.035 inch dia.
923345-20-C
3M
2
L1, L2**
Inductor, boost PFC with aux. 330 uH @ 5.3 A
PK, 1.555 Dia. inch
CTX16-17769R
Cooper
2
Q1, Q2
MOSFET, N-channel, 500 V, 11 A, 520 mΩ,
TO-220V
IRFB11N50APbF
IR
UCC28063EVM-723 300-W Interleaved PFC Pre-Regulator
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List of Materials
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Table 2. List of Materials (continued)
COUNT
REF DES
DESCRIPTION
PART NUMBER
MFR
1
R1
Resistor, chip, 1/10 W, 1%, 51.1 Ω, 0805
Std
Std
2
R11, R14
Resistor, chip, 1/10 W, 1%, 20.5 kΩ, 0805
Std
Std
2
R12, R13
Resistor, chip, 1/10 W, 1%, 133 kΩ, 0805
Std
Std
1
R15
Resistor, chip, 1/10 W, 1%, 121 kΩ, 0805
Std
Std
2
R16, R19
Resistor, chip, 1/10 W, 1%, 5.11 Ω, 0805
Std
Std
1
R18
Resistor, chip, 1/10 W, 1%, 9.53 kΩ, 0805
Std
Std
3
R2, R4, R17
Resistor, chip, 1/10 W, 1%, 10.0 kΩ, 0805
Std
Std
1
R23
Resistor, chip, 1/10 W, 1%, 82.5 kΩ, 0805
Std
Std
1
R24
Resistor, chip, 1/10 W, 1%, 100 Ω, 0805
Std
Std
2
R25, R26
Resistor, chip, 1 W, 5%, 0 Ω, 2512
Std
Std
1
R3
Resistor, chip, 1/2 W, 1%, 0.015 Ω, 2010
WSL2010R0150F
EA
Vishay
3
R5, R6, R7
Resistor, Chip, 1/10 W, 1%, 2.87 MΩ
Std
Std
5
R8, R9, R20, R21, R22
Resistor, chip, 1/10 W, 1%, 2.74 MΩ, 0805
Std
Std
1
R10
Resistor, Chip, 1/10 W, 1%, 3.01 MΩ, 0805
Std
Std
1
RT1
Thermistor, NTC, 5 Ω, 6 A, 5 Ω, 0.180 X 0.550
inch
CL-40
Thermometrics
2
TP1, TP2
Pin, thru hole, tin plate, for 0.062 PCB's,
K24A/M, 0.039 inch
K24A/M
Vector
1
U1
Interleave PFC Controller, SO16
UCC28063D
TI
1
VAR1
Varistor 275 V RMS, 0.472 x 0.213 inch
S10K275E2
Epcos
1
PCB
HPA343 printed circuit board
HPA343
1
X1 @ F1
4 A, fast acting fuse, BK/GDA-4A, 5mmX20mm
BK/S501-4-R
Cooper/Bussman
6
"X1 @ HS1 and D3,
HS2 and Q1, HS3 and
Q2"
Nut #4-40 (steel)
Std
Std
6
"X1 @ HS1 and D3,
HS2 and Q1, HS3 and
Q2"
Pan head screw #4-40X3/8 (steel)
Std
Std
1
X1 D3 and HS1
Thermal grease
Std
Std
6
"X1 @ HS1 and D3,
HS2 and Q1, HS3 and
Q2"
Split lock washer #4(steel)
Std
Std
6
"X1 @ HS1 and D3,
HS2 and Q1, HS3 and
Q2"
Nylon shoulder washer #4
3049
Keystone
Electronics
2
"X1 @ HS2 and Q1,
HS3 and Q2"
Thermal pad silicon TO220
3223-07FR-51
BERQUIST
4
1903C
Standoff hex .500/6-32THR nylon
1903C
Keystone
Electronics
4
4824
Nut
4824
Keystone
Electronics
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15
Evaluation Board/Kit Important Notice
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the
product(s) must have electronics training and observe good engineering practice standards. As such, the goods being provided are
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including product safety and environmental measures typically found in end products that incorporate such semiconductor
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Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30
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This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
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EVM Warnings and Restrictions
It is important to operate this EVM within the input voltage range of xxx V to xxx V and the output voltage range of xxx V to xxx V .
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are
questions concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the
EVM. Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load
specification, please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than xxx° C. The EVM is designed to
operate properly with certain components above xxx° C as long as the input and output ranges are maintained. These components
include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of
devices can be identified using the EVM schematic located in the EVM User's Guide. When placing measurement probes near
these devices during operation, please be aware that these devices may be very warm to the touch.
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