Revised October 2006 FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with 2V Undershoot Protection and Selectable Level Shifting General Description Features The Fairchild Universal Bus Switch FSTUD32450 provides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit...40-bit of high-speed CMOS TTL-compatible bus switching. The low On Resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. The FSTUD32450 is designed to allow “customer” configuration control of the enable connections. The device can be organized as either a ten 4-bit, eight 5-bit, four 10-bit, two 20-bit or one 40-bit enabled bus switch. Also achievable are 8-bit and 16-bit enabled configurations (see Functional Description). The device's bit configuration is controlled through select pin logic. (see Truth Table). When OEx is LOW, Port Ax is connected to Port Bx. When OEx is HIGH, the switch is OPEN. The A and B Ports are protected against undershoot to support an extended range to 2.0V below ground. Fairchild's integrated Undershoot Hardened Circuit (UHC®¥) senses undershoot at the I/O, and responds by preventing voltage differentials from developing and turning the switch on. ■ Undershoot protected to 2V (A and B Ports) Another innovative device feature is the addition of a level shifting select pin, “S2 and S5”. When S2 and S5 are LOW, the device behaves as a standard N-MOS switch. When S2 and S5 are HIGH, a diode to VCC is integrated into the circuit allowing for level shifting between 5V inputs and 3.3V outputs. ■ Voltage level shifting ■ 4: switch connection between two ports ■ Minimal propagation delay through the switch ■ Low lCC ■ Zero bounce in flow-through mode ■ Control inputs compatible with TTL level ■ See Applications Notes AN-5008 and AN-5021 for UHC details ■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA) Applications Note Select pins S0, S1, S2, S3, S4 and S5 are intended to be used as static user configurable control pins. The AC performance of these pins has not been characterized or tested. Switching of these select pins during system operation may temporarily disrupt output logic states and/or enable pin controls. 40-bit configuration can be achieved by connecting the OE1 and the OE6 pins to together. Ordering Code: Order Number FSTUD32450G (Note 1)(Note 2) Package Number BGA114A Package Description 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Note 1: Ordering code “G” indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. UHC®¥ is a registered trademark of Fairchild Semiconductor Corporation. © 2005 Fairchild Semiconductor Corporation DS500447 www.fairchildsemi.com FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with 2V Undershoot Protection and Selectable Level Shifting August 2001 FSTUD32450 Connection Diagram Pin Descriptions Pin Name Pin Assignment for FBGA Description OE1, OE2, OE3, OE4, Bus Switch OE5, OE6, OE7, OE8 Enables OE9, OE10 1A, 2A, 3A, 4A Bus A 1B, 2B, 3B, 4B Bus B S0, S1, S3, S4 Bit Configuration Enables S2, S5 Level Shifting Diode Enables FBGA Pin Assignments (Top Thru View) www.fairchildsemi.com 2 1 2 3 4 5 6 A 1A4 1A2 OE1 OE2 1B2 1B4 B 1A6 1A5 1A1 1B1 1B5 1B6 C 1A8 1A7 1A3 1B3 1B7 1B8 D 1A10 1A9 GND OE5 1B9 1B10 E 2A2 2A1 S0 VCC 2B1 2B2 F 2A4 2A3 S1 S2 2B3 2B4 G 2A6 2A5 VCC GND 2B5 2B6 H 2A8 2A7 GND GND 2B7 2B8 J 2A10 2A9 GND GND 2B9 2B10 K OE4 OE8 GND GND OE9 OE3 L 3A10 3A9 GND GND 3B9 3B10 M 3A8 3A7 GND GND 3B7 3B8 N 3A6 3A5 GND VCC 3B5 3B6 P 3A4 3A3 S5 S4 3B3 3B4 R 3A2 3A1 VCC S3 3B1 3B2 T 4A10 4A9 OE10 GND 4B9 4B10 U 4A8 4A7 4A3 4B3 4B7 4B8 V 4A6 4A5 4A1 4B1 4B5 4B6 W 4A4 4A2 OE7 OE6 4B2 4B4 FSTUD32450 Logic Diagrams 20-Bit Configuration 10-Bit Configuration 3 www.fairchildsemi.com FSTUD32450 5-Bit Configuration 4-Bit Configuration www.fairchildsemi.com 4 The device can also be configured as an 8 and 16-bit device by grounding the unused pins in Configurations 2 and 1 respectively. The 8-bit configuration may also be achieved by tying two of the 4-bit enables from configuration together and tying the remaining enable pin (OE) HIGH. Truth Tables (X VCC or GND) (see Functional Description) Select Pin S2, S5 Mode L Std. NMOS Switch H Level Shifting Diode Enabled 20-Bit Configuration (S0 S1 L) Inputs OE1 OE2 OE3 OE4 L X X X X H X X X X S3 S4 Inputs/Outputs OE5 1A1-10 1B1-10, 2A1-10 2B1-10 Z L Inputs Inputs/Outputs OE6 OE7 OE8 OE9 OE10 L X X X X H X X X X 10-Bit Configuration (S0 L, S1 3A1-10 3B1-10, 4A1-10 4B1-10 Z H) Inputs Inputs/Outputs OE1 OE2 OE3 OE4 OE5 L X X L X 1AX 1BX L X X H X 1AX 1BX H X X L X Z H X X H X Z S3 L, S4 1A1-10 1B1-10 2A1-10 2B1-10 2AX 2BX Z 2AX 2BX Z H Inputs Inputs/Outputs OE6 OE7 OE8 OE9 OE10 L X X L X 4AX 4BX L X X H X 4AX 4BX H X X L X Z H X X H X Z 5 4A1-10 4B1-10 3A1-10 3B1-10 3AX 3BX Z 3BX 3AX Z www.fairchildsemi.com FSTUD32450 Functional Description FSTUD32450 Truth Tables (Continued) 5-Bit Configuration (S0 H, S1 L) Inputs Inputs/Outputs OE1 OE2 OE3 OE4 OE5 1A1-5, 1B1-5 1A6-10, 1B6-10 L L L L X 1Ax 1Bx 1Ay 1By 2A1-5, 2B1-5 2Ax 2Bx L L L H X 1Ax 1Bx 1Ay 1By 2Ax 2Bx L L H L X 1Ax 1Bx 1Ay 1By Z L L H H X 1Ax 1Bx 1Ay 1By Z L H L L X 1Ax 1Bx Z 2Ax 2Bx L H L H X 1Ax 1Bx Z 2Ax 2Bx L H H L X 1Ax 1Bx Z Z L H H H X 1Ax 1Bx Z Z L L X Z 1Ay 1By 2Ax 2Bx L H X Z 1Ay 1By 2Ax 2Bx H L H L X Z 1Ay 1By Z H L H H X Z 1Ay 1By Z H H L L X Z Z 2Ax 2Bx H H L H X Z Z 2Ax 2Bx H L X Z Z Z H H X Z Z Z 4A1-5, 4B1-5 4A6-10, 4B6-10 S3 H, S4 2By Z 2By 2Ay 2By Z 2Ay 2By Z 2Ay 2By Z 2Ay 2By Z L Inputs Inputs/Outputs OE6 OE7 OE8 OE9 OE10 L L L L X 4Ax 4Bx 4Ay 4By 3Ax 3Bx L L L H X 4Ax 4Bx 4Ay 4By 3Ax 3Bx 3A1-5, 3B1-5 L L H L X 4Ax 4Bx 4Ay 4By Z L L H H X 4Ax 4Bx 4Ay 4By Z L H L L X 4Ax 4Bx Z 3Ax 3Bx L H L H X 4Ax 4Bx Z 3Ax 3Bx L H H L X 4Ax 4Bx Z Z L H H H X 4Ax 4Bx Z Z L L X Z 4Ay 4By 3Ax 3Bx L H X Z 4Ay 4By 3Ax 3Bx H L H L X Z 4Ay 4By Z H L H H X Z 4Ay 4By Z H H L L X Z Z 3Ax 3Bx H H L H X Z Z 3Ax 3Bx H H L X Z Z Z H H X Z Z Z 6 3By 3Ay 3By Z 3By Z L H 3By Z 3Ay L H 3Ay Z H H 3A6-10, 3B6-10 3Ay H www.fairchildsemi.com 2Ay Z L H 2By 2Ay L H 2By Z Z H H 2Ay 2Ay H H 2A6-10, 2B6-10 3Ay 3By Z 3Ay 3By Z 3Ay 3By Z 3By 3Ay Z (Continued) 4-Bit Configuration (S0 S1 H) Inputs Inputs/Outputs OE1 OE2 OE3 OE4 OE5 1A1-4, 1B1-4 1A5-8, 1B5-8 2A3-6, 2B3-6 2A7-10, 2B7-10 L L L L L 1Ax 1Bx 1Ay 1By 2Ax 2Bx 2Ay 2By L L L L H 1Ax 1Bx 1Ay 1By 2Ax 2Bx 2Ay 2By L L L H L 1Ax 1Bx 1Ay 1By 2Ax 2Bx Z L L L H H 1Ax 1Bx 1Ay 1By 2Ax 2Bx Z H L L 1Ax 1Bx 1Ay 1By Z 2Ay 2By L L H L H 1Ax 1Bx 1Ay 1By Z 2Ay 2By H H L 1Ax 1Bx 1Ay 1By Z Z L L H H H 1Ax 1Bx 1Ay 1By Z Z L L L 1Ax 1Bx Z 2Ax 2Bx 2Ay 2By L H L L H 1Ax 1Bx Z 2Ax 2Bx 2Ay 2By L H L 1Ax 1Bx Z 2Ax 2Bx Z L H L H H 1Ax 1Bx Z 2Ax 2Bx Z H L L 1Ax 1Bx Z Z 2Ay 2By L H H L H 1Ax 1Bx Z Z 2Ay 2By H H L 1Ax 1Bx Z Z Z L H H H H 1Ax 1Bx Z Z Z L L L Z 1Ay 1By 2Ax 2Bx 2Ay 2By H L L L H Z 1Ay 1By 2Ax 2Bx 2Ay 2By L H L Z 1Ay 1By 2Ax 2Bx Z H L L H H Z 1Ay 1By 2Ax 2Bx Z H L L Z 1Ay 1By Z 2Ay 2By H L H L H Z 1Ay 1By Z 2Ay 2By H H L Z 1Ay 1By Z Z H L H H H Z 1Ay 1By Z Z L L L Z Z 2Ax 2Bx 2Ay 2By H H L L H Z Z 2Ax 2Bx 2Ay 2By L H L Z Z 2Ax 2Bx Z H H L H H Z Z 2Ax 2Bx Z H L L Z Z Z 2Ay 2By H H H L H Z Z Z 2Ay 2By H H L Z Z Z Z H H H H H Z Z Z Z 7 1Az 2Az 1Bz 2Bz Z 1Bz 2Bz 1Az 2Az 1Bz 2Bz Z 1Bz 2Bz 1Az 2Az 1Bz 2Bz Z 1Bz 2Bz 1Az 2Az 1Bz 2Bz Z 1Bz 2Bz Z H H 1Bz 2Bz 1Az 2Az H H Z Z H H 1Bz 2Bz 1Az 2Az H H 1Az 2Az Z L L 1Bz 2Bz 1Az 2Az H H Z Z L L 1Bz 2Bz 1Az 2Az H H 1Az 2Az Z H H 1Bz 2Bz 1Az 2Az L L Z Z H H 1Bz 2Bz 1Az 2Az L L 1Az 2Az Z L L 2A1-2, 2B1-2 1Az 2Az L L 1A9-10, 2B9-10 1Az 2Az 1Bz 2Bz Z 1Bz 2Bz 1Az 2Az Z www.fairchildsemi.com FSTUD32450 Truth Tables FSTUD32450 Truth Tables (Continued) 4-Bit Configuration (continued) S3 S4 H Inputs Inputs/Outputs OE6 OE7 OE8 OE9 OE10 L L L L L 4Ax 4Bx 4Ay 4By 3Ax 3Bx 3Ay 3By L L L L H 4Ax 4Bx 4Ay 4By 3Ax 3Bx 3Ay 3By 4A5-8, 4B5-8 3A3-6, 3B3-6 3A7-10, 3B7-10 H L 4Ax 4Bx 4Ay 4By 3Ax L L H H 4Ax 4Bx 4Ay 4By 3Ax L H L L 4Ax 4Bx 4Ay 4By Z 3Ay 3By L H L H 4Ax 4Bx 4Ay 4By Z 3Ay 3By L L L L L H H L 4Ax 4Bx 4Ay 4Ay 4By 3Bx Z 3Bx L L H H H 4Ax 4Bx H L L L 4Ax 4Bx Z 3Ax 3Bx 3Ay 3By L H L L H 4Ax 4Bx Z 3Ax 3Bx 3Ay 3By 4Ax 4Bx Z 3Ax H L H H 4Ax 4Bx Z 3Ax H H L L 4Ax 4Bx Z Z 3Ay 3By H H L H 4Ax 4Bx Z Z 3Ay 3By L L H H H L 4Ax 4Ax 4Bx Z Z 3Bx Z Z H H H H L L L L Z 4Ay 4By 3Ax 3Bx 3Ay 3By H L L L H Z 4Ay 4By 3Ax 3Bx 3Ay 3By Z 4Ay 4By 3Ax L L H H Z 4Ay 4By 3Ax L H L L Z 4Ay 4By Z 3Ay 3By L H L H Z 4Ay 4By Z 3Ay 3By H L H H L Z 4Ay 4Ay 4By Z 3Bx H L H H H Z H L L L Z Z 3Ax 3Bx 3Ay 3By H H L L H Z Z 3Ax 3Bx 3Ay 3By H H H H 3Bx Z Z Z 3Ax H L H H Z Z 3Ax H H L L Z Z Z 3Ay 3By H H L H Z Z Z 3Ay 3By H H L Z Z Z Z H H H H H Z Z Z Z 3Bz 4Bz 3Az 4Az 3Bz 4Bz Z Z H 8 Z 3Az 4Az L H 3Bz 4Bz Z H 3Bx 3Bz 4Bz 3Az 4Az Z L www.fairchildsemi.com Z 3Az 4Az H H 3Bz 4Bz Z Z Z 3Bz 4Bz 3Az 4Az Z Z 4By Z 3Az 4Az L H 3Bz 4Bz Z H H 3Bx 3Bz 4Bz 3Az 4Az Z L L Z 3Az 4Az L H 3Bz 4Bz Z Z Z 3Bz 4Bz 3Az 4Az Z H H 4Bx Z 3Az 4Az L L 3Bz 4Bz Z H L 3Bx 3Bz 4Bz 3Az 4Az Z L H Z 3Az 4Az Z Z 3Bz 4Bz Z L L 3Az 4Az Z Z 4By 3A1-2, 3B1-2 4A9-10, 3B9-10 3Az 4Az L L L 4A1-4, 4B1-4 3Bz 4Bz Z 3Az 4Az 3Bz 4Bz Z 3Az 4Az 3Bz 4Bz Z Recommended Operating Conditions (Note 6) 0.5V to 7.0V 2.0V to 7.0V Supply Voltage (VCC) DC Switch Voltage (VS) (Note 4) 4.0V to 5.5V Power Supply Operating (VCC) DC Input Control Pin Voltage Input Voltage (VIN) 0.5V to 7.0V 50 mA (VIN) (Note 5) DC Input Diode Current (lIK) VIN 0V DC Output (IOUT) Current FSTUD32450 Absolute Maximum Ratings(Note 3) 0V to 5.5V Output Voltage (VOUT) 0V to 5.5V -40 qC to 85 qC Free Air Operating Temperature (TA) 128 mA / 100 mA 65qC to 150 qC DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG) Note 3: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 4: VS is the voltage observed/applied at either the A or B Ports across the switch. Note 5: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 6: Unused control inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Symbol Parameter VCC TA (V) Min VIK Clamp Diode Voltage VIH HIGH Level Input Voltage 4.0-5.5 VIL LOW Level Input Voltage 4.0-5.5 VOH HIGH Level Output Voltage 4.5-5.5 II Input Leakage Current 5.5 IOZ OFF-STATE Leakage Current RON Switch On Resistance 4.5 (Note 8) 4.5 ICC 40 qC to 85 qC Typ (Note 7) Max 1.2 4.5 VIKU IIN IF S2 HIGH 4.5V d VCC d 5.5V V IF S2 HIGH 4.5V d VCC d 5.5V V S2 r1.0 PA 0 d VIN d 5.5V 0 10 PA VIN 5.5 r1.0 PA 0 d A, B d VCC 4 7 : VIN 0V, IIN 64 mA, S2 S5 0V or VCC 4 7 : VIN 0V, IIN 30 mA, S2 S5 0V or VCC 4.5 8 12 : VIN 2.4V, IIN 15 mA, S2 S5 0V 4.0 11 20 : VIN 2.4V, IIN 15 mA, S2 S5 0V 4.5 35 50 : VIN 2.4V, IIN 15 mA, S2 S5 VCC 3 PA S2 S5 GND, VIN VCC or GND, IOUT 10 PA S2 S5 VCC, OEx VCC, VIN 1.5 mA S2 S5 VCC, OEx GND, VIN 2.5 mA 4.0 mA 2.0 V 0.8 See Figure 4 Increase in ICC per Voltage Undershoot 5.5 5.5 5.0V and TA S5 VCC 5.5V 0 VCC or GND, IOUT VCC or GND, IOUT 0 0 One Control Input at 3.4V Other Inputs at VCC or GND, S2 0V One Control Input at 3.4V Other Inputs at VCC or GND, S2 VCC 0.0 mA t IIN t 50 mA OEx Note 7: Typical values are at VCC 18 mA V Quiescent Supply Current Control Input Conditions V 2.0 5.5 ICCT Units 5.5V 25qC Note 8: Measured by the voltage drop between A and B pins at the indicated current through the switch. On Resistance is determined by the lower of the voltages on the two (A or B) pins. 9 www.fairchildsemi.com FSTUD32450 AC Electrical Characteristics 40 qC to 85 qC, TA Symbol Parameter tPHL, tPLH Propagation Delay Bus-to-Bus (Note 9) tPZH, tPZL Output Enable Time tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ CL Output Disable Time Sel (S0, 1) to Output Enable Time Sel (S0, 1) to Output Disable Time 50pF, RU VCC 4.5 – 5.5V Min Max 1.5 1.5 500: RD VCC Min S5 Figure 0V) Number Max 0.25 ns 6.5 7.0 ns 7.2 7.0 1.5 (S2 0.25 6.7 1.5 Conditions Units 4.0V ns 7.5 7.5 ns 7.7 ns VI OPEN Figures 2, 3 Figures 2, 3 VI 7V for tPZL VI OPEN for tPZH VI 7V for tPLZ VI OPEN for tPHZ VI 7V for tPZL VI OPEN for tPZH VI 7V for tPLZ VI OPEN for tPHZ Figures 2, 3 Figures 2, 3 Figures 2, 3 Note 9: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). AC Electrical Characteristics: Translating Diode TA Symbol Parameter CL 40 qC to 85 qC, 50pF, RU VCC Min tPHL, tPLH Propagation Delay Bus-to-Bus (Note 10) tPZH, tPZL Output Enable Time tPHZ, tPLZ tPZH, tPZL tPHZ, tPLZ Output Disable Time Sel (S0, 1) to Output Enable Time Sel (S0, 1) to Output Disable Time RD 500: 4.5 – 5.5V Conditions Units (S2 S5 Figure VCC) Number Max 1.5 0.25 ns 10.0 ns 1.5 9.0 1.5 ns 11.0 1.5 ns 10.0 ns VI OPEN Figures 2, 3 Figures 2, 3 VI 7V for tPZL VI OPEN for tPZH VI 7V for tPLZ VI OPEN for tPHZ VI 7V for tPZL VI OPEN for tPZH VI 7V for tPLZ VI OPEN for tPHZ Figures 2, 3 Figures 2, 3 Figures 2, 3 Note 10: This parameter is guaranteed by design but is not tested. This bus switch contributes no propagation delay other than the RC delay of the typical On Resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance). Capacitance Symbol CIN CI/O Note 11: TA (Note 11) Parameter Typ Max Units Conditions Control Pin Input Capacitance 4 pF VCC Input/Output Capacitance “OFF State” 8 pF VCC, OE 25qC, f 1 MHz, Capacitance is characterized but not tested. www.fairchildsemi.com 10 5.0V, VIN 0V 5.0V, VIN 0V Symbol VOUTU Parameter Output Voltage During Undershoot Min Typ 2.5 VOH 0.3 Max Units V S2 S5 0V, Figure 1 Conditions TBD TBD V S2 S5 VCC Note 12: This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event. FIGURE 1. Device Test Conditions Parameter Value VIN see Waveform V 100K : VTRI 11.0 V VCC 5.5 V R1 R2 Transient Input Voltage (VIN) Waveform Units AC Loading and Waveforms Note: Input driven by 50: source terminated in 50: Note: CL includes load and stray capacitance Note: Input Frequency 1.0 MHz, tW 500 ns FIGURE 2. AC Test Circuit FIGURE 3. AC Waveforms 11 www.fairchildsemi.com FSTUD32450 Undershoot Characteristic (Note 12) FSTUD32450 FIGURE 4. www.fairchildsemi.com 12 114-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA114A Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 13 www.fairchildsemi.com FSTUD32450 Configurable 4-Bit to 40-Bit Bus Switch with 2V Undershoot Protection and Selectable Level Shifting Physical Dimensions inches (millimeters) unless otherwise noted