DEC. 1998 Ver. 3.0 8-BIT SINGLE-CHIP MICROCONTROLLERS GMS90 Series DATA SHEET Version 3.0 Published by MCU Application Team 1998 LG Semicon Co., Ltd. All right reserved. Additional information of this manual may be served by LG Semicon offices in Korea or Distributors and Representatives listed at address directory. LG Semicon reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, LG Semicon Co., Ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual. GMS90 Series Device Naming Structure GMS90X5X - GBXXX XX XX Mask ROM version LG Semicon MCU Frequency Blank: 12MHz 24: 24MHz 40: 40MHz Package Type Blank: 40PDIP PL: 44PLCC Q: 44MQFP ROM Code serial No. ROM size 1: 4k bytes 2: 8k bytes 4: 16k bytes 6: 24k bytes 8: 32k bytes Operating Voltage C: 4.25~5.5V L: 2.7~3.6V OTP version LG Semicon MCU GMS97X5X X XX Package Type Blank: 40PDIP PL: 44PLCC Q: 44MQFP Frequency Blank: 12/24(5V),12MHz(3V) H: 33MHz ROM size 1: 4k bytes 2: 8k bytes 4: 16k bytes 6: 24k bytes 8: 32k bytes Operating Voltage C: 4.25~5.5V L: 2.7~3.6V Dec. 1998 Ver 3.0 GMS90 Series GMS90 Series Selection Guide ROM size (bytes) Operating Voltage (V) MASK OTP ROM-less 4.25~5.5 2.7~3.6 RAM size (bytes) Device Name Operating Frequency (MHz) 128 256 GMS90C31 GMS90C32 12/24/40 12/24/40 4K 8K 16K 24K 32K - 128 256 256 256 256 GMS90C51 GMS90C52 GMS90C54 GMS90C56 GMS90C58 12/24/40 12/24/40 12/24/40 12/24/40 12/24/40 - 4K 4K 8K 8K 16K 16K 24K 24K 32K 32K 128 128 256 256 256 256 256 256 256 256 GMS97C51 GMS97C51H GMS97C52 GMS97C52H GMS97C54 GMS97C54H GMS97C56 GMS97C56H GMS97C58 GMS97C58H 12/24 33 12/24 33 12/24 33 12/24 33 12/24 33 ROM-less 128 256 GMS90L31 GMS90L32 12/16 12/16 4K 8K 16K 24K 32K - 128 256 256 256 256 GMS90L51 GMS90L52 GMS90L54 GMS90L56 GMS90L58 12/16 12/16 12/16 12/16 12/16 - 4K 8K 16K 24K 32K 128 256 256 256 256 GMS97L51 GMS97L52 GMS97L54 GMS97L56 GMS97L58 12 12 12 12 12 Note: The ROM version products in this data book will be applied to new masking version. (From Dec., 1998) In case that you have old products, please refer to previous data book (prior to this). Dec. 1998 Ver 3.0 GMS90 Series GMS90C31/51, 97C51 GMS90L31/51, 97L51 (Low voltage versions) • Fully compatible to standard MCS-51 microcontroller • Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”) • 4K × 8 (EP)ROM • 128 × 8 RAM • 64K external program memory space • 64K external data memory space • Four 8-bit ports • Two 16-bit Timers / Counters • USART • Five interrupt sources, two priority levels • Power saving Idle and power down mode • Quick pulse programming algorithm (in the OTP devices) • 2-level program memory lock (in the OTP devices) • 2.7Volt low voltage version available • P-DIP-40, P-LCC-44, P-MQFP-44 package Block Diagram RAM 128 × 8 T0 CPU T1 ROM / EPROM 4K × 8 Dec. 1998 Ver 3.0 8-BIT USART PORT 0 I/O PORT 1 I/O PORT 2 I/O PORT 3 I/O 1 GMS90 Series GMS90C32/52, 97C52 GMS90L32/52, 97L52 (Low voltage versions) • Fully compatible to standard MCS-51 microcontroller • Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”) • 8K × 8 (EP)ROM • 256 × 8 RAM • 64K external program memory space • 64K external data memory space • Four 8-bit ports • Three 16-bit Timers / Counters (Timer2 with up/down counter feature) • USART • Six interrupt sources, two priority levels • Power saving Idle and power down mode • Quick pulse programming algorithm (in the OTP devices) • 2-level program memory lock (in the OTP devices) • 2.7Volt low voltage version available • P-DIP-40, P-LCC-44, P-MQFP-44 package Block Diagram RAM 256 × 8 T0 CPU T2 T1 ROM / EPROM 8K × 8 2 8-BIT USART PORT 0 I/O PORT 1 I/O PORT 2 I/O PORT 3 I/O Dec. 1998 Ver 3.0 GMS90 Series GMS90C54/56/58, 97C54/56/58 GMS90L54/56/58, 97L54/56/58 (Low voltage versions) • Fully compatible to standard MCS-51 microcontroller • Wide operating frequency up to 40MHz (for more detail, see “GMS90 Series Selection Guide”) • 16K/24K/32K bytes (EP)ROM • 256 × 8 RAM • 64K external program memory space • 64K external data memory space • Four 8-bit ports • Three 16-bit Timers / Counters (Timer2 with up/down counter feature) • USART • One clock output port • Programmable ALE pin enable / disable • Six interrupt sources, two priority levels • Power saving Idle and power down mode • Quick pulse programming algorithm (in the OTP devices) • 2-level program memory lock (in the OTP devices) • 2.7Volt low voltage version available • P-DIP-40, P-LCC-44, P-MQFP-44 package Block Diagram RAM 256 × 8 T0 CPU T2 8-BIT USART T1 ROM / EPROM GMS9XX54: 16K × 8 GMS9XX56: 24K × 8 GMS9XX58: 32K × 8 Dec. 1998 Ver 3.0 PORT 0 I/O PORT 1 I/O PORT 2 I/O PORT 3 I/O 3 GMS90 Series PIN CONFIGURATION P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 41 40 N.C.* 42 P1.0 / T2 1 VCC P1.1 / T2EX 2 P0.0 / AD0 P1.2 3 43 P1.3 4 44 P1.4 5 INDEX CORNER 6 44-PLCC Pin Configuration (top view) PSEN INT1 / P3.3 15 31 P2.7 / A15 T0 / P3.4 16 30 P2.6 / A14 T1 / P3.5 17 29 P2.5 / A13 28 32 P2.4 / A12 14 27 ALE / PROG INT0 / P3.2 26 33 P2.2 / A10 13 P2.3 / A11 N.C.* TxD / P3.1 25 34 P2.1 / A9 12 24 EA / VPP N.C.* P2.0 / A8 35 23 11 N.C.* P0.7 / AD7 RxD / P3.0 22 36 VSS 10 21 P0.6 / AD6 RESET XTAL1 37 20 9 XTAL2 P0.5 / AD5 P1.7 19 P0.4 / AD4 38 18 39 8 RD / P3.7 7 P1.6 WR / P3.6 P1.5 N.C.: Do not connect. 4 Dec. 1998 Ver 3.0 GMS90 Series 40-PDIP Pin Configuration (top view) Dec. 1998 Ver 3.0 T2 / P1.0 1 40 VCC T2EX / P1.1 2 39 P0.0 / AD0 P1.2 3 38 P0.1 / AD1 P1.3 4 37 P0.2 / AD2 P1.4 5 36 P0.3 / AD3 P1.5 6 35 P0.4 / AD4 P1.6 7 34 P0.5 / AD5 P1.7 8 33 P0.6 / AD6 RESET 9 32 P0.7 / AD7 RxD / P3.0 10 31 EA / VPP TxD / P3.1 11 30 ALE / PROG INT0 / P3.2 12 29 PSEN INT1 / P3.3 13 28 P2.7 / A15 T0 / P3.4 14 27 P2.6 / A14 T1 / P3.5 15 26 P2.5 / A13 WR / P3.6 16 25 P2.4 / A12 RD / P3.7 17 24 P2.3 / A11 XTAL2 18 23 P2.2 / A10 XTAL1 19 22 P2.1 / A9 VSS 20 21 P2.0 / A8 5 GMS90 Series P1.4 P1.3 P1.2 P1.1 / T2EX P1.0 / T2 N.C.* VCC P0.0 / AD0 P0.1 / AD1 P0.2 / AD2 P0.3 / AD3 44 43 42 41 40 39 38 37 36 35 34 44-MQFP Pin Configuration (top view) PSEN INT1 / P3.3 9 25 P2.7 / A15 T0 / P3.4 10 24 P2.6 / A14 T1 / P3.5 11 23 P2.5 / A13 22 26 P2.4 / A12 8 21 ALE / PROG INT0 / P3.2 P2.3 / A11 27 20 7 P2.2 / A10 N.C.* TxD / P3.1 19 28 P2.1 / A9 6 18 EA / VPP N.C.* P2.0 / A8 29 17 5 N.C.* P0.7 / AD7 RxD / P3.0 16 30 VSS 4 15 P0.6 / AD6 RESET XTAL1 31 14 3 XTAL2 P0.5 / AD5 P1.7 13 P0.4 / AD4 32 12 33 2 RD / P3.7 1 P1.6 WR / P3.6 P1.5 N.C.: Do not connect. 6 Dec. 1998 Ver 3.0 GMS90 Series Logic Symbol VCC XTAL1 XTAL2 RESET VSS Port 0 8-bit Digital I/O Port 1 8-bit Digital I/O Port 2 8-bit Digital I/O EA/VPP ALE/PROG Port 3 8-bit Digital I/O PSEN Dec. 1998 Ver 3.0 7 GMS90 Series PIN DEFINITIONS AND FUNCTIONS Pin Number Symbol P1.0-P1.7 P3.0-P3.7 XTAL2 8 Input/ Output Function PLCC44 PDIP40 MQFP44 2-9 1-8 40-44, 1-3 2 3 1 2 40 41 2 1 40 11, 13-19 10-17 5, 7-13 11 10 5 P3.0 / RxD 13 11 7 P3.1 / TxD 14 15 16 17 18 12 13 14 15 16 8 9 10 11 12 P3.2 /INT0 P 3.3 / IN T 1 P3.4 /T0 P3.5 /T1 P3.6 / WR 19 17 13 P3.7 /RD 20 18 14 I/O Port1 Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the pulls-ups (IIL, in the DC characteristics). Pins P1.0 and P1.1 also. Port1 also receives the low-order address byte during program memory verification. Port1 also serves alternate functions of Timer 2. P1.0 / T2 : Timer/counter 2 external count input P1.1 / T2EX : Timer/counter 2 trigger input In GMS9XC54/56/58: P1.0 / T2, Clock Out : Timer/counter 2 external count input, Clock Out I/O O Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 3 pins that are externally pulled low will source current because of the pulls-ups (IIL, in the DC characteristics). Port 3 also serves the special features of the 80C51 family, as listed below. receiver data input (asynchronous) or data input output(synchronous) of serial interface 0 transmitter data output (asynchronous) or clock output (synchronous) of the serial interface 0 interrupt 0 input/timer 0 gate control interrupt 1 input/timer 1 gate control counter 0 input counter 1 input the write control signal latches the data byte from port 0 into the external data memory the read control signal enables the external data memory to port 0 XTAL2 Output of the inverting oscillator amplifier. Dec. 1998 Ver 3.0 GMS90 Series Pin Number Symbol Input/ Output Function PLCC44 PDIP40 MQFP44 XTAL1 21 19 15 I XTAL1 Input to the inverting oscillator amplifier and input to the internal clock generator circuits.To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is divided down by a divide-by-two flip-flop. Minimum and maximum high and low times as well as rise fall times specified in the AC characteristics must be observed. P2.0-P2.7 24-31 21-28 18-25 I/O Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and can be used as inputs. As inputs, port 2 pins that are externally pulled low will source current because of the pulls-ups (IIL, in the DC characteristics).Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 special function register. PSEN 32 29 26 O The Program Store Enable The read strobe to external program memory when the device is executing code from the external program memory. PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. RESET 10 9 4 I RESET A high level on this pin for two machine cycles while the oscillator is running resets the device. An internal diffused resistor to VSS permits power-on reset using only an external capacitor to VCC. Dec. 1998 Ver 3.0 9 GMS90 Series Pin Number Symbol ALE / PROG PLCC44 PDIP40 MQFP44 33 30 27 Input/ Output O Function The Address Latch Enable / Program pulse Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. In GMS9XC54/56/58: If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With this bit set, the pin is weakly pulled high. The ALE disable feature will be terminated by reset. Setting the ALE-disable bit has no affect if the microcontroller is in external execution mode. EA / VPP 35 31 29 I External Access Enable / Program Supply Voltage EA must be external held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than its internal memory size. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. Note; however, that if any of the Lock bits are programmed, EA will be internally latched on reset. Port 0 Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the GMS97X5X. External pull-up resistors are required during program verification. P0.0-P0.7 36-43 32-39 30-37 I/O VSS 22 20 16 - Circuit ground potential VCC 44 40 38 - Supply terminal for all operating modes N.C. 1,12 23,34 - 6,17 28,39 - 10 No connection Dec. 1998 Ver 3.0 GMS90 Series FUNCTIONAL DESCRIPTION The GMS90 series is fully compatible to the standard 8051 microcontroller family. It is compatible with the general 8051 family. While maintaining all architectural and operational characteristics of the general 8051 family. Figure 1 shows a block diagram of the GMS90 series XTAL1 RAM OSC & TIMING XTAL2 RESET CPU EA/VPP Timer 0 ALE/PROG PSEN 128/256×8 ROM/EPROM 4K/8K/16K 24K/32K Port 0 Port 0 8-bit Digit. I/O Port 1 Port 1 8-bit Digit. I/O Port 2 Port 2 8-bit Digit. I/O Port 3 Port 3 8-bit Digit. I/O Timer 1 Timer 2 Interrupt Unit Serial Channel Figure 1. Block Diagram of the GMS90 series Dec. 1998 Ver 3.0 11 GMS90 Series CPU The GMS90 series is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44% one-byte, 41% two-byte, and 15% three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1.0µs (40MHz: 300ns). Special Function Register PSW Bit No. Addr. D0H LSB MSB 7 6 5 CY AC F0 4 3 2 RS1 RS0 OV Bit 1 0 F1 P Function CY Carry Flag AC Auxiliary Carry Flag (for BCD operations) F0 General Purpose Flag RS1 0 0 1 1 PSW RS0 0 1 0 1 Register Bank select control bits Bank 0 selected, data address 00H - 07H Bank 1 selected, data address 08H - 0FH Bank 2 selected, data address 10H - 17H Bank 3 selected, data address 18H - 1FH OV Overflow Flag F1 General Purpose Flag P Parity Flag Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e. even parity. Reset value of PSW is 00H. 12 Dec. 1998 Ver 3.0 GMS90 Series SPECIAL FUNCTION REGISTERS All registers, except the program counter and the four general purpose register banks, reside in the special function register area. The 28 special function registers (SFR) include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. There are also 128 directly addressable bits within the SFR area. All SFRs are listed in Table 1, Table 1, and Table 3. In Table 1 they are organized in numeric order of their addresses. In Table 2 they are organized in groups which refer to the functional blocks of the GMS90 series. Table 3 illustrates the contents of the SFRs. Table 1. Special Function Registers in Numeric Order of their Addresses Address Register Contents after Reset Address Register Contents after Reset 80H 81H 82H 83H 84H 85H 86H 87H P0 1) SP DPL DPH reserved reserved reserved PCON FFH 07H 00H 00H XXH 2) XXH 2) XXH 2) 0XX0000B 2) 90H 91H 92H 93H 94H 95H 96H 97H P1 1) reserved reserved reserved reserved reserved reserved reserved FFH 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 88H 89H 8AH 8BH 8CH 8DH 8EH 3) 8FH TCON 1) TMOD TL0 TL1 TH0 TH1 ☞ 3) reserved 00H 00H 00H 00H 00H 00H ☞ 3) XXH 2) 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH SCON 1) SBUF reserved reserved reserved reserved reserved reserved 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 1) Bit-addressable Special Function Register. 2) X means that the value is indeterminate and the location is reserved. 3) The GMS9XX54/56/58 have the AUXR0 register at address 8EH. GMS9XX51/52 8EH GMS9XX54/56/58 reserved Dec. 1998 Ver 3.0 XXXXXXXXB2) 8EH AUXR0 XXXXXXX0B2) 13 GMS90 Series Table 1. Special Function Registers in Numeric Order of their Addresses (cont’d) 14 Address Register Contents after Reset Address Register Contents after Reset A0H A1H A2H A3H A4H A5H A6H A7H P2 1) reserved reserved reserved reserved reserved reserved reserved FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) C8H C9H 3) CAH CBH CCH CDH CEH CFH T2CON 1) T2MOD RC2L RC2H TL2 TH2 reserved reserved 00H ☞ 3) 00H 00H 00H 00H XXH 2) XXH 2) A8H A9H AAH ABH ACH ADH AEH AFH IE 1) reserved reserved reserved reserved reserved reserved reserved 0X000000B 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) D0H D1H D2H D3H D4H D5H D6H D7H PSW 1) reserved reserved reserved reserved reserved reserved reserved 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) B0H B1H B2H B3H B4H B5H B6H B7H P3 1) reserved reserved reserved reserved reserved reserved reserved FFH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) D8H D9H DAH DBH DCH DDH DEH DFH reserved reserved reserved reserved reserved reserved reserved reserved XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) B8H B9H BAH BBH BCH BDH BEH BFH IP 1) reserved reserved reserved reserved reserved reserved reserved XX000000B 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) E0H E1H E2H E3H E4H E5H E6H E7H ACC 1) reserved reserved reserved reserved reserved reserved reserved 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) C0H C1H C2H C3H C4H C5H C6H C7H reserved reserved reserved reserved reserved reserved reserved reserved XXH XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) E8H E9H EAH EBH ECH EDH EEH EFH reserved reserved reserved reserved reserved reserved reserved reserved XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) Dec. 1998 Ver 3.0 GMS90 Series Table 1. Special Function Registers in Numeric Order of their Addresses (cont’d) Address Register F0H F1H F2H F3H F4H F5H F6H F7H B 1) reserved reserved reserved reserved reserved reserved reserved Contents after Reset 00H XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) Address Register F8H F9H FAH FBH FCH FDH FEH FFH reserved reserved reserved reserved reserved reserved reserved reserved Contents after Reset XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) XXH 2) 1) Bit-addressable Special Function Register. 2) X means that the value is indeterminate and the location is reserved. 3) Address C9H is configured as below. GMS9XX51/52 C9H GMS9XX54/56/58 reserved Dec. 1998 Ver 3.0 XXXXXXX0B 2) C9H T2MOD XXXXXX00B2) 15 GMS90 Series Table 2. Special Function Registers - Functional Blocks Block Symbol Name Address Contents after Reset CPU ACC B DPH DPL PSW SP Accumulator B-Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer E0H 1) F0H 1) 83H 82H D0H 1) 81H 00H 00H 00H 00H 00H 07H Interrupt System IE IP Interrupt Enable Register Interrupt Priority Register A8H 1) B8H 1) 0X000000B 2) XX000000B 2) Ports P0 P1 P2 P3 Port 0 Port 1 Port 2 Port 3 80H 1) 90H 1) A0H 1) B0H 1) FFH FFH FFH FFH Serial Channels PCON 3) SBUF SCON Power Control Register Serial Channel Buffer Reg. Serial Channel 0 Control Reg. 87H 99H 98H 1) 0XXX0000B 2) XXH 2) 00H Timer 0/ Timer 1 TCON TH0 TH1 TL0 TL1 TMOD Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register 88H 1) 8CH 8DH 8AH 8BH 89H 00H 00H 00H 00H 00H 00H Timer 2 T2CON T2MOD RC2H RC2L TH2 TL2 AUXR0 4) Timer 2 Control Register Timer 2 Mode Register Timer 2 Reload Capture Reg., High Byte Timer 2 Reload Capture Reg., Low Byte Timer 2, High Byte Timer 2, Low Byte Aux. Register 0 C8H 1) C9H CBH CAH CDH CCH 8EH 00H 00H 00H 00H 00H 00H XXXXXXX0B 2) PCON 3) Power Control Register 87H 0XXX0000B 2) Power Modes Saving 1) Bit-addressable Special Function register 2) X means that the value is indeterminate and the location is reserved 3) This special function register is listed repeatedly since some bit of it also belong to other functional blocks 4) The AUXR0 is in the GMS9XX54/56/58 only. 16 Dec. 1998 Ver 3.0 GMS90 Series Table 3. Contents of SFRs, SFRs in Numeric Order Address Register 80H P0 81H SP 82H DPL 83H DPH 87H Bit 7 6 5 4 3 2 1 0 PCON SM O D - - - GF1 GF0 PDE IDLE 88H TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 89H TMOD GATE C/T M1 MT GATE C/T M1 M0 8AH TL0 8BH TL1 8CH TH0 8DH TH1 8EH AUXR0 † - - - - - - - A0 † 90H P1 98H SCON SM0 SM1 SM2 REN TB8 RB8 TI RI 99H SBUF A0H P2 A8H IE EA - ET2 ES ET1 EX1 ET0 EX0 B0H P3 B8H IP - - PT2 PS PT1 PX1 PT0 PX0 † indicates resident in the GMS9XX54/56/58, not in 9XX51/52. SFR bit and byte addressable SFR not bit addressable - : this bit location is reserved Dec. 1998 Ver 3.0 17 GMS90 Series Table 3. Contents of SFRs, SFRs in Numeric Order (cont’d) Address Register Bit 7 6 5 4 3 2 1 0 C8H T2CON TF2 EXF2 RCLK TCLK EXEN 2 TR2 C/T2 CP/RL2 C9H T2MOD - - - - - - T2O E † DCEN CAH RC2L CBH RC2H CCH TL2 CDH TH2 D0H PSW CY AC F0 RS1 RS0 OV F1 P E0H ACC F0H B † indicates resident in the GMS9XX54/56/58, not in 9XX51/52. SFR bit and byte addressable SFR not bit addressable - : this bit location is reserved 18 Dec. 1998 Ver 3.0 GMS90 Series TIMER / COUNTER 0 AND 1 Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4: Table 4. Timer/Counter 0 and 1 Operating Modes TMOD Mode Input Clock Description Gate C/T M1 M0 internal external (Max.) 0 8-bit timer/counter with a divide-by-32 prescaler X X 0 0 fOSC ÷(12×32) fOSC ÷(24×32) 1 16-bit timer/counter X X 0 1 fOSC ÷12 fOSC ÷24 2 8-bit timer/counter with 8-bit auto-reload X X 1 0 fOSC ÷12 fOSC ÷24 3 Timer/counter 0 used as one 8-bit timer/counter and one 8-bit timer Timer 1 stops X X 1 1 fOSC ÷12 fOSC ÷24 In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is fOSC/12. In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate pulse width measurements. Figure 2 illustrates the input clock logic. ÷ 12 fOSC fOSC ÷ 12 C/T TMOD 0 Timer 0/1 Input Clock P3.4/T0 P3.5/T1 Max. fOSC/24 1 TR0 / 1 TCON Gate & =1 TMOD ≥1 P3.2 / INT0 P3.3 / INT1 Figure 2. Timer/Counter 0 and 1 Input Clock Logic Dec. 1998 Ver 3.0 19 GMS90 Series TIMER 2 Timer 2 is a 16-bit timer/Counter with an up/down count feature. It can operate either as timer or as an event counter which is selected by bit C/T2 (T2CON.1). It has three operating modes as shown in Table 5. Table 5. Timer/Counter 2 Operating Modes T2MO T2CON D T2CON Mode RCLK or CP/RL2 TCLK 16-bit AutoReload 16-bit Capture Baud Rate Generator Off Note: ↓ = 20 TR2 DCEN EXEN2 P1.1/ T2EX 0 0 1 0 0 X 0 0 1 0 1 ↓ 0 0 0 0 1 1 1 1 X X 0 1 0 1 1 X 0 X 0 1 1 X 1 ↓ 1 X 1 X 0 X 1 X 1 X 1 ↓ X X 0 X X X Input Clock Remarks internal external (P1.0/T2) reload upon overflow reload trigger (falling edge) Down counting Up counting fOSC ÷ 12 Max. fOSC ÷24 16 bit Timer/ Counter (only up-counting) capture TH2,TL2 → RC2H,RC2L fOSC ÷ 12 Max. fOSC ÷ 24 no overflow interrupt request (TF2) extra external interrupt ("Timer 2") fOSC ÷ 12 Max. fOSC ÷ 24 - - Timer 2 stops falling edge Dec. 1998 Ver 3.0 GMS90 Series SERIAL INTERFACE (USART) The serial port is full duplex and can operate in four modes (one synchronous mode, three asynchronous modes) as illustrated in Table 6. The possible baud rates can be calculated using the formulas given in Table 7. Table 6. USART Operating Modes SCON Mode Baudrate SM0 SM1 0 0 0 f OSC -----------12 1 0 1 Timer 1/2 overflow rate 2 1 0 f OSC f OSC ------------ or -----------32 64 3 1 1 Timer 1/2 overflow rate Description Serial data enters and exits through RxD. TxD outputs the shift clock. 8-bit are transmitted/received (LSB first) 8-bit UART 10 bits are transmitted (through TxD) or received (RxD) 9-bit UART 11 bits are transmitted (TxD) or received (RxD) 9-bit UART Like mode 2 except the variable baud rate Table 7. Formulas for Calculating Baud rates Baud Rate derived from Interface Mode Baudrate 0 f OSC -----------12 2 2 ------------------ × f OSC 64 1,3 2 ------------------ × ( Timer 1 overflow ) 32 1,3 SMOD f OSC 2 ------------------ × -------------------------------------------------32 12 × [ 256 – ( TH1 ) ] 1,3 f OSC ---------------------------------------------------------------------------------32 × [ 65536 – ( RC2H, RC2L ) ] Oscillator SMOD SMOD Timer 1 (16-bit timer) (8-bit timer with 8-bit auto reload) Timer 2 Dec. 1998 Ver 3.0 21 GMS90 Series INTERRUPT SYSTEM The GMS90 series provides 5 (4K bytes ROM version) or 6 (above 8K bytes ROM version) interrupt sources with two priority levels. Figure 3 gives a general overview of the interrupt sources and illustrates the request and control flags. High Priority Timer 0 Overflow TF0 TCON.5 ET0 PT0 IE.1 IP.1 ET1 PT1 IE.3 IP.3 EXF2 ET2 PT2 T2CON.6 IE.5 IP.5 Timer 1 Overflow Low Priority TF1 TCON.7 Timer 2 Overflow TF2 ≥1 T2CON.7 P1.1/ T2EX EXEN2 T2CON.3 UART RI ≥1 SCON.0 TI ES PS SCON.1 IE.4 IP.4 IT0 EX0 PX0 TCON.0 IE.0 IP.0 P3.2/ INT0 IE0 TCON.1 P3.3/ INT1 IE1 TCON.3 IT1 EX1 EA PX1 TCON.2 IE.2 IE.7 IP.2 : Low level triggered : Falling edge triggered Figure 3. Interrupt Request Sources 22 Dec. 1998 Ver 3.0 GMS90 Series Table 8. Interrupt Sources and their Corresponding Interrupt Vectors Source (Request Flags) RESET IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 Vectors Vector Address RESET External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial port interrupt Timer 2 interrupt 0000H 0003H 000BH 0013H 001BH 0023H 002BH A low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request of higher priority is serviced. If requests of the same priority are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence as shown in Table 9. Table 9. Interrupt Priority-Within-Level Interrupt Source External Interrupt 0 Timer 0 Interrupt External Interrupt 1 Timer 1 Interrupt Serial Channel Timer 2 Interrupt Dec. 1998 Ver 3.0 IE0 TF0 IE1 TF1 RI + TI TF2 + EXF2 Priority High ↓ ↓ ↓ ↓ Low 23 GMS90 Series Power Saving Modes Two power down modes are available, the Idle Mode and Power Down Mode. The bits PDE and IDLE of the register PCON select the Power Down mode or the Idle mode, respectively. If the Power Down mode and the Idle mode are set at the same time, the Power Down mode takes precedence. Table 10 gives a general overview of the power saving modes. Table 10. Power Saving Modes Overview Mode Entering Instruction Example Idle mode ORL PCON, #01H - Enabled interrupt - Hardware Reset CPU is gated off CPU status registers maintain their data. Peripherals are active Power-Down mode ORL PCON, #02H Hardware Reset Oscillator is stopped, contents of onchip RAM and SFR’s are maintained (leaving Power Down Mode means redefinition of SFR contents). Leaving by Remarks In the Power Down mode of operation, VCC can be reduced to minimize power consumption. It must be ensured, however, that VCC is not reduced before the Power Down mode is invoked, and that VCC is restored to its normal operating level, before the Power Down mode is terminated. The reset signal that terminates the Power Down mode also restarts the oscillator. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize (similar to power-on reset). 24 Dec. 1998 Ver 3.0 GMS90 Series ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient temperature under bias (TA)...................................................................................... -40 to + 85 °C Storage temperature (TST)...................................................................................................... -65 to + 150 °C Voltage on VCC pins with respect to ground (VSS) ................................................................. -0.5V to 6.5V Voltage on any pin with respect to ground (VSS) ..........................................................-0.5V to VCC + 0.5V Input current on any pin during overload condition............................................................-15mA to +15mA Absolute sum of all input currents during overload condition...........................................................|100mA| Power dissipation ....................................................................................................................................1.5W Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for longer periods may affect device reliability. During overload conditions (VIN > VCC or VIN < VSS) the Voltage on VCC pins with respect to ground (VSS) must not exceed the values defined by the absolute maximum ratings. Dec. 1998 Ver 3.0 25 GMS90 Series DC Characteristics DC Characteristics for GMS90C31/32, GMS90C51/52/54/56/58 VCC= 5V + 10%, -15%; VSS=0V; TA= 0°C to 70°C Parameter Symbol Limit Values Min. Max. 0.2VCC - 0.1 Unit Test Conditions V - Input low voltage (except EA, RESET) VIL -0.5 Input low voltage (EA) VIL1 -0.5 0.2VCC - 0.3 V - Input low voltage (RESET) VIL2 -0.5 0.2VCC + 0.1 V - Input high voltage (except XTAL1, EA, RESET) VIH 0.2VCC + 0.9 VCC + 0.5 V - Input high voltage to XTAL1 VIH1 0.7VCC VCC + 0.5 V - Input high voltage to EA, RESET VIH2 0.6VCC VCC + 0.5 V - Output low voltage (ports 1, 2, 3) VOL - 0.45 V IOL= 1.6mA 1) Output low voltage (port 0, ALE, PSEN) VOL1 - 0.45 V IOL= 3.2mA 1) Output high voltage (ports 1, 2, 3) VOH 2.4 0.9VCC - V IOH= -80µA IOH= -10µA Output high voltage (port 0 in external bus mode, ALE, PSEN) VOH1 2.4 0.9VCC - V IOH= -800µA 2) IOH= -80µA 2) Logic 0 input current (ports 1, 2, 3) IIL -10 -50 µA VIN= 0.45V Logical 1-to-0 transition current (ports 1, 2, 3) ITL -65 -650 µA VIN= 2.0V Input leakage current (port 0, EA) ILI - ±1 µA 0.45 < VIN < VCC CIO - 10 pF fC= 1MHz TA= 25°C ICC ICC ICC ICC ICC ICC IPD - mA mA mA mA mA mA µA VCC= 5V 4) VCC= 5V 5) VCC= 5V 4) VCC= 5V 5) VCC= 5V 4) VCC= 5V 5) VCC= 5V 6) Pin capacitance Power supply current: Active mode, 12MHz 3) Idle mode, 12MHz 3) Active mode, 24 MHz 3) Idle mode, 24MHz 3) Active mode, 40 MHz 3) Idle mode, 40 MHz 3) Power Down Mode 3) 26 21 4.8 36.2 8.2 58.5 12.5 50 Dec. 1998 Ver 3.0 GMS90 Series 1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL of ALE and port 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with a schmitt-trigger strobe input. 2) Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address lines are stabilizing. 3) ICC Max at other frequencies is given by: active mode: ICC = 1.27 × fOSC + 5.73 idle mode: ICC = 0.28 × fOSC + 1.45 (except OTP devices) where fOSC is the oscillator frequency in MHz. ICC values are given in mA and measured at VCC = 5V. 4) ICC (active mode) is measured with: XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.; EA = Port0 = RESET = VCC; all other pins are disconnected. ICC would be slightly higher if a crystal oscillator is used (appr. 1mA). 5) ICC (Idle mode) is measured with all output pins disconnected and with all peripherals disabled; XTAL1 driven with tCLCH, tCHCL = 5ns, VIL = VSS + 0.5V, VIH = VCC - 0.5V; XTAL2 = N.C.; RESET = EA = VSS; Port0 = VCC; all other pins are disconnected; 6) IPD (Power Down Mode) is measured under following conditions: EA = Port0 = VCC; RESET = VSS; XTAL2 = N.C.; XTAL1 = VSS; all other pins are disconnected. Dec. 1998 Ver 3.0 27 GMS90 Series DC Characteristics for GMS97C51/52/54/56/58 (H) VCC= 5V + 10%, -15%; VSS=0V; TA= 0°C to 70°C Parameter Symbol Limit Values Min. Max. Unit Test Conditions Input low voltage (except EA, RESET) VIL -0.5 0.2VCC - 0.1 V - Input low voltage (EA) VIL1 -0.5 0.2VCC - 0.3 V - Input low voltage (RESET) VIL2 -0.5 0.2VCC + 0.1 V - Input high voltage (except XTAL1, EA, RESET) VIH 0.2VCC + 0.9 VCC + 0.5 V - Input high voltage to XTAL1 VIH1 0.7VCC VCC + 0.5 V - Input high voltage to EA, RESET VIH2 0.6VCC VCC + 0.5 V - Output low voltage (ports 1, 2, 3) VOL - 0.45 V IOL= 1.6mA 1) Output low voltage (port 0, ALE, PSEN) VOL1 - 0.45 V IOL= 3.2mA 1) Output high voltage (ports 1, 2, 3) VOH 2.4 0.9VCC - V IOH= -80µA IOH= -10µA Output high voltage (port 0 in external bus mode, ALE, PSEN) VOH1 2.4 0.9VCC - V IOH= -800µA 2) IOH= -80µA 2) Logic 0 input current (ports 1, 2, 3) IIL -10 -50 µA VIN= 0.45V Logical 1-to-0 transition current (ports 1, 2, 3) ITL -65 -650 µA VIN= 2.0V Input leakage current (port 0, EA) ILI - ±1 µA 0.45 < VIN < VCC CIO - 10 pF fC= 1MHz TA= 25°C ICC ICC ICC ICC ICC ICC IPD - mA mA mA mA mA mA µA VCC= 5V 4) VCC= 5V 5) VCC= 5V 4) VCC= 5V 5) VCC= 5V 4) VCC= 5V 5) VCC= 5V 6) Pin capacitance Power supply current: Active mode, 12MHz 3) Idle mode, 12MHz 3) Active mode, 24 MHz 3) Idle mode, 24MHz 3) Active mode, 33 MHz 3) Idle mode, 33 MHz 3) Power Down Mode 3) 28 21 4.8 36.2 8.2 45 10 50 Dec. 1998 Ver 3.0 GMS90 Series DC Characteristics for GMS90L31/32, GMS90L51/52/54/56/58 VCC= 3.3V + 0.3V, -0.6V; VSS=0V; TA= 0°C to 70°C Limit Values Parameter Symbol Min. Max. Unit Test Conditions Input low voltage VIL -0.5 0.8 V - Input high voltage VIH 2.0 VCC + 0.5 V - Output low voltage (ports 1, 2, 3) VOL - 0.45 0.30 V IOL= 1.6mA 1) IOL= 100µA 1) Output low voltage (port 0, ALE, PSEN) VOL1 - 0.45 0.30 V IOL= 3.2mA 1) IOL= 200µA 1) Output high voltage (ports 1, 2, 3) VOH 2.0 0.9VCC - V IOH= -20µA IOH= -10µA Output high voltage (port 0 in external bus mode, ALE, PSEN) VOH1 2.0 0.9VCC - V IOH= -800µA 2) IOH= -80µA 2) Logic 0 input current (ports 1, 2, 3) IIL -1 -50 µA VIN= 0.45V Logical 1-to-0 transition current (ports 1, 2, 3) ITL -25 -250 µA VIN= 2.0V Input leakage current (port 0, EA) ILI - ±1 µA 0.45 < VIN < VCC CIO - 10 pF fC= 1MHz TA= 25°C ICC ICC IPD - 15 5 10 mA mA µA VCC= 3.6V 4) VCC= 2.6V 5) VCC=2~ 5.5V 6) Pin capacitance Power supply current: Active mode, 16 MHz 3) Idle mode, 16MHz 3) Power Down Mode 3) Dec. 1998 Ver 3.0 29 GMS90 Series DC Characteristics for GMS97L51/52/54/56/58 VCC= 3.3V + 0.3V, -0.6V; VSS=0V; TA= 0°C to 70°C Limit Values Parameter Symbol Min. max. Unit Test Conditions Input low voltage VIL -0.5 0.8 V - Input high voltage VIH 2.0 VCC + 0.5 V - Output low voltage (ports 1, 2, 3) VOL - 0.45 0.30 V IOL= 1.6mA 1) IOL= 100µA 1) Output low voltage (port 0, ALE, PSEN) VOL1 - 0.45 0.30 V IOL= 3.2mA 1) IOL= 200µA 1) Output high voltage (ports 1, 2, 3) VOH 2.0 0.9VCC - V IOH= -20µA IOH= -10µA Output high voltage (port 0 in external bus mode, ALE, PSEN) VOH1 2.0 0.9VCC - V IOH= -800µA 2) IOH= -80µA 2) Logic 0 input current (ports 1, 2, 3) IIL -1 -50 µA VIN= 0.45V Logical 1-to-0 transition current (ports 1, 2, 3) ITL -25 -250 µA VIN= 2.0V Input leakage current (port 0, EA) ILI - ±1 µA 0.45 < VIN < VCC CIO - 10 pF fC= 1MHz TA= 25°C ICC ICC IPD - 15 5 10 mA mA µA VCC= 3.6V 4) VCC= 2.6V 5) VCC=2~ 5.5V 6) Pin capacitance Power supply current: Active mode, 12MHz 3) Idle mode, 12MHz 3) Power Down Mode 3) 30 Dec. 1998 Ver 3.0 GMS90 Series AC Characteristics Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a ‘t’ (stand for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH I: Instruction (program memory contents) L: Logic level LOW, or ALE P: PSEN Q: Output Data R: RD signal T: Time V: Valid W: WR signal X: No longer a valid logic level Z: Float For example, tAVLL = Time from Address Valid to ALE Low tLLPL = Time from ALE Low to PSEN Low AC Characteristics for GMS90 series (12MHz version) VCC= 5V : VCC= 5V + 10%, − 15%; VSS= 0V; TA= 0°C to 70°C (CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF) VCC= 3.3V : VCC= 3.3V + 0.3V, − 0.6V; VSS= 0V; TA= 0°C to 70°C (CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF) Variable clock : Vcc = 5V : 1/tCLCL = 3.5 MHz to 12 MHz Vcc = 3.3V : 1/tCLCL = 1 MHz to 12 MHz External Program Memory Characteristics 12 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 12MHz Min. Max. Min. Max. Unit ALE pulse width tLHLL 127 - 2tCLCL-40 - ns Address setup to ALE tAVLL 43 - tCLCL-40 - ns Address hold after ALE tLLAX 30 - tCLCL-53 - ns ALE low to valid instruction in tLLIV - 233 - 4tCLCL-100 ns ALE to PSEN tLLPL 58 - tCLCL-25 - ns PSEN pulse width tPLPH 215 - 3tCLCL-35 - ns PSEN to valid instruction in tPLIV - 150 - 3tCLCL-100 ns Input instruction hold after PSEN tPXIX 0 - 0 - ns Input instruction float after PSEN tPXIZ † - 63 - tCLCL-20 ns Address valid after PSEN tPXAV † 75 - tCLCL-8 - ns Dec. 1998 Ver 3.0 31 GMS90 Series 12 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 12MHz Min. Max. Min. Max. Unit Address to valid instruction in tAVIV - 302 - 5tCLCL-115 ns Address float to PSEN tAZPL 0 - 0 - ns † Interfacing the GMS90 series to devices with float times up to 75 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. 32 Dec. 1998 Ver 3.0 GMS90 Series AC Characteristics for GMS90 series (12MHz) External Data Memory Characteristics 12 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 12MHz Min. Max. Min. Max. Unit RD pulse width tRLRH 400 - 6tCLCL-100 - ns WR pulse width tWLWH 400 - 6tCLCL-100 - ns Address hold after ALE tLLAX2 53 - tCLCL-30 - ns RD to valid data in tRLDV - 252 - 5tCLCL-165 ns Data hold after RD tRHDX 0 - 0 - ns Data float after RD tRHDZ - 97 - 2tCLCL-70 ns ALE to valid data in tLLDV - 517 - 8tCLCL-150 ns Address to valid data in tAVDV - 585 - 9tCLCL-165 ns ALE to WR or RD tLLWL 200 300 3tCLCL-50 3tCLCL+50 ns Address valid to WR or RD tAVWL 203 - 4tCLCL-130 - ns WR or RD high to ALE high tWHLH 43 123 tCLCL-40 tCLCL+40 ns Data valid to WR transition tQVWX 33 - tCLCL-50 - ns Data setup before WR tQVWH 433 - 7tCLCL-150 - ns Data hold after WR tWHQX 33 - tCLCL-50 - ns Address float after RD tRLAZ - 0 - 0 ns Advance Information (12MHz) External Clock Drive Parameter Symbol Variable Oscillator (Freq. = 3.5 to 12MHz) Min. Max. Unit Oscillator period (VCC=5V) Oscillator period (VCC=3.3V) tCLCL tCLCL 83.3 83.3 285.7 1 ns High time tCHCX 20 tCLCL - tCLCX ns Low time tCLCX 20 tCLCL - tCHCX ns Rise time tCLCH - 20 ns Fall time tCHCL - 20 ns Dec. 1998 Ver 3.0 33 GMS90 Series AC Characteristics for GMS90 series (16MHz version) VCC= 3.3V + 0.3V, −0.6V; VSS= 0V; TA= 0°C to 70°C (CL for port 0. ALE and PSEN outputs = 50pF; CL for all other outputs = 50pF) External Program Memory Characteristics 16 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 16MHz Min. Max. Min. Max. Unit ALE pulse width tLHLL 85 - 2tCLCL-40 - ns Address setup to ALE tAVLL 23 - tCLCL-40 - ns Address hold after ALE tLLAX 23 - tCLCL-40 - ns ALE low to valid instruction in tLLIV - 150 - 4tCLCL-100 ns ALE to PSEN tLLPL 38 - tCLCL-25 - ns PSEN pulse width tPLPH 153 - 3tCLCL-35 - ns PSEN to valid instruction in tPLIV - 88 - 3tCLCL-100 ns Input instruction hold after PSEN tPXIX 0 - 0 - ns Input instruction float after PSEN tPXIZ † - 43 - tCLCL-20 ns Address valid after PSEN tPXAV † 55 - tCLCL-8 - ns Address to valid instruction in tAVIV - 198 - 5tCLCL-115 ns Address float to PSEN tAZPL 0 - 0 - ns † Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. 34 Dec. 1998 Ver 3.0 GMS90 Series AC Characteristics for GMS90 series (16MHz) External Data Memory Characteristics 16 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 16MHz Min. Max. Min. Max. Unit RD pulse width tRLRH 275 - 6tCLCL-100 - ns WR pulse width tWLWH 275 - 6tCLCL-100 - ns Address hold after ALE tLLAX2 23 - tCLCL-40 - ns RD to valid data in tRLDV - 183 - 5tCLCL-130 ns Data hold after RD tRHDX 0 - 0 - ns Data float after RD tRHDZ - 75 - 2tCLCL-50 ns ALE to valid data in tLLDV - 350 - 8tCLCL-150 ns Address to valid data in tAVDV - 398 - 9tCLCL-165 ns ALE to WR or RD tLLWL 138 238 3tCLCL−50 3tCLCL+50 ns Address valid to WR or RD tAVWL 120 - 4tCLCL-130 - ns WR or RD high to ALE high tWHLH 28 97 tCLCL−35 tCLCL+35 ns Data valid to WR transition tQVWX 13 - tCLCL−50 - ns Data setup before WR tQVWH 288 - 7tCLCL-150 - ns Data hold after WR tWHQX 23 - tCLCL−40 - ns Address float after RD tRLAZ - 0 - 0 ns Advance Information (16MHz) External Clock Drive Parameter Symbol Variable Oscillator (Freq. = 3.5 to 16MHz) Min. Max. Unit Oscillator period tCLCL 62.5 285.7 ns High time tCHCX 17 tCLCL - tCLCX ns Low time tCLCX 17 tCLCL - tCHCX ns Rise time tCLCH - 17 ns Fall time tCHCL - 17 ns Dec. 1998 Ver 3.0 35 GMS90 Series AC Characteristics for GMS90 series (24MHz version) VCC= 5V + 10%, −15%; VSS= 0V; TA= 0°C to 70°C (CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF) External Program Memory Characteristics 24 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 24MHz Min. Max. Min. Max. Unit ALE pulse width tLHLL 43 - 2tCLCL-40 - ns Address setup to ALE tAVLL 17 - tCLCL-25 - ns Address hold after ALE tLLAX 17 - tCLCL-25 - ns ALE low to valid instruction in tLLIV - 80 - 4tCLCL-87 ns ALE to PSEN tLLPL 22 - tCLCL-20 - ns PSEN pulse width tPLPH 95 - 3tCLCL-30 - ns PSEN to valid instruction in tPLIV - 60 - 3tCLCL-65 ns Input instruction hold after PSEN tPXIX 0 - 0 - ns Input instruction float after PSEN tPXIZ † - 32 - tCLCL-10 ns Address valid after PSEN tPXAV † 37 - tCLCL-5 - ns Address to valid instruction in tAVIV - 148 - 5tCLCL-60 ns Address float to PSEN tAZPL 0 - 0 - ns † Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. 36 Dec. 1998 Ver 3.0 GMS90 Series AC Characteristics for GMS90 series (24MHz) External Data Memory Characteristics 24 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 24MHz Min. Max. Min. Max. Unit RD pulse width tRLRH 180 - 6tCLCL-70 - ns WR pulse width tWLWH 180 - 6tCLCL-70 - ns Address hold after ALE tLLAX2 15 - tCLCL-27 - ns RD to valid data in tRLDV - 118 - 5tCLCL-90 ns Data hold after RD tRHDX 0 - 0 - ns Data float after RD tRHDZ - 63 - 2tCLCL-20 ns ALE to valid data in tLLDV - 200 - 8tCLCL-133 ns Address to valid data in tAVDV - 220 - 9tCLCL-155 ns ALE to WR or RD tLLWL 75 175 3tCLCL-50 3tCLCL+50 ns Address valid to WR or RD tAVWL 67 - 4tCLCL-97 - ns WR or RD high to ALE high tWHLH 17 67 tCLCL-25 tCLCL+25 ns Data valid to WR transition tQVWX 5 - tCLCL-37 - ns Data setup before WR tQVWH 170 - 7tCLCL-122 - ns Data hold after WR tWHQX 15 - tCLCL-27 - ns Address float after RD tRLAZ - 0 - 0 ns Advance Information (24MHz) External Clock Drive Parameter Symbol Variable Oscillator (Freq. = 3.5 to 24MHz) Min. Max. Unit Oscillator period tCLCL 41.7 285.7 ns High time tCHCX 12 tCLCL - tCLCX ns Low time tCLCX 12 tCLCL - tCHCX ns Rise time tCLCH - 12 ns Fall time tCHCL - 12 ns Dec. 1998 Ver 3.0 37 GMS90 Series AC Characteristics for GMS90 series (33MHz version) VCC= 5V + 10%, −15%; VSS= 0V; TA= 0°C to 70°C (CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF) External Program Memory Characteristics 33 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 33MHz Min. Max. Min. Max. Unit ALE pulse width tLHLL 40 - 2tCLCL-20 - ns Address setup to ALE tAVLL 10 - tCLCL-20 - ns Address hold after ALE tLLAX 10 - tCLCL-20 - ns ALE low to valid instruction in tLLIV - 56 - 4tCLCL-65 ns ALE to PSEN tLLPL 15 - tCLCL-15 - ns PSEN pulse width tPLPH 80 - 3tCLCL-20 - ns PSEN to valid instruction in tPLIV - 35 - 3tCLCL-55 ns Input instruction hold after PSEN tPXIX 0 - 0 - ns Input instruction float after PSEN tPXIZ † - 20 - tCLCL-10 ns Address valid after PSEN tPXAV † 25 - tCLCL-5 - ns Address to valid instruction in tAVIV - 91 - 5tCLCL-60 ns Address float to PSEN tAZPL 0 - 0 - ns † Interfacing the GMS90 series to devices with float times up to 35 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. 38 Dec. 1998 Ver 3.0 GMS90 Series AC Characteristics for GMS90 series (33MHz) External Data Memory Characteristics 33 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 33MHz Min. Max. Min. Max. Unit RD pulse width tRLRH 132 - 6tCLCL-50 - ns WR pulse width tWLWH 132 - 6tCLCL-50 - ns Address hold after ALE tLLAX2 10 - tCLCL-20 - ns RD to valid data in tRLDV - 81 - 5tCLCL-70 ns Data hold after RD tRHDX 0 - 0 - ns Data float after RD tRHDZ - 46 - 2tCLCL-15 ns ALE to valid data in tLLDV - 153 - 8tCLCL-90 ns Address to valid data in tAVDV - 183 - 9tCLCL-90 ns ALE to WR or RD tLLWL 71 111 3tCLCL-20 3tCLCL+20 ns Address valid to WR or RD tAVWL 66 - 4tCLCL-55 - ns WR or RD high to ALE high tWHLH 10 40 tCLCL-20 tCLCL+20 ns Data valid to WR transition tQVWX 5 - tCLCL-25 - ns Data setup before WR tQVWH 142 - 7tCLCL-70 - ns Data hold after WR tWHQX 10 - tCLCL-20 - ns Address float after RD tRLAZ - 0 - 0 ns Advance Information (33MHz) External Clock Drive Parameter Symbol Variable Oscillator (Freq. = 3.5 to 24MHz) Min. Max. Unit Oscillator period tCLCL 30.3 285.7 ns High time tCHCX 11.5 tCLCL - tCLCX ns Low time tCLCX 11.5 tCLCL - tCHCX ns Rise time tCLCH - 5 ns Fall time tCHCL - 5 ns Dec. 1998 Ver 3.0 39 GMS90 Series AC Characteristics for GMS90 series (40MHz version) VCC= 5V + 10%, − 15%; VSS= 0V; TA= 0°C to 70°C (CL for port 0. ALE and PSEN outputs = 100pF; CL for all other outputs = 80pF) External Program Memory Characteristics 40 MHz Oscillator Parameter Symbol Variable Oscillator 1/tCLCL = 3.5 to 40MHz Min. Max. Min. Max. Unit ALE pulse width tLHLL 35 - 2tCLCL−15 - ns Address setup to ALE tAVLL 10 - tCLCL−15 - ns Address hold after ALE tLLAX 10 - tCLCL−15 - ns ALE low to valid instruction in tLLIV - 55 - 4tCLCL−45 ns ALE to PSEN tLLPL 10 - tCLCL−15 - ns PSEN pulse width tPLPH 60 - 3tCLCL−15 - ns PSEN to valid instruction in tPLIV - 25 - 3tCLCL−50 ns Input instruction hold after PSEN tPXIX 0 - 0 - ns Input instruction float after PSEN tPXIZ † - 15 - tCLCL−10 ns Address valid after PSEN tPXAV † 20 - tCLCL−5 - ns Address to valid instruction in tAVIV - 65 - 5tCLCL−60 ns Address float to PSEN tAZPL 5 - 5 - ns † Interfacing the GMS90 series to devices with float times up to 20 ns is permissible. This limited bus contention will not cause any damage to port 0 Drivers. 40 Dec. 1998 Ver 3.0 GMS90 Series AC Characteristics for GMS90 series (40MHz) External Data Memory Characteristics at 40 MHz Clock Parameter Symbol Variable Clock 1/tCLCL = 3.5 to 40MHz Min. Max. Min. Max. Unit RD pulse width tRLRH 120 - 6tCLCL-30 - ns WR pulse width tWLWH 120 - 6tCLCL-30 - ns Address hold after ALE tLLAX2 10 - tCLCL-15 - ns RD to valid data in tRLDV - 75 - 5tCLCL-50 ns Data hold after RD tRHDX 0 - 0 - ns Data float after RD tRHDZ - 38 - 2tCLCL-12 ns ALE to valid data in tLLDV - 150 - 8tCLCL-50 ns Address to valid data in tAVDV - 150 - 9tCLCL-75 ns ALE to WR or RD tLLWL 60 90 3tCLCL-15 3tCLCL+15 ns Address valid to WR or RD tAVWL 70 - 4tCLCL-30 - ns WR or RD high to ALE high tWHLH 10 40 tCLCL-15 tCLCL+15 ns Data valid to WR transition tQVWX 5 - tCLCL-20 - ns Data setup before WR tQVWH 125 - 7tCLCL-50 - ns Data hold after WR tWHQX 5 - tCLCL-20 - ns Address float after RD tRLAZ - 0 - 0 ns Advance Information (40MHz) External Clock Drive Parameter Symbol Variable Oscillator (Freq. = 3.5 to 40MHz) Min. Max. Unit Oscillator period tCLCL 25 285.7 ns High time tCHCX 10 tCLCL - tCLCX ns Low time tCLCX 10 tCLCL - tCHCX ns Rise time tCLCH - 10 ns Fall time tCHCL - 10 ns Dec. 1998 Ver 3.0 41 GMS90 Series tLHLL ALE tLLPL tAVLL tPLPH tLLIV tPLIV PSEN tPXAV tPXIZ tPXIX tAZPL tLLAX PORT 0 INSTR. IN A0-A7 A0-A7 tAVIV PORT 2 A8-A15 A8-A15 Figure 4. External Program Memory Read Cycle 42 Dec. 1998 Ver 3.0 GMS90 Series ALE tLHLL tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL tRHDZ tRLDV tLLAX2 tRHDX tRLAZ A0-A7 from RI or DPL PORT 0 DATA IN A0-A7 from PCL INSTR. IN tAVWL tAVDV PORT 2 P2.0-P2.7 or A8-A15 from DPH A8-A15 from PCH Figure 5. External Data Memory Read Cycle ALE tLHLL tWHLH PSEN tLLWL tWLWH WR tAVLL PORT 0 tQVWX tLLAX2 A0-A7 from RI or DPL tWHQX tQVWH DATA OUT A0-A7 from PCL INSTR. IN tAVWL PORT 2 P2.0-P2.7 or A8-A15 from DPH A8-A15 from PCH Figure 6. External Data Memory Write Cycle Dec. 1998 Ver 3.0 43 GMS90 Series VCC−0.5V 0.2VCC + 0.9 Test Points 0.2VCC − 0.1 0.45V AC Inputs during testing are driven at VCC−0.5V for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made a VIHmin for a logic ‘1’ and VILmax for a logic ‘0’. Figure 7. AC Testing: Input, Output Waveforms VOH − 0.1 VLOAD + 0.1 Timing Reference Points VLOAD VLOAD − 0.1 0.2VCC − 0.1 VOL + 0.1 For timing purposes a port pin is no longer floating when a 100mV change from load voltage occurs and begins to float when a 100mV change from the loaded VOH / VOL level occurs. IOL / IOH ≥ 20mA. Figure 8. Float Waveforms tCLCL VCC−0.5V 0.45V 0.7 VCC 0.2 VCC −0.1 tCHCX tCHCL tCLCX tCLCH Figure 9. External Clock Cycle 44 Dec. 1998 Ver 3.0 GMS90 Series OSCILLATOR CIRCUIT CRYSTAL OSCILLATOR MODE C2 DRIVING FROM EXTERNAL SOURCE N.C. XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14 C1 XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15 External Oscillator Signal XTAL2 P-LCC-44/Pin 20 P-DIP-40/Pin 18 M-QFP-44/Pin 14 XTAL1 P-LCC-44/Pin 21 P-DIP-40/Pin 19 M-QFP-44/Pin 15 C1, C2 = 30pF ±10pF for Crystals For Ceramic Resonators, contact resonator manufacturer. Figure 10. Recommended Oscillator Circuits Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. Dec. 1998 Ver 3.0 45 GMS90 Series OTP ROM Verification Characteristics ROM Verification Mode 1 Limit Values Parameter Symbol Unit Min. Max. Address to valid data tAVQV - 48tCLCL ENABLE to valid data tCLCL - 48tCLCL Data float after ENABLE tEHQZ 0 48tCLCL 1/tCLCL 4 6 Oscillator frequency P1.0-P1.7 ns MHz Address P2.0-P2.4 tAVQV Data Out PORT 0 tELQV tEHQZ P2.7 ENABLE Address: P1.0-P1.7 = A0-A7 P2.0-P2.5 = A8-A13 P3.4 = A14 Data: Input: P2.6-P2.7, PSEN = VSS ALE = VIH EA, RESET = VIH2 P0.0-P0.7 = D0-D7 Figure 11. OTP ROM Verification Mode 1 46 Dec. 1998 Ver 3.0 GMS90 Series EPROM CHARACTERISTICS The GMS97C5X, 97L5X are programmed by using a modified Quick-Pulse Programming TM algorithm. It differs from older methods in the value used for V PP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The GMS97C5X, 97L5X contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an manufactured by LGS. Table 11 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figure 12 and Figure 13. Figure 14 show the circuit configuration for normal program memory verification. Reading the Signature Bytes : The GMS97X51/52 signature bytes in locations 030 H and 031H, the GMS97X54/56/58 signature bytes in locations 030H and 060H. To read these bytes follow the procedure for EPROM verify, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: Device Location Contents Remarks GMS97X51 30H 31H E0H 73H Manufacturer ID Device ID GMS97X52 30H 31H E0H 71H Manufacturer ID Device ID GMS97X54 30H 60H E0H 54H Manufacturer ID Device ID GMS97X56 30H 60H E0H 56H Manufacturer ID Device ID GMS97X58 30H 60H E0H 58H Manufacturer ID Device ID Quick-pulse programming The setup for microcontroller quick-pulse programming is shown in Figure 13. Note that the GMS97C5X, 97L5X is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 12. The code byte to be programmed into that location is applied to port 0, RST, PSEN and pins of port 2 and 3 in Table 11 are held at the "Program Code Data" levels indicated in Table 11. The ALE/PROG is pulsed low 25 times(10 times for 97X54/56/58) as shown Figure 13. To program the encryption table, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence for addresses 0 through 1F H(3FH for 97X54/56/58), using the "Program Encryption Table" levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 25 pulses (10 pulses for 97X54/56/58) programming sequence using the "Pgm Security Bit" levels after one security bit is programmed, further programming of the code memory and Dec. 1998 Ver 3.0 47 GMS90 Series encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free glitches and overshoot. +5V VCC A0-A7 P1 A8-A13 P2.0 -P2.5 P0 A14 P3.4 1 RST 1 P3.6 1 P3.7 EA/VPP ALE/PROG PROGRAM DATA +12.75V ☞NOTE PSEN 0 XTAL2 P2.7 1 XTAL1 P2.6 1 4~6MHz VSS NOTE: GMS97X51/52: 100µs × 25 pulses to GND GMS97X54/56/58: 100µs × 10 pulses to GND Figure 12. Programming Configuration Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory location to be read is applied to ports 1 and 2 as shown in Figure 15. The other pins are held at the "Verify Code Data" levels indicated in Table 11. The contents of the address location will be emitted on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. 48 Dec. 1998 Ver 3.0 GMS90 Series Program Memory Lock Bits Lock Bit Protection Modes The two-level Program Lock system consists of 2 Lock bits and a 32-byte (64-byte for GMS97X54/ 56/58) Encryption Array which are used to protect the program memory against software piracy. Mode LB1 LB2 1 U U No program lock features 2 P U Further programming of the EPROM is disabled 3 P P Same as mode 2, also verify is Encryption Array: Protection Type disabled Within the EPROM array are 32 bytes (64 bytes for GMS97X54/56/58) of Encryption Array that U: unprogrammed, P: programmed are initially unprogrammed (all 1s). Every time that a byte is addressed during a verify, address lines are used to select a byte of the Encryption array. This byte is then exclusive-NORed (XNOR) with the code byte, creating an Encrypted Verify byte. The algorithm, with the array in the unprogrammed state (all 1s), will return the code in its original, unmodified form, It is recommended that whenever the Encryption Array is used, at least one of the Lock Bits be programmed as well. Program / Verify algorithms Any algorithm in agreement with the conditions listed in Table 11, and which satisfies the timing specifications is suitable. Table 11. EPROM programming modes RST PSEN ALE/ PROG EA/ VPP P2.7 P2.6 P3.7 P3.6 Read Signature 1 0 1 1 0 0 0 0 Program Code Data 1 0 0 VPP 1 0 1 1 Verify Code Data 1 0 1 1 0 0 1 1 Program encryption table 1 0 0 VPP 1 0 1 0 Program security bit 1 1 0 0 VPP 1 1 1 1 Program security bit 2 1 0 0 VPP 1 1 0 0 MODE Notes: 1. “0” = Valid low for that pin, "1" = valid high for that pin. 2. VPP = 12.75V ± 0.25V 3. VCC = 5V ± 10% during programming and verification. 4. ALE/PROG receives 25 (10 for GMS97X54/56/58) programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100us (± 10us) and high for a minimum of 10µs. Dec. 1998 Ver 3.0 49 GMS90 Series 25 PULSES In the GMS97X51/52 ALE/PROG Min. 10µs 100µs ±10 100µs ±10 Enlarged View 10 PULSES In the GMS97X54/56/58 ALE/PROG Figure 13. PROG Waveform +5V VCC A0-A7 P1 A8-A13 P2.0 -P2.5 A14 P3.4 1 RST 1 P3.6 1 P3.7 10kΩ PROGRAM DATA P0 EA/VPP 1 ALE/PROG 1 PSEN 0 XTAL2 P2.7 0 XTAL1 P2.6 1 4~6MHz VSS Figure 14. Program Verification 50 Dec. 1998 Ver 3.0 GMS90 Series EPROM Programming and Verification Characteristics TA= 21°C to 27°C, VCC= 5V + 10%, − 15%; VSS=0V; Limit Values Parameter Symbol Unit Min. Max. Programming supply voltage VPP 12.5 13.0 V Programming supply current IPP - 50 mA 1/tCLCL 4 6 MHz Address setup to PROG low tAVGL 48tCLCL - - Address hold after PROG tGHAX 48tCLCL - - Data setup to PROG tDVGL 48tCLCL - - Data hold after PROG tGHDX 48tCLCL - - P2.7 (ENABLE) high to VPP tEHSH 48tCLCL - - VPP setup to PROG tSHGL 10 - µs VPP hold after PROG tGHSL 10 - µs PROG width tGLGL 90 110 µs Address to data valid tAVQV - 48tCLCL - ENABLE low to data valid tELQV - 48tCLCL - Data float after ENABLE tEHQZ 0 48tCLCL - PROG high to PROG low tGHGL 10 - µs Oscillator frequency PROGRAMMING VERIFICATION ~ ~ ~ ~ P1.0-P1.7 P2.0-P2.5 P3.4 ADDRESS ADDRESS tAVQV ~ ~ ~ ~ PORT 0 DATA IN tDVGL tAVGL 25 or 10 PULSES tSHGL tGHGL DATA OUT tGHDX tGHAX ALE/PROG ~ ~ t G LG L tGHSL ~ ~ EA/VPP VPP TTL HIGH TTL HIGH tELQV tEHSH tEHQZ ~ ~ P2.7 (ENABLE) TTL HIGH Figure 15. EPROM Programming and Verification Dec. 1998 Ver 3.0 51 GMS90 Series Plastic Package P-LCC-44 (Plastic Leaded Chip-Carrier) 44PLCC UNIT: INCH 0.695 0.685 0.012 0.0075 0.021 0.013 0.032 0.026 0.656 0.650 0.695 0.685 0.050 BSC 0.630 0.590 min. 0.020 0.656 0.650 0.120 0.090 0.180 0.165 52 Dec. 1998 Ver 3.0 GMS90 Series Plastic Package P-DIP-40 (Plastic Dual in-Line Package) 40DIP UNIT: INCH 0.600 BSC 0.022 0.015 Dec. 1998 Ver 3.0 0.065 0.045 0.100 BSC 0.140 0.120 min. 0.015 0.200 max. 2.075 2.045 0.550 0.530 0-15° 0.012 0.008 53 GMS90 Series Plastic Package P-MPQF-44 (Plastic Metric Quad Flat Package) 44MQFP 13.45 12.95 UNIT: MM 0-7° 0.25 0.10 SEE DETAIL "A" 2.35 max. 0.45 0.30 0.80 BSC 0.23 0.13 2.10 1.95 10.10 9.90 13.45 12.95 10.10 9.90 1.03 0.73 1.60 REF DETAIL "A" 54 Dec. 1998 Ver 3.0 MASK ORDER & VERIFICATION SHEET GMS90X5X-GB Customer should write inside thick line box. 1. Customer Information 2. Device Information Package ROM size Company Name Application YYYY MM DD Vol. / Freq. 4K 44MQFP 8K 44PLCC 12MHz 5V 24MHz 16K Order Date 40MHz 40PDIP 24K Tel: Fax: 32K Name & Signature: Mask Data 16MHz ROM: 4K,8K ROM: 16,24,32K ROM Protection 3. Marking Specification 12MHz 3V Without Normal File Name: ( Super .HEX) Check Sum: Internet Chollian Hitel (Please check mark into 40PDIP or 44PLCC LGS GMS90 ➀ 5 ➁ -GB 44MQFP LGS 90 ➀ 5 ➁ -GB YYW W KOREA SIEMENS ’92 ➀ C: 5V L: 3V YYW W KOREA SIEM ENS ’92 ) ➁ RO M size 1: 4K 2: 8K 4: 16K 6: 24K 8: 32K Custom er’s part num ber 4. Delivery Schedule Quantity Date Customer Sample Risk Order MM DD pcs YYYY MM DD pcs 5. ROM Code Verification Verification D ate: YYYY This box is written after “5.Verification”. MM DD YYYY MM DD Approval Date: P lease confirm our verification data. Check Sum: Tel: Name & Signature: LG Confirmation YYYY Fax: I agree w ith your verification data and confirm you to m ake m ask set. Tel: Name & Signature: Fax: LG Semicon